Semiconductor device including a sense element and a main element, and current detector circuit using the semiconductor device

Abstract

False detection relating to overcurrent is prevented, and it is determined with no dead time whether or not the current of a main element is an overcurrent. By a gate signal indicating conductivity being applied to the gate of a sense element earlier than to a main element when the main element is caused to be conductive, and overshoot caused by a differential circuit of the sense element gate input portion being caused before current flows into the main element, it is possible to prevent false detection relating to overcurrent, and determine with no dead time whether or not the current of the main element is an overcurrent.

Claims

1. A semiconductor device comprising: a main element; a sense element for detecting current flowing through the main element on the same semiconductor substrate; a collector terminal of the main element; and a collector terminal of the sense element, wherein the collector terminal of the main element and the collector terminal of the sense element are connected to each other, wherein, when the main element is caused to be conductive, a gate signal indicating conductivity is applied to the gate of the sense element earlier than to the main element, wherein no collector current flows into the sense element during a time when the main element is not conductive, and wherein a signal indicating detection of the value of current flowing through the sense element is a current signal representing the current flowing through the main element.

2. The semiconductor device according to claim 1, wherein a gate signal to the main element, when the main element is caused to be conductive, is a gate signal provided to the sense element when the sense element is caused to be conductive, delayed by a delay circuit.

3. The semiconductor device according to claim 1, wherein the main element and sense element are provided adjacent on the semiconductor substrate.

4. The semiconductor device according to claim 3, wherein the main element and sense element are one power semiconductor element divided into two regions.

5. The semiconductor device according to claim 1, wherein the main element and sense element are IGBTs (Insulated Gate Bipolar Transistors).

6. The semiconductor device according to claim 1, wherein the main element is such that a plurality of basic elements are connected in parallel, and the sense element is formed of one unit element.

7. A semiconductor device comprising: a main element; a sense element for detecting current flowing through the main element on the same semiconductor substrate; a collector terminal of the main element; and a collector terminal of the sense element, wherein the collector terminal of the main element and the collector terminal of the sense element are connected to each other, wherein, when the main element is caused to be conductive, a gate signal indicating conductivity is applied to the gate of the sense element earlier than to the main element, wherein no collector current flows into the sense element during a time when the main element is not conductive, and wherein the predetermined period is at maximum the sum of the time from the gate signal causing the sense element to be conductive being provided to the sense element until the gate signal causing the main element to be conductive is provided to the main element and the time from the main element gate signal beginning to rise until reaching the threshold voltage of the main element.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a circuit diagram for showing a configuration example of a semiconductor device and current detector circuit according to the invention;

(2) FIG. 2 is a timing chart for illustrating an operation of the circuit shown in FIG. 1;

(3) FIG. 3 is a circuit diagram for showing another configuration example of the semiconductor device and current detector circuit according to the invention;

(4) FIG. 4 is a symbol diagram of a composite element 10;

(5) FIG. 5 is a diagram showing the configuration of the composite element 10;

(6) FIG. 6 is a diagram showing a configuration example of the composite element 10 on a semiconductor substrate;

(7) FIG. 7 is a diagram showing an example of a basic configuration of a circuit that carries out control and a protective action with respect to the composite element 10;

(8) FIG. 8 is a diagram showing a timing chart for when the composite element 10 shown in FIG. 7 changes from an off-state to an on-state; and

(9) FIG. 9 is a diagram showing an equivalent circuit of the composite element 10.

DETAILED DESCRIPTION

(10) Hereafter, referring to the drawings, a detailed description will be given of an embodiment of the invention.

Example 1

(11) FIG. 1 shows a configuration example of a semiconductor device and current detector circuit according to the invention. Also, FIG. 2 shows a timing chart thereof. The same reference signs are given to regions the same as in FIG. 7, and a detailed description will be omitted. Although the load 50, diode FWD, and power supply Vi of FIG. 7 are omitted from the drawing, they are assumed to be connected in the same way.

(12) The circuit shown in FIG. 1 has a composite element 1, a control circuit 2, a delay circuit 3, the resistor Rs (the resistance value thereof is also taken to be Rs), the reference voltage Vref, and a comparator 30. The composite element 1 is configured of the main element 100 and sense element 200, in the same way as the composite element 10 shown in FIG. 5, but unlike the composite element 10, the main element 100 and sense element 200 are of configurations having independent gate terminals G(M) and G(S) respectively. Herein, the main element 100 and sense element 200 themselves are made in the same way as the existing elements of the background art.

(13) The inventor, as a result of evaluating the composite element 1 wherein the main element 100 and sense element 200 each have independent gate terminals, has obtained the important finding that when the main element 100 and sense element 200 are in the vicinity of the same substrate, the operation of the sense element 200 is strongly affected by the operation of the main element 100, and even when the gate voltage of the sense element 200 exceeds the threshold voltage of the sense element 200, no collector current flows into the sense element 200 unless the main element 100 is conductive. In this case, it has also been confirmed that when a collector current flows into the main element 100 owing to a voltage the same as the gate voltage of the sense element 200 being applied to the gate of the main element 100, a collector current also flows into the sense element, and the composite element 1 performs an operation the same as that heretofore known as a composite element. The invention has been contrived based on these findings.

(14) The delay circuit 3 generates a gate signal Vg(M), which is a delay of a gate signal Vg(S) input from the control circuit 2 into the gate terminal G(S) of the sense element 200, and inputs the gate signal Vg(M) into the gate terminal G(M) of the main element 100.

(15) FIG. 2 shows a timing chart for when the composite element 1 of FIG. 1 is turned on. In FIG. 2, on the gate signal Vg(S) of the sense element 200 beginning to rise at a time t1, switching noise generated by a current responding to a rise of the voltage of the gate terminals G flowing through a differentiating circuit formed of an input capacitor Cies2 of the sense element 200 and the resistor Rs appears in a sense voltage Vs. As current is not yet flowing through the main element 100 at this time, there is no collector current flowing through the sense element 200, as heretofore described. Consequently, the original sense voltage Vs, which is proportional to the collector current Ic, is zero, and as it does not happen that any voltage that is not zero, which has sensed the collector current Ic, is superimposed on (added to) voltage generated by the switching noise, the sense voltage Vs at this time does not reach the reference voltage Vref. That is, it is possible to prevent a false detection of overcurrent due to switching noise.

(16) The gate signal Vg(M) to the main element 100 begins to rise at a time t3, later by a delay time tdly than the gate signal Vg(S) of the sense element 200. Then, on the gate signal Vg(S) reaching a threshold voltage Vth of the main element 100 at a time t4, the main element 100 switches from an off state to an state, the collector current of the main element 100 and sense element 200 starts to flow, and the sense voltage Vs indicates a voltage proportional to the collector current Ic.

(17) Provided that the delay time tdly is set so that the main element 100 switches from an off state to an on state after switching noise due to the rise in the gate voltage of the sense element 200 dies down, switching noise due to the rise in the gate voltage of the sense element 200 is not superimposed on the original sense voltage Vs, which is proportional to the collector current Ic, because of which it is possible to prevent a false detection of overcurrent. Furthermore, when it is envisaged that switching noise will become excessive because of the application, it is sufficient to deactivate overcurrent evaluation by the sense voltage Vs for a predetermined time from the time t1. Herein, it is sufficient that the predetermined time is, at maximum, (the delay time tdly+the time from the main element gate signal Vg(S) beginning to rise until reaching the threshold voltage Vth). Provided that this time can be secured, it is possible to prevent the effect of switching noise, and for dead time to be zero. When the time is longer, there is a possibility of dead time occurring.

(18) Also, when the main element 100 switches from an off state to an on state, the sense element 200 gate voltage has already risen, because of which no dead time with respect to current detection occurs.

Example 2

(19) FIG. 3 shows another configuration example of the semiconductor device and current detector circuit according to the invention. The configuration example is such that the delay circuit 3 of FIG. 1 is configured of a resistor Rdly. With this kind of simple configuration too, it is possible for the sense element 200 to be preceding and already realizing an on-state operation when the main element 100 switches from an off state to an on state. The timing chart at this time is practically the same as that shown in FIG. 2. Also, deactivating of overcurrent evaluation by the sense voltage Vs for a predetermined time from the time t1 can also be applied in the same way as Example 1.