Via for electrical contact passing through layers of optical waveguide in multilayer structure including electrical substrate and laminated layers of optical waveguide

Abstract

A structure is formed which is prepared as a via for electrical contact passing through layers of an optical waveguide, in a multilayer structure including an electrical substrate and the laminated layers of the optical waveguide. The surface of an electrode pad is plated with solder. The layers of the optical waveguide are formed above the portion plated with solder are removed to expose the portion plated with solder. A device is prepared having both a light-emitter or photoreceptor in optical contact with the optical waveguide, and a stud (pillar). The stud (pillar) is inserted into the portion in which layers of the optical waveguide have been removed, and the plated solder is melted to bond the electrode pad on top of the electrical substrate to the tip of the inserted stud (pillar).

Claims

1. A structure prepared as a via for electrical contact passing through layers of an optical waveguide, formed in a multilayer structure including an electrical substrate and the layers of the optical waveguide, the structure comprising: a surface of an electrode pad, the surface being plated with solder on top of the electrical substrate; and the layers of the optical waveguide removed above a top portion of the surface plated with the solder, wherein the top portion of the surface plated with the solder is exposed.

2. The structure of claim 1, further comprising a device including: a light-emitter or photoreceptor in optical contact with the optical waveguide; and a stud (pillar) long enough to reach the surface of the electrode pad plated with the solder.

3. The structure of claim 2, wherein the stud (pillar) is inserted into the top portion above which the layers of the optical waveguide have been removed.

4. The structure of claim 3, wherein the plated solder is melted to bond the electrode pad on the top of the electrical substrate to a tip of the inserted stud (pillar) by way of the via for electrical contact.

5. A structure prepared as a via for electrical contact passing through layers of an optical waveguide, formed in a multilayer structure including an electrical substrate and the layers of the optical waveguide, the structure comprising: a surface of an electrode pad, the surface being plated with solder on top of the electrical substrate; the layers of the optical waveguide removed above a top portion of the surface plated with the solder, exposing the top portion of the surface plated with the solder; and a device including: a light-emitter or photoreceptor in optical contact with the optical waveguide; and a stud (pillar) long enough to reach the surface of the electrode pad plated with the solder, wherein the stud (pillar) is inserted into the top portion above which the layers of the optical waveguide have been removed, wherein the plated solder is melted to bond the electrode pad on the top of the electrical substrate to a tip of the inserted stud (pillar) by way of the via for electrical contact.

6. The structure of claim 5, wherein the layers of the optical waveguide are formed by forming a laminated optical waveguide having a core interposed between an underclad layer and an overclad layer on the top of the electrical substrate.

7. The structure of claim 6, wherein the laminated optical waveguide is configured so the layers of the optical waveguide above the top portion of the surface plated with the solder are removed beforehand, and the top portion of the surface plated with the solder remains exposed during lamination.

8. An optical chip assembly having a structure prepared as a via for electrical contact passing through layers of an optical waveguide, formed in a multilayer structure including an electrical substrate and the layers of the optical waveguide, the optical chip assembly comprising; a surface of an electrode pad, the surface being plated with solder on top of the electrical substrate; the layers of the optical waveguide removed above a top portion of the surface plated with the solder to expose the top portion of the surface plated with the solder; an optical chip including: a light-emitter or photoreceptor in optical contact with the optical waveguide; and a stud (pillar) long enough to reach the surface of the electrode pad plated with the solder, wherein the stud (pillar) is inserted into the top portion above which the layers of the optical waveguide have been removed, wherein the plated solder is melted to bond the electrode pad on the top of the electrical substrate to a tip of the inserted stud (pillar), wherein the plated solder forms an electrical contact between the optical chip and the electrical substrate.

9. The optical chip assembly of claim 8, wherein the layers of the optical waveguide are formed by forming a laminated optical waveguide having a core interposed between an underclad layer and an overclad layer on the top of the electrical substrate.

10. The optical chip assembly of claim 9, wherein the laminated optical waveguide is configured so the layers of the optical waveguide above the top portion of the surface plated with the solder are removed beforehand, and the top portion of the surface plated with the solder remains exposed during lamination.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a diagram used to explain the formation of a via for electrical contact in the prior art. (Note that FIG. 1 and FIG. 2 are consecutive.)

(2) FIG. 2 is a diagram used to explain the formation of a via for electrical contact in the prior art. (Note that FIG. 1 and FIG. 2 are consecutive.)

(3) FIG. 3 is a diagram showing the configuration of the electrical contact between the device or optical chip and the electrical substrate in the prior art.

(4) FIG. 4 is a diagram used to explain the formation of a via for electrical contact in the present invention. (Note that FIG. 4 and FIG. 5 are consecutive.)

(5) FIG. 5 is a diagram used to explain the formation of a via for electrical contact in the present invention. (Note that FIG. 4 and FIG. 5 are consecutive.)

(6) FIG. 6 is a diagram showing the configuration of the electrical contact between the device or optical chip and the electrical substrate in the present invention.

(7) FIG. 7 is a diagram showing the results of an experiment conducted on the present invention.

DESCRIPTION OF EMBODIMENT

(8) FIG. 4 and FIG. 5 are diagrams used to explain the formation of a via for electrical contact in the present invention.

(9) Note that FIG. 4 and FIG. 5 are consecutive.

(10) Steps (1) through (6) can be the same as those in the prior art (FIG. 1 and FIG. 2).

(11) Therefore, to avoid redundancy, further explanation has been omitted.

(12) In the present invention, as shown in (7), a resist pattern is formed.

(13) In other words, a resist pattern is prepared over the electrode pad on top of the electrical substrate.

(14) In the present invention, as shown in (8), solder is formed on top of the electrode pad.

(15) In other words, solder is plated on the surface of the electrode pad in accordance with the resist pattern.

(16) The solder can be adjusted to any thickness using electroplating. The layer can be thin or thick.

(17) In this way, strong metal bonding can be obtained using solder.

(18) In the present invention, as shown in (9), the resist is stripped.

(19) In other words, the prepared resist pattern is removed.

(20) In the present invention, as shown in (10), the seed layer is etched.

(21) The rest of the process involves the formation of a multilayer structure including the electrical substrate and the laminated layers of the optical waveguide.

(22) In the present invention, as shown in (11), the layers of the optical waveguide are formed.

(23) In other words, the layers of the optical waveguide are formed on top of the electrical substrate, covering the portion plated with solder.

(24) In the present invention, as shown in (12), a portion of the layers of the optical waveguide is removed, and a via hole is formed.

(25) In other words, the layers of the optical waveguide over the portion plated with solder are removed to expose the portions plated with solder.

(26) The seed layer formation and plating steps in the prior art are eliminated.

(27) There is, of course, no chemical damage to the optical waveguide.

(28) Instead of the “filled via” of the prior art, a so-called “conformal via” is formed in the present invention.

(29) Because the space inside the conformal via can be utilized, the distance between the chip and the mirror after bonding can be reduced as described below.

(30) Finally, in the present invention, as shown in (13), a portion of the layers of the optical waveguide is removed, and a mirror is installed.

(31) FIG. 6 is a diagram showing the configuration of the electrical contact between the device or optical chip and the electrical substrate in the present invention.

(32) The device or optical chip has a stud (pillar), and the stud (pillar) is bonded to the solder plated on the surface of the electrode pad on top of the electrical substrate.

(33) The stud (pillar) may be inserted into the portion in which the layers of the optical waveguide have been removed, and the plated solder melted to bond the electrode pad on the electrical substrate to the tip of the inserted stud (pillar).

(34) Here, a strong metal bond using solder has been realized in a specific structure.

(35) The space in the conformal via can be utilized to accommodate the stud (pillar) and significantly reduce the distance between the chip and mirror after bonding.

(36) In order to realize this structure, the device may be provided with both a light-emitter or photoreceptor in optical contact with the optical waveguide, and a stud (pillar) long enough to reach the electrode plated with solder on top of the electrical substrate.

(37) In other words, the floor of the conformal via is utilized.

(38) For such a purpose, the shape and other characteristics of the “stud (pillar)” can be broadly interpreted by those skilled in the art to include many different modifications and applications.

(39) The thickness of the plated solder can be adapted with respect to the thickness of the layers of the formed optical waveguide and the length (height) of the prepared stud (pillar).

(40) The conformal via may conceivably be filled with solder by filling the conformal via with solder paste to a thickness close to that of a filled via.

(41) However, when bonding is performed using molten solder, there is a risk that the solder will overflow (due to thermal expansion, etc.) and cause a short.

(42) Also, it is not easy to supply the appropriate amount of solder paste to the via.

(43) Therefore, the use of plating is superior.

(44) The layers of the optical waveguide may be formed by laminating a laminated waveguide (having a core interposed between an underclad layer and an overclad layer) on top of the electrical substrate.

(45) Also, the laminated optical waveguide may be configured so the layers of the optical waveguide above the portion plated with solder are removed beforehand, and the portion plated with solder remains exposed during lamination.

(46) The use of a laminated optical waveguide can reduce steps (11) and (12) in the present invention to a single step and shorten the process.

(47) Laminated optical waveguides are available which are thinner than laminating an underclad, then a core, and then an overclad which are a photocurable resin (etc.).

(48) When a thin laminated optical waveguide is used, the solder plating can also be thinner.

(49) When a photocurable resin is laminated, the solder plating can be thicker.

(50) When solder is melted and bonded, the solder may flow once it melts into the form shown in the diagram due to surface tension.

(51) This alone can cause one to say the structure of the present invention is itself novel.

(52) It is clear from the plot distribution in the graph that the improvement to insertion loss is good.

(53) FIG. 7 is a diagram showing the results of an experiment conducted on the present invention.

(54) Solder plating (100% Sn here) was formed over the surface of the electrode pad on top of the electrical substrate, and gold studs (bumps) were mounted on top to obtain a good metal bond.

(55) The resistance per bump was dozens of mΩ.

(56) When gold bonding was performed, the resistance per bump was several Ω.