Process for forming graphene layers on silicon carbide

Abstract

A process for forming graphene, includes: depositing at least a first and a second metal onto a surface of silicon carbide (SiC), and heating the SiC and the first and second metals under conditions that cause the first metal to react with silicon of the silicon carbide to form carbon and at least one stable silicide. The corresponding solubilities of the carbon in the stable silicide and in the second metal are sufficiently low that the carbon produced by the silicide reaction forms a graphene layer on the SiC.

Claims

1. A process for forming graphene, comprising: depositing at least two metals onto a surface of silicon carbide (SiC), the at least two metals comprising at least one first metal and at least one second metal; and heating the SiC and the first and second metals under conditions that cause the at least one first metal to react with silicon of the silicon carbide to form carbon and at least one stable silicide, wherein corresponding solubilities of the carbon in the at least one stable silicide and in the at least one second metal are sufficiently low that the carbon produced by the silicide reaction forms a graphene layer disposed between the at least one stable silicide and the remaining SiC, and wherein the at least one second metal is chosen such that the corresponding solubility of carbon in the at least one second metal is lower than the corresponding solubility of carbon in the at least one stable silicide.

2. The process of claim 1, wherein the first at least one metal is nickel, and the second at least one metal is copper.

3. A process for forming graphene layers, comprising: depositing one or more layers, collectively substantially composed of nickel and copper, onto a surface of silicon carbide; heating the resulting structure to cause at least a portion of the nickel to react with a corresponding portion of the silicon carbide to form a carbon and a metallic layer comprising a nickel silicide and any remaining unreacted nickel and copper, wherein the carbon is in a form of a graphene layer disposed between remaining silicon carbide and the metallic layer.

4. The process of claim 3, comprising removing the metallic layer to expose the underlying graphene layer.

5. The process of claim 1, wherein the silicon carbide is in the form of a thin film disposed on a substrate.

6. The process of claim 5, wherein the substrate is a silicon substrate.

7. The process of claim 6, wherein the thin film of SiC is in the form of mutually spaced islands of silicon carbide disposed on the silicon substrate.

8. The process of claim 5, comprising removing at least a portion of the substrate under the silicon carbide islands to free a corresponding portion of the mutually spaced islands of silicon carbide.

9. The process of claim 1, wherein the graphene layer is part of a micro-electro-mechanical systems (MEMS) transducer.

10. The process of claim 1, wherein the silicon carbide is substantially amorphous.

11. The process of claim 1, wherein said heating step is performed in an inert gas atmosphere.

12. The process of claim 1, wherein said heating step is performed under vacuum.

13. The process of claim 12, wherein said vacuum has a pressure of about 10.sup.−4 to 10.sup.−3 mbar.

14. The process of claim 1, wherein said heating step comprises includes heating the SiC and the first and second metals to a temperature of at least 800° C.

15. The process of claim 1, wherein said heating step comprises includes heating the SiC and the first and second metals to a temperature of about 1000° C.

16. The process of claim 15, wherein said heating step comprises heating the SiC and the first and second metals to a temperature of about 1050° C.

17. The process of claim 1, wherein said heating step is a rapid thermal processing (RTP) heating step.

18. A structure comprising one or more layers of graphene formed by the process of claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Some embodiments of the present invention are hereinafter described, by way of example only, with reference to the accompanying drawings, wherein:

(2) FIG. 1 is a scanning electron microscope image of a SiC cantilever structure attached to a silicon wafer;

(3) FIG. 2 is a flow diagram of a process for forming graphene layers in accordance with some embodiments of the present invention;

(4) FIG. 3 is a set of schematic cross-sectional side views of a wafer at different stages of the process of FIG. 2;

(5) FIG. 4 is a photograph of a full wafer of graphene devices produced using the process of FIGS. 2 and 3;

(6) FIG. 5 is a set of three cross-sectional transmission electron microscopy (XTEM) images of a sample processed in accordance with the process of FIG. 2 at successively higher magnifications and showing graphene layers disposed between a SiC layer and a metallic capping layer;

(7) FIGS. 6 and 7 are graphs of sheet resistance as a function of electrical current for a two-sheet graphene layer and a Ni—Cu film, respectively;

(8) FIGS. 8 and 9 are schematic diagrams illustrating an arrangement for performing adhesion energy measurements on graphene layers formed by the process of FIG. 2;

(9) FIG. 10 is a graph of the energy release rate for debonding (layer separation) of an interface adjacent to the graphene layer, as measured using the arrangement shown in FIG. 8; and

(10) FIG. 11 is a graph representing the defect densities of graphene layers formed by the process of FIG. 2 (as assessed using Raman spectroscopy) as a function of the initial thickness of the Ni metal layer of each sample.

DETAILED DESCRIPTION

(11) Described herein are new processes for forming a graphene layer between SiC and a combination of at least two metals, including at least one first metal and at least one second metal, the process including heating the SiC and the first and second metals under conditions that cause the at least one first metal to react with silicon of the silicon carbide to form at least one stable silicide, and wherein the corresponding solubilities of carbon in the at least one stable silicide and in the at least one second metal are sufficiently low that carbon produced by the silicide reaction forms a graphene layer between the SiC and the overlying metal/silicide. The at least one second metal may be chosen such that the corresponding solubility of carbon in the at least one second metal is lower than the corresponding solubility of carbon in the at least one stable silicide.

(12) In some embodiments, the combination of at least two metals is a combination of Ni and Cu. In some embodiments, the SiC is amorphous. In other embodiments, the SiC is crystalline. In some embodiments, the SiC is in the form of a thin film of SiC supported on a substrate, which may or may not be a silicon substrate. In some embodiments, the SiC is in the form of a thin film of 3C—SiC on a (100) or (111) Si surface. The thin film of SiC can be formed on a Si wafer using a method and apparatus as described in WO2010/091473, entitled “A chemical vapour deposition system and process”, the entirety of which is hereby incorporated by reference.

(13) Additionally, the thin film of SiC can be patterned and etched using a process such as that described in Australian Provisional Patent Application No. 2013902931, entitled “A silicon carbide etching process” (the entirety of which is hereby incorporated by reference) to form micromachined structures (which may be freestanding) that can be used as sensors and/or transducers. FIG. 1 is a scanning electron microscope image of such a structure.

(14) In some embodiments, a combination of Ni and Cu is deposited onto the surface of the SiC (e.g., by sputtering or thermal evaporation). In some embodiments, the Ni is deposited first, onto the SiC surface, and the Cu is then deposited onto the Ni. In some embodiments, the SiC is patterned prior to the deposition of these metals to form mutually spaced SiC islands on the substrate.

(15) In the described embodiments, the resulting structure is then heated in a substantially inert ambient (e.g., a vacuum of 10.sup.−3 mbar or less, preferably between 10.sup.−4 mbar and 10.sup.−3 mbar so that some oxygen is present, or an inert gas atmosphere such as argon) to a temperature of at least 800° C., with the best results obtained at a temperature around 1000° C. so that the Ni undergoes a solid phase reaction with the underlying SiC. Using this method, the best quality graphene layers have been found to be formed at, temperatures of about 1050° C. Under these conditions, two reaction products are formed: a Nickel Silicide (whose stoichiometry depends on temperature) and elemental Carbon (C). The low solubility of C in the silicide causes a thin layer or film of carbon to form, in the form of one or more sheets of graphene. The presence of Cu further decreases the overall solubility of C, and is found to increase the crystallinity of the graphene.

(16) As shown in FIGS. 3 and 5, the graphene layer forms between the SiC layer and a metal layer constituted by the silicide produced by the reaction and any remaining portion of the original metals. This metal layer can then be removed (e.g., by wet etching) to expose the graphene. Because the graphene forms directly on the SiC, the described processes avoid any need for manual transfer of the graphene film, which is a significant limitation of other approaches, and facilitate making electrical contact to the graphene. In practice, graphene films formed by the processes described herein are found to have significantly improved electrical conductivity relative to transferred graphene films, and, when used in SiC/graphene transducers as described above, effectively do not change the resonance frequency of such transducers.

(17) In one example, as shown in the flow diagram of FIG. 2 and the schematic cross-sectional side views of FIG. 3, the process begins at step 202 by receiving a composite substrate or wafer consisting of a thin film 302 of epitaxial SiC on a single-crystal silicon substrate 304 (in this example, being of (111) orientation) (FIG. 3A). At step 204, the SiC film 302 is patterned using standard photolithography. That is, by depositing a layer of photoresist 306 over the sample, and exposing selected regions of the photoresist 306 to UV light (FIG. 3B), and then developing the photoresist 306 so that only selected regions 310 of the photoresist remain on the sample, as shown in FIG. 3C. Subsequently, the exposed regions of the SiC layer 302 are removed by etching to form mutually spaced islands 308 of SiC capped by the photoresist 310 (FIG. 3D). The remaining photoresist 310 is then stripped from the sample, leaving only the SiC islands 308 as shown in FIG. 3D.

(18) At step 206, a thin metal alloy layer 312 of Cu and Ni is deposited over the sample, as shown in FIG. 3E. At step 208, the entire sample is heated to a temperature of about 1050° C. for a period of 1 hour in a substantially inert ambient (e.g., under a partial vacuum of 10.sup.−4-10.sup.−3 mbar), which causes a layer of graphene 314 to form at the interface between the SiC and the metal alloy layer 312, as described above and shown in FIG. 3F.

(19) At step 210, the resulting metallic layer 316 (consisting of any remaining alloy and silicide formed by reaction of at least one of the metals with the SiC) is removed from the sample (in this example, by a Freckle etch) to expose the graphene 314 and produce the structure shown in FIG. 3G. Finally, at step 212, a further patterning step and etch step can be used to selectively remove a portion of the silicon substrate 304 under a portion of each SiC/graphene island to partially free those parts and form suspended structures, 318 as shown in FIG. 3H (which may be, for example, linear cantilevers, or more complex structures such as those shown in FIGS. 1 and 4). Alternatively, the structures may be completely released by etching all of the substrate 304 under the structures to form singulated structures of graphene on SiC.

(20) Table 1 compares the results of Hall effect measurements performed on (i) graphene films on SiC by the processes described herein, and (ii) the bare SiC film, demonstrating that by adding the graphene film to the SiC film, the resulting bilayer structure exhibits orders of magnitude lower sheet resistance (R.sub.s) and a 10-fold increase in charge carrier mobility (μ). In this example, the graphene was formed on SiC(111) by heating the sample to a temperature of about 1050° C. in a vacuum furnace for a period of about 1 hour at a pressure of about 10.sup.−3 mbar.

(21) TABLE-US-00001 TABLE 1 Graphene on crystalline SiC Crystalline SiC only Sheet Resistance Rs 2.1 × 10.sup.2 Ω/□ 7.1 × 10.sup.4 Ω/□ Hole Mobility μ.sub.H 340 cm.sup.2 V.sup.−1 s.sup.−1 36 cm.sup.2 V.sup.−1 s.sup.−1

(22) FIG. 5 includes three cross-sectional transmission electron microscopy (XTEM) images at different magnifications of a sample similar to that described above, but where the SiC was of (100) orientation and was heated to a temperature of about 1100° C. for about 1 hour at a pressure of 10.sup.−3 mbar. The images show the underlying silicon substrate 502, the SiC film 504, and an overlying gold layer 506 deposited as part of the sample preparation for TEM, and, in the highest resolution image, the graphene layer 508, in this example being in the form of a double sheet having a thickness of about 0.9 nm.

(23) FIG. 6 is a graph of the vertical 602 and horizontal 604 sheet resistance of the ˜1 nm graphene layer (of two sheets) 508 shown in FIG. 5 as a function of the electric current passing through it. For the purpose of comparison, FIG. 7 is a corresponding graph of vertical 702 and horizontal 704 sheet resistance, but for a Ni—Cu film having a much greater thickness of about 20 nm. Considering that the measured sheet resistances of these two layers are similar, but that the metal film is more than an order of magnitude thicker, it is immediately apparent that the resistivity of the graphene is vastly greater than that of the (oxidised) metal film. Indeed, the resistivity of the graphene layer is calculated to be about 2×10.sup.−8 Ω-m, whereas the resistivity of the metal film is about 4×10.sup.−7 Ω-m (which is approximately equal to the resistivity of titanium). Considering the atomic scale thickness of the two-sheet graphene layer, it will be apparent that its resistivity is remarkably low. For example, even if it was possible to deposit a uniform ˜1 nm thick layer of gold, one of the most electrically conductive metals, its resistivity would be at least 10 times greater than the resistivity of bulk gold due to spatial confinement below the electron mean free path. Any other metal would suffer from partial or total oxidation. Consequently, it will be apparent that the properties of the graphene layers produced by the processes described herein are particularly advantageous.

(24) Finally, the relatively insensitivity of the graphene sheet resistance to electrical current evident from the data in FIG. 6 suggests that the graphene layer suffers far less from Joule heating than the oxidised metal layer of FIG. 7 (as suggested by the positive slope of the sheet resistance data in that figure). Consequently, conductive sheets of graphene formed by the processes described herein may have drastically higher thermal conduction and improved reliability relative to metal layers having similar physical dimensions. In other words, the described graphene layers may enable unprecedented levels of miniaturisation for certain applications.

(25) As expected, graphene layers formed in situ by the processes described herein have superior adhesion to graphene layers transferred from graphite. FIG. 8 is a schematic diagram illustrating the configuration of a four-point bending test that is used to measure the adhesion energy of graphene layer 802 sandwiched between at least one top layer 804 and at least one bottom layer 806. The application of generally opposing forces to the outer layer 804, 806, as represented by the arrows 808 in FIG. 8, eventually cause the topmost layer(s) 804 to crack, as shown in FIG. 9, and the separation of the graphene layer 807 from the layers 804, 806 immediately adjacent can be measured to quantitatively assess the adhesion energy.

(26) FIG. 10 is a graph indicating the adhesion energy of a graphene layer formed as described above (SiC(111), furnace heating at 1100 C for 1 hour), as calculated from the applied mechanical load to obtain a steady-state interfacial crack propagation or “displacement” using the general arrangement shown in FIGS. 8 and 9. In this example, the adhesion energy of the graphene (capped by a 500 nm Si film deposited by PVD) to the SiC film is expected to be much higher than the adhesion energy of a graphene film grown ex situ and subsequently transferred to an SiO.sub.2 substrate has been measured to be around 0.45 m.sup.−2, as described in S. P. Koenig, N. G. Boddeti, M. L. Dunn, and J. S. Bunch, Nature Nanotechnology 6 (543-546) (2011).

(27) Although graphene layers can be formed in this general manner using only Ni on the SiC surface, the inventors have determined that the addition of at least one second metal in which the solubility of carbon is very low (e.g., Cu) improves the crystallinity of the graphene layers as measured by Raman spectroscopy.

(28) FIG. 11 is a graph representing the quality of graphene layers formed using the processes described herein as a function of the thickness of the initial metal layer deposited on the SiC, comparing also: (i) the use of (100) and (111) Si substrates, (ii) the use of nickel only and nickel+copper as the initial metal layer, and (iii) the use of conventional furnace processing with rapid thermal processing (RTP).

(29) In this example, the quality of the graphene layers was assessed using Raman spectroscopy, specifically using a measure known in the art as “the I.sub.D/I.sub.G ratio” which is a measure of the defect density of the graphene layers, as described in A. C. Ferrari and D. M. Basko, Nature Nanotechnology 8, 235 (2013). Accordingly, a perfect graphene layer would have an I.sub.D/I.sub.G ratio approaching zero.

(30) The data in FIG. 11 shows that, while there is only a relatively weak dependence on the metal film thickness, the defect density in the graphene layers is reduced by about a factor of two when the metal film includes both nickel and copper, rather than nickel alone. Additionally, the data demonstrate that the quality of the graphene layers is degraded when grown on SiC films formed on silicon substrates having a (111) orientation, relative to those where the silicon substrates have a (100) orientation.

(31) Finally, the data demonstrate that the quality of the graphene layers is vastly improved (in this example, by about a factor of four (symbol 1102)) when a sample is heated using rapid thermal processing (in this example, 4 minutes at 1100° C.) rather than furnace heating. Additionally, the uniformity of the resulting graphene layers is improved when formed using RTP, as is apparent from the error bars on the corresponding symbol in FIG. 5 being smaller than the size of the symbol used to represent the data point.

(32) Finally, the processes described herein provide the first viable route to the microfabrication of graphene/SiC devices on silicon at the wafer scale.

(33) Compared to the prior art method of growing graphene layers by CVD on metal foils, the described processes do produce graphene layers of lower quality. The substrate surface after the reaction is significantly rougher than prior to the reaction (˜3 nm RMS roughness vs ˜40 nm RMS roughness). However, the impact of this roughness depends upon the application. For example, the roughness should not be relevant for manufacturing transducers, but may be more relevant for other electronic applications.

(34) The described processes form graphene at relatively low temperatures compared to sublimation processes (˜1000° C. versus 1300° C. for the latter), and can yield high quality graphene on epitaxial SiC films.

(35) The described processes are scalable for producing graphene layers consisting of one or more graphene sheets for micro and nano-devices on a mass production level. Graphene/SiC transducer devices have been proven on wafers that can be manufactured with standard semiconducting processing methodologies. Furthermore, no additional photo-lithography (self-aligned patterning of graphene) is needed, resulting in low processing costs.

(36) Graphene layers produced by the described processes are particularly applicable to advanced technologies where graphene has a strong advantage, including chemical and mechanical sensing, and optical applications where its non-linear optics, in particular saturable absorption properties, outperform rival technologies at a substantially lower cost. The production of graphene devices using the described processes is self-aligned, and can be scaled up to large wafer sizes. As a process technology, the described processes can be utilised and further developed across a wide range of applications, including graphene micro-transducers (a subset of MEMS), and non-linear optical devices.

(37) Many modifications will be apparent to those skilled in the art without departing from the scope of the present invention.