Cold start DC/DC converter

Abstract

A DC/DC converter comprising a first charge pump circuit including first MOS transistors including first depletion MOS transistors, an oscillating circuit connected to the charge pump circuit only at the gates of some at least of the first MOS transistors, including the first depletion MOS transistors.

Claims

1. A DC/DC converter comprising: a first charge pump circuit comprising: first MOS transistors including first depletion MOS transistors, a first terminal intended to receive a first voltage, a second terminal intended to supply a second voltage, a least one capacitor, at least one conduction path between the first terminal and the second terminal only comprising some of said first depletion MOS transistors in series, and at least one conduction path between the first terminal and an electrode of the capacitor comprising only one of the first depletion MOS transistors or only some of said first depletion MOS transistors in series, a second charge pump circuit comprising: second MOS transistors including second depletion MOS transistors, and a third terminal intended to receive the first voltage and a fourth terminal intended to supply a third voltage of a sign opposite to that of the first voltage, and wherein the oscillating circuit is powered between the second voltage and the third voltage, and an oscillating circuit connected to: the charge pump circuit only at the gates of at least some of the first MOS transistors including the first depletion MOS transistors, the second charge pump circuit only at the gates of at least some of the second MOS transistors including the second depletion MOS transistors, wherein the oscillating circuit is supplied with the second voltage.

2. The converter of claim 1, wherein the oscillating circuit comprises a ring oscillator.

3. The converter of claim 1, wherein the oscillating circuit is powered with the first voltage.

4. The converter of claim 3, comprising a third charge pump circuit only comprising third enhancement MOS transistors, the oscillating circuit being further connected to the third charge pump circuit only at the gates of some at least of the third enhancement MOS transistors, the third charge pump circuit comprising a fifth terminal intended to receive the first voltage and a sixth terminal intended to supply a fourth voltage of same sign as the first voltage.

5. The converter of claim 4, further comprising a switching circuit capable of successively powering the oscillating circuit with the second voltage and with the fourth voltage.

6. An electronic power recovery system comprising a transducer capable of supplying a voltage from a power source and the converter of claim 1, the charge pump circuit receiving said voltage.

7. A DC/DC converter comprising: a first charge pump circuit comprising: first MOS transistors including first depletion MOS transistors, a first terminal intended to receive a first voltage, at least one capacitor, and at least one conduction path between the first terminal and an electrode of the capacitor comprising only one of the first depletion MOS transistors or only some of said first depletion MOS transistors in series, a third charge pump circuit only comprising third enhancement MOS transistors, an oscillating circuit connected to: the first charge pump circuit only at the gates of at least some of the first MOS transistors including the first depletion MOS transistors, the third charge pump circuit only at the gates of some at least of the third enhancement MOS transistors, wherein: the oscillating circuit is powered with the first voltage, and the third charge pump circuit comprising a fifth terminal intended to receive the first voltage and a sixth terminal intended to supply a fourth voltage of same sign as the first voltage, and a switching circuit capable of successively powering the oscillating circuit with a second voltage and with the fourth voltage.

8. The converter of claim 7, wherein the oscillating circuit comprises a ring oscillator.

9. The converter of claim 7, wherein the first charge pump circuit is intended to supply the second voltage and wherein the oscillating circuit is supplied with the second voltage.

10. The converter of claim 9, wherein the first charge pump circuit further comprises a second terminal intended to supply the second voltage and wherein the first charge pump circuit comprises at least one conduction path between the first terminal and the second terminal only comprising some of said first depletion MOS transistors in series.

11. The converter of claim 10, comprising a second charge pump circuit comprising second MOS transistors including second depletion MOS transistors, the oscillating circuit being connected to the second charge pump circuit only at the gates of at least some of the second MOS transistors including the second depletion MOS transistors, the second charge pump circuit comprising a third terminal intended to receive the first voltage and a fourth terminal intended to supply a third voltage of a sign opposite to that of the first voltage, and wherein the oscillating circuit is powered between the second voltage and the third voltage.

12. An electronic power recovery system comprising a transducer capable of supplying a voltage from a power source and the converter of claim 7, the charge pump circuit receiving said voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows in the form of a block diagram an embodiment of cold start DC/DC converter;

(2) FIG. 2 is a more detailed electric diagram of an embodiment of the converter of FIG. 1;

(3) FIG. 3 is an electric diagram of a detail of an element of the converter of FIG. 2;

(4) FIG. 4 shows a curve of the variation of the drain current of a depletion MOS transistor according to the gate-source voltage;

(5) FIGS. 5 and 6 are electric diagrams of a portion of the converter of FIG. 2 at two successive steps of operation of the converter;

(6) FIG. 7 shows curves of the variation of the transformation ratio of the converter according to the voltage received by the converter respectively for the converter of FIG. 2 and for a converter with enhancement transistors;

(7) FIGS. 8, 9, and 10 are electric diagrams of other embodiments of a cold start DC/DC converter;

(8) FIG. 11 shows curves of the variation of the transformation ratio of the converter according to the voltage received by the converter respectively for the converter of FIG. 10 and for a converter with enhancement transistors;

(9) FIGS. 12 and 13 are electric diagrams of other embodiments of a cold start DC/DC converter;

(10) FIG. 14 shows curves of the variation of the transformation ratio of the converter according to the voltage received by the converter respectively for the converter of FIG. 13 and for a converter with enhancement transistors;

(11) FIGS. 15 and 16 are electric diagrams of other embodiments of a cold start DC/DC converter; and

(12) FIG. 17 shows an embodiment of a power recovery system

DETAILED DESCRIPTION

(13) The same elements have been designated with the same reference numerals in the different drawings. For clarity, only those elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, the structure of a transducer is well known by those skilled in the art and has not been described in detail. Unless otherwise specified, expressions “approximately”, “substan-tially”, and “in the order of” mean to within 10%, preferably to within 5%. Further, a signal which alternates between a first constant state, for example, a low state, noted “0”, and a second constant state, for example, a high state, noted “1”, is called “binary signal”. The high and low states of binary signals of a same electronic circuit may be different. In particular, the binary signals may correspond to voltages or to currents which may not be perfectly constant in the high or low state. In the following description, the source and the drain of a MOS transistor are called “power terminals” of the MOS transistor. Further, in the present description, term “connected” is used to designate a direct electric connection, with no intermediate electronic component, for example, by means of a conductive track, and term “coupled” or term “linked” will be used to designate either a direct electric connection (then meaning “connected”) or a connection via one or a plurality of intermediate components (resistor, capacitor, etc.).

(14) FIG. 1 shows in the form of a block diagram an embodiment of a converter 5 comprising:

(15) a charge pump circuit 10 (Charge Pump) receiving a voltage V.sub.e at an input node IN and supplying a voltage V.sub.s to an output node OUT; and

(16) an oscillating circuit 11 supplying at least one digital control signal φ to charge pump circuit 10.

(17) Oscillating circuit 11 may comprise:

(18) an oscillator 12 (Oscillator) supplying at least one clock signal clk; and

(19) an interface circuit 14 (Buffer) receiving clock signal clk and supplying digital control signal φ.

(20) In the present embodiment, oscillator 12 and interface circuit 14 are powered with input voltage V.sub.e and are further connected to a source of a reference potential GND, for example, the ground, which is taken to be equal to 0 V in the following description.

(21) Voltage V.sub.e is a DC voltage, capable of yawing over time, supplied by an electronic circuit, not shown. It may be the voltage supplied by a transducer capable of transforming into electric power another form of power, for example, thermal power, mechanical power, or radiative power. Voltage V.sub.e may be lower than 300 mV, for example, in the range from 100 mV to 200 mV. In the following description, voltages V.sub.e and V.sub.s are reference to ground GND.

(22) Voltage V.sub.s supplied by charge pump circuit 10 is equal to the product of voltage V.sub.e and of a transformation ratio k, positive or negative, which depends on the structure of charge pump circuit 10. Terminal OUT may be connected to a dissipative load, for example, for the powering of an electronic device, and/or to a capacitive load, for example, for power storage.

(23) Clock signal clk and control signal φ are binary signals. Control signal φ alternates between voltage V.sub.e and 0 V.

(24) Interface circuit 14 is capable of shaping clock signal clk to supply control signal φ in a form adapted to charge pump circuit 10. As a variation, it is possible for interface circuit 14 not to be present, and clock signal clk may then directly be used as a control signal.

(25) According to an embodiment, charge pump circuit 10 comprises depletion MOS transistors having their gates controlled by control signal φ. A depletion transistor is a transistor for which a conductive channel is present between the source and the drain even when the gate is at 0 V. The threshold voltage of an N-channel depletion MOS transistor is negative.

(26) Charge pump circuit 10 comprises at least one capacitor. The conduction path or the conduction paths between input node IN and one of the capacitor electrodes is only formed by the channels of depletion MOS transistors having their gates controlled by the oscillating circuit. Control signals φ supplied by interface circuit 14 are only supplied to MOS transistor gates. This enables to decrease the current to be supplied by interface circuit 14 and advantageously enables to ensure that the charge pump circuit operates during a cold start even if voltage V.sub.e is low.

(27) Preferably, at least one conduction path between input node IN and output node OUT is only formed by the channels of depletion MOS transistors having their gates controlled by the oscillating circuit. This advantageously enables, in a cold start, converter 10 to provide a voltage V.sub.s different from 0 V as soon as voltage V.sub.e is different from 0 V.

(28) According to an embodiment, charge pump circuit 10 only comprises MOS transistors and at least one capacitor. According to an embodiment, all the MOS transistors of charge pump circuit 10 are depletion MOS transistors. According to another embodiment, charge pump circuit 10 comprises at least one depletion MOS transistor and enhancement MOS transistors.

(29) FIG. 2 shows a more detailed embodiment of converter 5 of FIG. 1 where oscillator 12 is a ring oscillator, where charge pump circuit 10 is a voltage doubler and where interface circuit 14 comprises inverters.

(30) In this embodiment, charge pump circuit 10 comprises four N-channel depletion MOS transistors T.sub.1, T.sub.2, T.sub.3, and T.sub.4 and one capacitor C.sub.1. A first power terminal of transistor T.sub.1 is connected to input node IN and the second power terminal of transistor T.sub.1 is connected to a first electrode of capacitor C.sub.1. The gate of transistor T.sub.1 receives a first control signal φ.sub.1. A first power terminal of transistor T.sub.2 is connected to input node IN and the second power terminal of transistor T.sub.2 is connected to the second electrode of capacitor C.sub.1. The gate of transistor T.sub.2 receives a second control signal φ.sub.2. A first power terminal of transistor T.sub.3 is connected to the second electrode of capacitor C.sub.1 and the second power terminal of transistor T.sub.3 is connected to ground GND. The gate of transistor T.sub.3 receives first control signal φ.sub.1. A first power terminal of transistor T.sub.4 is connected to the first electrode of capacitor C.sub.1 and the second power terminal of transistor T.sub.4 is connected to output node OUT. The gate of transistor T.sub.4 receives second control signal φ.sub.2. The bulk of each MOS transistor T.sub.1 to T.sub.4 is connected to ground GND.

(31) Oscillator 12 comprises a succession of an odd number of series-connected inverters, the output of the last inverter of the succession of inverters being connected to the input of the first inverter of the succession of inverters. Three series-connected inverters INV.sub.1, INV.sub.2, INV.sub.3 are shown in FIG. 2, the output of inverter INV.sub.3 being connected to the input of inverter INV.sub.1. Inverter INV.sub.3 supplies clock signal clk. Oscillator 12 further comprises an inverter INV.sub.4 having its input connected to the output of inverter INV.sub.3, and supplying a clock signal clkb. Each clock signal clk, clkb is a binary signal. Signals clk and clkb are complementary. The period of signal clk particularly depends on power supply voltage V.sub.e of oscillator 12 and on the number of series-connected inverters.

(32) Interface circuit 14 comprises an inverter INV.sub.5 receiving signal clk and supplying clock signal φ.sub.1. Interface circuit 14 comprises an inverter INV.sub.6 receiving signal clkb and supplying control signal φ.sub.2. Each inverter INV.sub.1 to INV.sub.6 is connected to anode for supplying voltage V.sub.e and is connected to ground GND.

(33) FIG. 3 shows an embodiment of an inverter INV. Each inverter INV.sub.1 to INV.sub.6 may have the structure shown in FIG. 3. Inverter INV comprises an input node A and an output node B. Inverter INV comprises a MOS transistor T.sub.5, for example, a P-channel enhancement MOS transistor, having its source connected to a node for supplying voltage Ve, having its drain connected to node B, and having its gate connected to node A. The bulk of transistor T.sub.5 is connected to a node for supplying voltage Ve. Inverter INV further comprises a MOS transistor T.sub.6, for example, an N-channel enhancement MOS transistor, having its source connected to ground GND, having its drain connected to node B, and having its gate connected to node A The bulk of transistor T.sub.6 is connected to ground GND.

(34) The operating principle of charge pump circuit 10 according to the embodiment shown in FIG. 2 will now be described in relation with FIGS. 4 to 6.

(35) In nominal operation, interface circuit 14 supplies binary controls signals φ.sub.1 and φ.sub.2 which are complementary. In the present embodiment, each signal φ.sub.1 and φ.sub.2 corresponds to a voltage which substantially alternates between voltage V.sub.e and 0 V. In steady state, charge pump circuit 10 supplies a voltage V.sub.s which is proportional to V.sub.e, transformation ratio k being theoretically equal to 2 and, in practice, slightly smaller than 2.

(36) FIG. 4 is a curve C.sub.I of the variation of drain-source current I.sub.ds of an N-channel depletion MOS transistor according to gate-source voltage V.sub.gs in ohmic state. Four bias points P1 to P4 have been shown on curve C.sub.I.

(37) FIG. 5 illustrates the conduction state of each MOS transistor T.sub.1 to T.sub.4 when control signal φ.sub.1 is at V.sub.e and control signal φ.sub.2 is at 0 V. Transistor T.sub.1 is substantially at bias point P.sub.2, transistors T.sub.3 and T.sub.4 are substantially at bias point P.sub.4, and transistor T.sub.3 is substantially at bias point P.sub.1. The current then preferably flows along dashed line 20. Capacitor C.sub.1 is then charged under voltage V.sub.e.

(38) FIG. 6 illustrates the conduction state of each MOS transistor T.sub.1 to T.sub.4 when control signal φ.sub.2 is at V.sub.e and control signal φ.sub.1 is at 0 V. Transistor T.sub.2 is at bias point P.sub.1, transistors T.sub.1 and T.sub.3 are at bias point P.sub.4, and transistor T.sub.4 is at bias point P.sub.3. The current then preferably flows along dashed line 22, which results in a discharge of capacitor C.sub.1 towards output node OUT. Voltage V.sub.s at output node OUT is maintained substantially at approximately k*V.sub.e, k being close to 2 in steady state in the present embodiment.

(39) FIG. 7 shows variation curves Ck.sub.1 and Ck.sub.2, according to voltage V.sub.e, of transformation ratios k.sub.1 and k.sub.2 in steady state respectively of converter 5 shown in FIG. 2 and of a converter having the same structure as converter 5 with the difference that transistors T.sub.1 to T.sub.4 are replaced with N-channel enhancement MOS transistors. Curves Ck.sub.1 and Ck.sub.2 have been obtained for MOS transistors having a 0.18-μm channel length.

(40) For curves Ck.sub.1 and Ck.sub.2, transformation ratio k.sub.1 and k.sub.2 of converter 5 decreases when voltage V.sub.e decreases. However, the decrease is faster when enhancement MOS transistors are used. Indeed, transformation ratio k.sub.2 decreases below 1.75 as soon as voltage V.sub.e decreases below 420 mV while transformation ratio k.sub.1 decreases below 1.75 only when voltage V.sub.e decreases below 250 mV. The present embodiment thus enables to operate the DC/DC converter at an input voltage smaller than that which can be obtained with a converter having the same structure, formed of enhancement MOS transistors.

(41) FIG. 8 shows another embodiment of a DC/DC converter 30. Converter 30 comprises all the elements of converter 5 with the difference that inverters INV.sub.1 to INV.sub.6 are supplied with voltage V.sub.s instead of receiving voltage V.sub.e.

(42) In normal operation, voltage V.sub.s is higher than voltage V.sub.e. The power supply of oscillating circuit 11 of converter 30 is advantageously more efficient than that of converter 5. Further, the conductivity of MOS transistors T.sub.1 to T.sub.4 of converter 30 is increased when the gates thereof are taken to V.sub.s in the on state with respect to MOS transistors T.sub.1 to T.sub.4 of converter 30 having their gates only taken to V.sub.e in the on state.

(43) When voltage V.sub.e increases from the zero value, oscillator 12 of converter 30 cannot start as long as output voltage Vs is smaller than the start voltage of oscillator 12. The current then directly flows through transistors T.sub.1 and T.sub.4 of charge pump circuit 10 so that voltage V.sub.s rises until it becomes substantially equal to voltage V.sub.e. As soon as voltage V.sub.s has reached the start voltage of oscillator 12, the operation of converter 30 carries on as previously described for converter 5 in relation with FIGS. 4 to 6.

(44) Further, as soon as oscillator 12 has started, voltage V.sub.s becomes greater than V.sub.e, so that the oscillation frequency of oscillator 12 increases faster than if oscillator 12 was supplied with voltage V.sub.e and the variation rate of the transformation ratio of charge pump circuit 10 is increased.

(45) Generally, charge pump circuit 10 may correspond to any type of voltage step-up, step-down, or inverter charge pump circuit.

(46) FIG. 9 shows, as an example, another embodiment of a converter 35 where charge pump circuit 10 is a voltage step-up circuit having a transformation ratio of approximately 4. Charge pump circuit 10 of converter 35 comprises transistors T.sub.1 to T.sub.4 and capacitor C.sub.1 previously described in relation with FIG. 2 and further comprises N-channel depletion MOS transistors T.sub.7 to T.sub.12 and capacitors C.sub.2 and C.sub.3.

(47) The power terminal of transistor T.sub.4 which is not connected to capacitor C.sub.1 is connected to a first electrode of capacitor C.sub.2. A first power terminal of transistor T.sub.7 is connected to input node IN and the second power terminal of transistor T.sub.7 is connected to the second electrode of capacitor C2. The gate of transistor T.sub.7 receives first control signal φ.sub.1. A first power terminal of transistor T.sub.8 is connected to ground GND and the second power terminal of transistor T.sub.8 is connected to the second electrode of capacitor C.sub.2. The gate of transistor T.sub.8 receives second control signal φ.sub.2. A first power terminal of transistor T.sub.9 is connected to the first electrode of capacitor C.sub.2 and the second power terminal of transistor T.sub.9 is connected to a first electrode of capacitor C.sub.3. The gate of transistor T.sub.9 receives first control signal φ.sub.1. A first power terminal of transistor T.sub.10 is connected to input node IN and the second power terminal of transistor T.sub.10 is connected to the second electrode of capacitor C.sub.3. The gate of transistor T.sub.10 receives second control signal φ.sub.2. A first power terminal of transistor T.sub.11 is connected to ground GND and the second power terminal of transistor T.sub.11 is connected to the second electrode of capacitor C.sub.3. The gate of transistor T.sub.11 receives first control signal φ.sub.1. A first power terminal of transistor T.sub.12 is connected to the first electrode of capacitor C.sub.3 and the second power terminal of transistor T.sub.12 is connected to output node OUT. The gate of transistor T.sub.12 receives second control signal φ.sub.2.

(48) FIG. 10 shows another embodiment of a converter 40. Converter 40 comprises all the elements of converter 35, shown in FIG. 9, with the difference that charge pump circuit 10 is a voltage inverter having a transformation ratio k of approximately −1 and that oscillator 12 and interface circuit 14 are connected to output node OUT supplying voltage V.sub.s instead of being connected to ground GND.

(49) Charge pump circuit 10 of converter 40 comprises four N-channel depletion MOS transistors T.sub.13, T.sub.14, T.sub.15, and T.sub.16 and one capacitor C.sub.4. A first power terminal of transistor T.sub.13 is connected to ground GND and the second power terminal of transistor T.sub.13 is connected to a first electrode of capacitor C.sub.4. The gate of transistor T.sub.13 receives second control signal φ.sub.2. A first power terminal of transistor T.sub.14 is connected to input node IN and the second power terminal of transistor T.sub.14 is connected to the second electrode of capacitor C.sub.4. The gate of transistor T.sub.14 receives second control signal φ.sub.2. A first power terminal of transistor T.sub.15 is connected to the second electrode of capacitor C.sub.4 and the second power terminal of transistor T.sub.15 is connected to ground GND. The gate of transistor T.sub.15 receives first control signal φ.sub.1. A first power terminal of transistor T.sub.16 is connected to the first electrode of capacitor C.sub.4 and the second power terminal of transistor T.sub.16 is connected to output node OUT. The gate of transistor T.sub.16 receives first control signal φ.sub.1. The bulk of each transistor T.sub.13, T.sub.14, T.sub.15, and T.sub.16 is connected to ground GND.

(50) The fact for oscillator 12 and for interface circuit 14 to be biased between voltage −V.sub.e and voltage V.sub.e advantageously enables to improve the operation of converter 40. Indeed, in operation, transistors T.sub.13, T.sub.14, T.sub.15 and T.sub.16 are more blocked when their gates receive voltage −V.sub.e rather than at ground GND. Further, in a cold start, as long as the oscillator has not started, voltage V.sub.s remains substantially at 0 V. As soon as oscillator 12 has started, voltage V.sub.s decreases below 0 V, so that the oscillation frequency of oscillator 12 increases faster than if oscillator 12 was connected to ground GND and the variation rate of the transformation ratio of charge pump circuit 10 is increased.

(51) FIG. 11 shows variation curves Ck.sub.1′ and Ck.sub.2′, according to voltage V.sub.e, of transformation ratios k.sub.1′. and k.sub.2′ respectively of converter 40 shown in FIG. 10 and of a converter having the same structure as converter 40 with the difference that transistors T.sub.13 to T.sub.16 are replaced with N-channel enhancement MOS transistors. Curves Ck.sub.1′. and Ck.sub.2′ have been obtained for MOS transistors having a 0.18-μm channel length.

(52) For curves Ck.sub.1′ and Ck.sub.2′, transformation ratios k.sub.1′ and k.sub.2′, which are negative, decrease when voltage V.sub.e increases. However, the decrease is faster when depletion MOS transistors are used. Indeed, transformation ratio k.sub.1′ decreases below −0.5 as soon as voltage V.sub.e increases above 200 mV while transformation ratio k.sub.2′ decreases below −0.5 only when voltage V.sub.e increases above 300 mV.

(53) FIG. 12 illustrates, in the form of a block diagram, another embodiment of a converter 45. Converter 45 comprises two charge pump circuits 10.sub.1 and 10.sub.2. Charge pump circuit 10.sub.1 is capable of supplying a positive voltage V.sub.s1, of same sign as voltage V.sub.e and charge pump circuit 10.sub.2 is capable of supplying a voltage V.sub.s2 of a sign opposite to that of voltage V.sub.e. Oscillator 12 and interface circuit 14 are supplied with positive voltage V.sub.s1 and negative voltage V.sub.s2. Interface circuit 14 supplies control signals φ.sub.1 and φ.sub.2 to the two charge pump circuits 10.sub.1 and 10.sub.2. In normal operation, control signals φ.sub.1 and φ.sub.2 alternate between voltage V.sub.s1, which may be greater than V.sub.e, and voltage V.sub.s2, which is negative. This enables to improve the conduction and the blocking of the MOS transistors of charge pump circuit 10.sub.1 and 10.sub.2. The transformation ratio of charge pump circuit 10.sub.1 is thus increased and becomes closer to the theoretical maximum value. Further, as soon as oscillator 12 has started, voltage V.sub.s1 is greater than voltage V.sub.e and voltage V.sub.s2 decreases below 0 V, so that the oscillation frequency of oscillator 12 increases faster than if oscillator 12 was connected to voltage V.sub.e and to ground GND and the variation rate of the transformation ratio of charge pump circuit 10 is increased.

(54) FIG. 13 shows, as an example, an embodiment of a converter 50, corresponding to a more detailed embodiment of converter 45 of FIG. 12, where charge pump circuit 10.sub.1 has the structure of charge pump circuit 10 of converter 5, where charge pump circuit 10.sub.2 has the structure of charge pump circuit 10 of converter 40, where oscillating circuit 11 has the structure of oscillating circuit 11 of converter 10 with the difference that oscillating circuit 11 is supplied with voltage V.sub.s1 instead of voltage V.sub.e and receives voltage V.sub.s2 instead of being connected to ground GND. Interface circuit 14 supplies control signals φ.sub.1 and φ.sub.2 to the two charge pump circuits 10.sub.1 and 10.sub.2. In normal operation, control signals φ.sub.1 and φ.sub.2 alternate between voltage V.sub.s1, which, in the present embodiment, is substantially equal to 2V.sub.e, and voltage V.sub.s2, which, in the present embodiment, is substantially equal to −V.sub.e.

(55) FIG. 14 is a drawing similar to FIG. 7 for converter 45 of FIG. 12 in the case where charge pump circuit 10.sub.1 is a voltage step-up circuit having the structure of the charge pump circuit of converter 35 shown in FIG. 9. FIG. 14 shows variation curves Ck.sub.1″ and Ck.sub.2″, according to voltage V.sub.e, of transformation ratios k.sub.1″ and k.sub.2″ of charge pump circuit 10.sub.2 respectively of converter 45 and of a converter having the same structure as converter 45 with the difference that the transistors of charge pump circuits 10.sub.1 and 10.sub.2 are replaced with N-channel enhancement MOS transistors. Curves Ck.sub.1″ and Ck.sub.2″ have been obtained for MOS transistors having a 0.18-μm channel width.

(56) For curves Ck.sub.1″ and Ck.sub.2″, transformation ratio k.sub.1′ and k.sub.2″ decreases when voltage V.sub.e decreases. However, the decrease is faster when enhancement MOS transistors are used. Indeed, transformation ratio k.sub.2″ decreases below 2.75 as soon as voltage V.sub.e decreases below 250 mV while transformation ratio k.sub.1″ decreases below 2.75 only when voltage V.sub.e decreases below 155 mV.

(57) FIG. 15 shows another embodiment of a converter 55. Converter 55 comprises two charge pump circuits 10.sub.1 and 10.sub.2. Charge pump circuit 10.sub.1 is connected to input node IN and supplies a voltage V.sub.s1 to an output node OUT.sub.1. Charge pump circuit 10.sub.1 may correspond to any of the charge pump circuits previously described in relation with FIG. 2, 8, 9, 10, or 13. Charge pump circuit 10.sub.2 is connected to input node IN and supplies a voltage V.sub.s2 to an output node OUT.sub.2. Charge pump circuit 10.sub.2 corresponds to an amplifier formed with enhancement MOS transistors. As an example, charge pump circuit 10.sub.2 may correspond to any of the charge pump circuits previously described in relation with FIG. 2, 8, 9, 10, or 13 by replacing the depletion MOS transistors with enhancement MOS transistors. In FIG. 15, the shown charge pump circuit 10.sub.2 has the same structure as charge pump circuit 10 shown in FIG. 9 with the difference that depletion MOS transistors T.sub.1 to T.sub.4 and T.sub.7 to T1.sub.2 have been respectively replaced with enhancement MOS transistors T.sub.1′ to T.sub.4′ and T.sub.7′ to T.sub.12′. Converter 55 comprises oscillator 12 and interface circuit 14 such as previously described. According to an embodiment, oscillator 12 and interface circuit 14 are connected to output node OUT.sub.1. Charge pump circuit 10.sub.2 may have the same structure as charge pump circuit 10.sub.1 with the difference that the depletion MOS transistors of charge pump circuit 10.sub.1 are replaced with enhancement MOS transistors.

(58) During a cold start at low voltage V.sub.e, charge pump circuit 10.sub.1, which supplies voltage V.sub.s1, starts faster and under a lower voltage V.sub.e than charge pump circuit 10.sub.2. Charge pump circuit 10.sub.2 only starts when voltage V.sub.s1 is greater than the threshold voltage of the enhancement MOS transistors forming it. Indeed, control signals φ.sub.1 and φ.sub.2 of the gates of the enhancement MOS transistors of charge pump circuit 10.sub.2 vary substantially from 0 V to V.sub.s1. When charge pump circuit 10.sub.2 operates normally, it may be advantageous to use voltage V.sub.s2 supplied by charge pump circuit 10.sub.2 since the power efficiency, equal to the ratio of the power supplied by the charge pump circuit to the power received by the charge pump circuit, of charge pump circuit 10.sub.2 may be greater than the power efficiency of charge pump circuit 10.sub.1.

(59) According to an embodiment, charge pump circuit 10.sub.1 is connected to input node IN by a switch SW1. Further, oscillator 12 and interface circuit 14 are connected to output node OUT.sub.1 by a switch SW.sub.2 and to output node OUT.sub.2 by a switch SW.sub.3. Switches SW.sub.1, SW.sub.2, and SW.sub.3 are controlled by a control unit, not shown, which may comprise a dedicated circuit. According to an embodiment, during a cold start with a low voltage V.sub.e, switches SW.sub.1 and SW.sub.2 are on and switch SW.sub.3 is off. Oscillating circuit 11 is then powered with voltage V.sub.s1. The control unit may be capable of comparing voltage V.sub.s1 with a reference voltage, for example, equal to the sum of the threshold voltage of the enhancement MOS transistors of charge pump circuit 10.sub.2 and of a security margin. When voltage V.sub.s1 is greater than the reference voltage, the control unit may turn off switch SW.sub.1 to increase the power transfer to charge pump circuit 10.sub.2. Further, switch SW.sub.2 may then be turned off and switch SW.sub.3 may be turned on so that circuits 12 and 14 are then powered with voltage V.sub.s2.

(60) FIG. 16 shows another embodiment of a charge pump circuit 10 of voltage doubler type. Charge pump circuit 10 shown in FIG. 16 comprises all the elements of charge pump circuit 10 previously described in relation with FIG. 2 with the difference that depletion MOS transistor T.sub.3 is replaced with an N-channel enhancement transistor T.sub.16. The bulk of transistor T.sub.16 is connected to ground GND. This enables to improve the power efficiency of the converter. Preferably, depletion MOS transistors T.sub.1 and T.sub.2 are not replaced with enhancement MOS transistors, to avoid degrading the starting performance of charge pump circuit 10.

(61) An enhancement MOS transistor may be provided in parallel with a depletion MOS transistor for at least one of the depletion MOS transistors of the charge pump circuit. This enables to improve the power efficiency of the converter while keeping the advantages of the use of depletion MOS transistors. As an example, in FIG. 16, a P-channel enhancement MOS transistor T.sub.17 may be assembled in parallel with depletion MOS transistor T.sub.4, a first power terminal of transistor T.sub.17 being connected to the first electrode of capacitor C.sub.1, the second power terminal of transistor T.sub.17 being connected to output node OUT. The gate of transistor T.sub.17 receives control signal φ.sub.1. The bulk of transistor T.sub.17 may be connected to output node OUT. This enables to improve the power efficiency of the converter.

(62) FIG. 17 shows an embodiment of a power recovery system 60 comprising a transducer 62 capable of supplying voltage V.sub.e to a converter 64 which may correspond to any of previously-described converters 5, 30, 35, 40, 45, 50, 55. Transducer 62 may be capable of transforming into electric power another form of power, for example, thermal power, mechanical power, or radiative power.

(63) Specific embodiments have been described. Various alterations, modifications, and improvements will readily occur to those skilled in the art. In particular, although, in the previously-described embodiments, oscillator 12 is a ring oscillator, it should be clear that oscillator 12 may have a different structure. As an example, the previously-described embodiments may be implemented with a relaxation oscillator.

(64) Further, it should be noted that those skilled in the art may combine various elements of these various embodiments and variations without showing any inventive step. As an example, the embodiments previously described in relation with FIGS. 13 and 15 may be combined, and the converter may comprise two charge pump circuits used to supply the two voltages between which the oscillating circuit is supplied at the starting as shown in FIG. 13 and one charge pump circuit with enhancement MOS transistors, such as shown in FIG. 15, used to supply the output voltage of the converter once the converter has started.

(65) Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.