Power converter configured for limiting switching overvoltage

Abstract

The present disclosure relates to a power converter configured for limiting switching overvoltage. The power converter comprises a pair of commutation cells. Each commutation cell includes a power electronic switch and a gate driver connected to a gate of the power electronic switch. A reference of the gate driver of a first commutation cell is connected to a ground of the power converter while a reference of the gate driver of a second commutation cell is connected to a collector of the power electronic switch of the first commutation cell. The gate driver of the second commutation cell has no negative voltage power input, either through using a single voltage power supply or by connecting a negative voltage connection of the dual voltage power supply to ground.

Claims

1. A power converter configured for limiting switching overvoltage, comprising: a pair of first and second commutation cells, each commutation cell including a power electronic switch, a gate driver connected to a gate of the power electronic switch, and respective first and second resistors connected in series and connected across a parasitic emitter inductance of the power electronic switch, a reference of the gate driver of a first commutation cell being connected to a ground of the power converter, the reference of the gate driver of the first commutation cell being also connected to a connection point between the first and second resistors of the first commutation cell, a reference of the gate driver of a second commutation cell being connected to a collector of the power electronic switch of the first commutation cell, the reference of the gate driver of the second commutation cell being also connected to a connection point between the first and second resistors of the second commutation cell, wherein the gate driver of the second commutation cell has solely a single positive voltage power supply input.

2. The power converter of claim 1, wherein the negative voltage supply input of the gate driver of the first commutation cell is connected to the ground of the power converter.

3. The power converter of claim 1, wherein the power electronic switches include isolated gate bipolar transistors (IGBT).

4. The power converter of claim 1, wherein the power converter is a DC to AC power converter.

5. The power converter of claim 1, wherein the power electronic switches each include a collector and an emitter.

6. The power converter of claim 1, wherein each commutation cell includes first and second resistors connected in series and connected across a parasitic emitter inductance of the power electronic switch, the reference of the gate driver being connected to a connection point between the first and second resistors.

7. The power converter of claim 6, wherein each commutation cell includes a diode connected in parallel to one of the first and second resistors, between an emitter of the power electronic switch and the reference of the gate driver, the diode becoming conductive when a voltage at the emitter of the power electronic switch is greater than a voltage of the reference of the gate driver.

8. The power converter of claim 1, wherein: a high frequency loop is defined by the pair of commutation cells; parasitic inductances are defined by interconnection of elements of the high frequency loop; and voltages induced in the parasitic inductances of the high frequency loop are sampled and supplied to the references of the gate drivers to slow down a variation of gate-emitter voltages of the power electronic switches.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the disclosure will be described by way of example only with reference to the accompanying drawings, in which:

(2) FIG. 1 is an idealized circuit diagram of a conventional commutation cell such as those used in conventional power converter circuits;

(3) FIG. 2 is another circuit diagram of the conventional commutation cell of FIG. 1, showing parasitic (stray) inductances;

(4) FIG. 3 is a circuit diagram of a conventional commutation cell further showing a gate driver;

(5) FIG. 4 is a circuit diagram of a conventional IGBT leg formed of two conventional commutation cells;

(6) FIG. 5 is a diagram showing current and voltage waveforms at turn-off of the IGBTs of FIG. 4;

(7) FIG. 6 is a circuit diagram of an IGBT leg having resistive dividers connected across parasitic (stray) emitter inductances, according to an embodiment;

(8) FIG. 7 is a diagram showing current and voltage waveforms at turn-off of the IGBTs of FIG. 6 with a bus voltage of 500 volts;

(9) FIG. 8 is a diagram showing current and voltage waveforms at turn-off of the IGBTs of FIG. 6, the resistive divider being adjusted for a maximum bus voltage of 300 volts in short circuit condition; and

(10) FIG. 9 is a schematic representation of IGBT capacitances including a Miller capacitance.

(11) Like numerals represent like features on the various drawings.

DETAILED DESCRIPTION

(12) Various aspects of the present disclosure generally address one or more of the problems of overvoltage present power converters at the time of switching.

(13) Circuits operable to limit overvoltage in commutation cells, especially at turn-off of IGBTs, are described in international patent publication no WO 2013/082705 A1, in international patent application no PCT/CA2013/000805, in U.S. provisional applications No. 61/808,254, no 61/898,502 and no 61/904,038, and in “Reducing switching losses and increasing IGBT drive efficiency with Reflex™ gate driver technology”, available at http://www.advbe.com/docs/DeciElec2013-Jean Marc Cyr-TM4.pdf, all of which are authored by Jean-Marc Cyr et al. the disclosure of these being incorporated by reference herein.

(14) The present technology provides control of overvoltage and switching losses at turn-off of a power electronic switch of a commutation cell. Circuits and methods presented herein are generally compatible with other solutions to limit overvoltage at turn-off of power electronic switches.

(15) In a commutation cell, di/dt at turn-off of a power electronic switch generates a voltage across stray inductances of a high frequency loop of the commutation cell. This voltage is applied across the power electronic switch in addition to a bus voltage providing power to the commutation cell. A solution based on the injection of a sample of the overvoltage present across the power electronic switch to a gate driver of the power electronic switch has been proposed. When a pair of power electronic switches are connected in series, a parasitic inductance present being an emitter of a “top” power electronic switch and a collector of a “bottom” power electronic switch may not be sufficient to provide a sufficient sample of the overvoltage present in the top power electronic switch. An improvement comprises using a gate driver having a single, positive voltage power supply for driving the top power electronic switch. A zero voltage being initially applied by the gate driver to the gate of the top power electronic switch while turned on, a voltage swing required to turn it off is reduced.

(16) The techniques disclosed herein will mainly be described in relation to the use of isolated gate bipolar transistors (IGBT). Mentions of IGBTs in the following description are made for illustration purposes and are not meant to limit the present disclosure. The same techniques may equally be applied to commutation cells constructed using metal-oxide-semiconductor field-effect transistors (MOSFET), bipolar transistors and like power electronic switches.

(17) Generally stated, by changing the reference of the gate driver from the emitter (logical pin) of FIG. 4 to the ground bus (for the bottom IGBT Q.sub.1) and to the collector of the bottom IGBT (for the top IGBT Q.sub.2), it is possible to decrease this overvoltage of V.sub.ce during turn-off. Because available parasitic inductances are not similarly distributed about the top and bottom IGBTs, a variant further proposes to modify a voltage applied to the gate of the top IGBT while turned on.

(18) In other words, a technique for connecting reference of the gate driver to a power tab of the IGBT, the power tab being itself connected to a power source, instead of to the logical pin has been developed. A voltage across the emitter inductance is injected in the gate driver to create a negative voltage at the emitter of the IGBT to slow down the negative slope of V.sub.ge, as will be discussed hereinbelow. The result is a direct action on the gate voltage without any delay and di/dt limitations.

(19) Because there is no optimal emitter inductance between the logical and power connections of the emitter in a commercial IGBT module, the present disclosure introduces a technique developed to optimize the sample of the overvoltage injected in the gate drive circuit using a resistive divider. FIG. 6 is a circuit diagram of an IGBT leg having resistive dividers connected across parasitic (stray) emitter inductances, according to an embodiment. Generally, FIG. 6 shows a power converter having a pair of commutation cells connected in series, each commutation cell including a power electronic switch and a gate driver. The power converter may for example be an IGBT leg 90 including compensation circuits connected to gate drivers 60 and 62 in a configuration that reduces overvoltage on the IGBTs. FIG. 6 introduces a compensation circuit that optimizes overvoltage on the IGBT using a resistive divider.

(20) Discussing the bottom portion of the IGBT leg 90 of FIG. 6, the bottom IGBT Q.sub.1 includes a parasitic collector inductance L.sub.c-low a parasitic emitter inductance L.sub.e-low. The gate 26 of the bottom IGBT Q.sub.1 connected to its gate driver 60 via a resistor R.sub.1. A reference 52 of the gate driver 60 is connected to a compensation circuit having a resistive divider circuit including two resistors R.sub.2 and R.sub.3 and a diode D.sub.3 that allows the turn-on not to be impacted by shorting the resistor R.sub.2 when a voltage at the emitter of the bottom IGBT Q.sub.1 is higher than the reference 52. The diode D.sub.3 is conducting while turning on the IGBT Q.sub.1 because the direction of the current in the IGBT Q.sub.1 causes a voltage to be higher at the emitter 24 than at the reference 52. In contrast, the diode D.sub.3 is not conducting while turning off the IGBT Q.sub.1 because a drop of voltage at the emitter 22 causes application of a negative voltage across the diode D.sub.3. It is to be noted that while the resistors R.sub.2 and R.sub.3 are shown connected across both parasitic inductances L.sub.e-low and L.sub.−Vbus, they may alternatively be connected solely across parasitic inductance L.sub.e-low, should this parasitic inductance be sufficient and the connection available.

(21) In the circuit of FIG. 6, values of the resistors R.sub.2 and R.sub.3 are selected according to an acceptable overvoltage level allowed across the bottom IGBT Q.sub.1. FIG. 7 is a diagram showing current and voltage waveforms at turn-off of the IGBTs of FIG. 6 with a bus voltage of about 500 volts. FIG. 8 is a diagram showing current and voltage waveforms at turn-off of the IGBTs of FIG. 6, the resistive divider being adjusted for a maximum bus voltage of 300 volts in short circuit condition. A ratio of R.sub.2 over R.sub.3 is increased to reduce the overvoltage. The value of these two resistors R.sub.2 and R.sub.3 in parallel is set, in series with a gate driver resistor R.sub.1. A value of the gate driver resistor R.sub.1 is adjusted in a conventional manner according to a proper commutation behavior.

(22) By correctly setting values of the resistors of the compensation circuits, it is possible to reduce the effect of the emitter inductance to get the maximum overvoltage allowed to therefore improve the efficiency.

(23) In other words, the normal practice consisting in using a resistor R.sub.1 in the ground connection of the gate driver to limit the current in the diodes that protect the gate driver of the lower IGBT from a negative voltage when the upper IGBT turns off has been modified by splitting the resistor in two resistors, including R.sub.1 in series with R.sub.2 and R.sub.3 connected in parallel, and by adapting their ratio to limit the effect of the emitter inductance on the di/dt. An equivalent resistor value may remain the same, but the voltage divider gives the desired weight of the emitter inductance to limit the overvoltage at the desired level.

(24) The overvoltage can be optimized as much as possible to reach the maximum IGBT rating while maintaining the speed of the di/dt for efficiency reasons. This is done by reducing a value of R.sub.2, the resistor connected to the IGBT emitter, compared to R.sub.3, the resistor connected to the power tab. The voltage across the emitter inductance is thus split in two and only the voltage across the logical resistor is applied in the gate drive circuit to limit the gate voltage drop.

(25) FIGS. 7 and 8 both show the current I and the voltages V.sub.ge and V.sub.ce during turn-off for the circuit of FIG. 6, for different bus voltages. It may be observed that overvoltage of V.sub.ce during turn-off is greatly reduced (see plateau 92). This plateau 92 occurs while a drop rate of the voltage V.sub.ge is reduced by the insertion of a sample of the voltage across the parasitic inductance L.sub.e-low.

(26) The duration of the plateau 92 impacts losses of the commutation cell during turn-off of the IGBT. A longer plateau 92 brings higher losses. Because of the desire to limit at the same time the overvoltage and its length, a square wave shape of the overvoltage plateau 92 is suitable. The intrinsic behavior (natural feedback) of the overvoltage gives this shape.

(27) This technique works very well for the bottom IGBT Q.sub.1 because the emitter inductance L.sub.e-low is sufficiently large to provide good overvoltage sampling. In contrast, for the top IGBT Q.sub.2, the emitter inductance L.sub.e-high often has a too small value to suitably clamp a voltage thereacross without increasing the gate resistor R.sub.4, to protect the top IGBT Q.sub.2. In practice, the emitter inductance L.sub.e-high of the top IGBT Q.sub.2 is very often too low to be used to bring down the overvoltage across the top IGBT Q.sub.2 to a safe level.

(28) Indeed, because of the constraints on packaging of IGBT modules, the upper and lower semiconductors are generally packaged within close proximity of each other so the emitter inductance of the upper IGBT Q.sub.2, L.sub.e-high, is quite small, in the order of a few nH. On the other hand, because the only point of connection other than the logical emitter of the lower IGBT Q.sub.1 is the power tab of −V.sub.bus, the inductance of the lower IGBT Q.sub.1, L.sub.e-low, may be as much as 5 times greater than the upper emitter inductance L.sub.e-high. The connection of the −V.sub.bus tab is highly inductive because of its length and curves.

(29) The comparatively small value of the upper emitter inductance L.sub.e-high may impact the effectiveness of the solution described hereinabove when applied without additional modification to the top IGBT Q.sub.2.

(30) FIG. 9 is a schematic representation of IGBT capacitances including a Miller capacitance. A Miller current 200 circulates in the Miller capacitance C.sub.CG, causing a voltage variation dv/dt thereacross. The Miller current 200 is split between a portion 202 flowing through the gate resistor R.sub.4 and a portion 204 flowing through a gate to emitter parasitic capacitance C.sub.GE. The gate driver tries to maintain the gate to emitter voltage V.sub.ge in an off state, sinking the current 202 with the gate resistor R.sub.4. To this end, the gate resistor R.sub.4 has a low value to keep the gate to emitter voltage V.sub.ge below the threshold voltage V.sub.ge(th) even in the presence of the Miller current.

(31) Retuning to FIG. 4, a typical IGBT leg is shown in which both gate drivers 40 have positive and negative supply voltages connected to +15V and −5V power sources. Voltages induced across each of the emitter parasitic inductances L.sub.e-high and L.sub.e-low are driven by the sum of their gate to emitter voltages V.sub.ge, when the IGBTs operate in their linear region, and the negative supply voltage, that is −5V in the typical case of FIG. 4. FIG. 5 shows a gate to emitter voltage V.sub.ge of about +7V (in the linear region). Consequently, the total voltages induced across the emitter parasitic inductances L.sub.e-high and L.sub.e-low reach an average of +12V. In contrast, FIG. 7 shows distinct gate to emitter voltages V.sub.ge for both IGBTs, still reaching about +7V (in the linear region), falling to about 0V for the upper IGBT Q.sub.2 and to about −5V for the lower IGBT Q.sub.1. Consequently, the total voltage induced across the emitter parasitic inductance L.sub.e-high reaches an average of +7V while the total voltage induced across the emitter parasitic inductance L.sub.e-low reaches an average of +12V.

(32) As previously discussed, the emitter inductance L.sub.e-high of the top IGBT Q.sub.2 has a smaller value compared to the emitter inductance L.sub.e-low of the bottom IGBT Q.sub.1. In the embodiment of FIG. 6, a gate driver 62 connected to a gate 64 of the top IGBT Q.sub.2 is a single supply gate driver: instead of using a conventional dual supply gate driver having a negative supply voltage of −5V and positive supply voltage of +15V (as in the case of FIG. 4), the gate driver 62 is powered by a single positive supply voltage of +15V, its negative supply voltage being set at 0V, for example being connected to a ground reference 54. By modifying the negative supply of the gate driver 62, the voltage induced in the emitter inductance L.sub.e-high at turn-off of the top IGBT Q.sub.2 can be maintained as low as +7V, since it is not summed with a −5V of a conventional gate driver, and still successfully maintain the gate to emitter voltage V.sub.ge of the top IGBT Q.sub.2 in the linear region. As a result, when the negative power supply of the gate driver 62 is at 0V instead of −5V, the sample of the overvoltage can be as low as 7V compared with 12V. For the same overvoltage (for the same di/dt), the parasitic emitter inductance L.sub.e-high of the top IGBT Q.sub.2 may be only about 60% (i.e. 7/12) of the parasitic emitter inductance that would be required with −5V applied to the negative power supply of the gate driver 62. In summary, the smaller parasitic inductance L.sub.e-high of the top IGBT Q.sub.2 is sufficient to suitably clamp the voltage across the top IGBT Q.sub.2 when using the configuration of FIG. 6.

(33) The gate driver 60 of the bottom IGBT Q.sub.1 may be a dual supply gate driver powered using a negative supply voltage of −5V and a positive supply voltage of +15V and still adequately use the L.sub.e-low. However, the gate driver 60 may optionally use a single power supply, this latter solution being at once effective and more economical.

(34) Generally stated, in the case of conventional power converters, the negative supply voltage of the gate driver of the top IGBT Q.sub.2 was required because of the Miller current 200 generated by the collector to emitter voltage variation (dVce/dt) caused by turning on of the bottom IGBT Q.sub.1. With the present technology, the negative power supply is not required because the emitter voltage of the top IGBT Q.sub.2 is pushed up by the voltage induced across the emitter inductance L.sub.e-high, which behaves as a negative supply would. The polarity across the emitter inductance L.sub.e-high is reversed compared to the indication on FIG. 6 because the current variation (di/dt) is on the opposite direction.

(35) The foregoing describes solutions applicable to DC-DC power converters, AC-DC power converters and to DC-AC power converters, for example commutation cells using a full leg of semiconductors, opposite pairs of power electronic switches and freewheel diodes, to provide alternative current to a connected load such as a motor of an electric vehicle.

(36) Those of ordinary skill in the art will realize that the description of the power converter are illustrative only and are not intended to be in any way limiting. Other embodiments will readily suggest themselves to such persons with ordinary skill in the art having the benefit of the present disclosure. Furthermore, the power converter may be customized to offer valuable solutions to existing needs and problems of overvoltage occurring upon switching in power converters.

(37) In the interest of clarity, not all of the routine features of the implementations of the power converter are shown and described. It will, of course, be appreciated that in the development of any such actual implementation of the power converter, numerous implementation-specific decisions may need to be made in order to achieve the developer's specific goals, such as compliance with application-, system-, and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the field of power electronics having the benefit of the present disclosure.

(38) It is to be understood that the power converter is not limited in its application to the details of construction and parts illustrated in the accompanying drawings and described hereinabove. The proposed commutation cell and compensation circuit for limiting switching overvoltage and for limiting recovery current is capable of other embodiments and of being practiced in various ways. It is also to be understood that the phraseology or terminology used herein is for the purpose of description and not limitation. Hence, although the commutation cell and compensation circuit for limiting switching overvoltage and for limiting recovery current has been described hereinabove by way of illustrative embodiments thereof, it can be modified, without departing from the spirit, scope and nature of the subject invention.