Static offset reduction in a current conveyor

Abstract

A voltage mirror circuit, having an input node and an output node provides substantially equal voltage levels at the input node and the output node. The voltage mirror circuit comprises an input current source transistor, an input gain transistor arranged in series with the input current source transistor such that the input gain transistor is traversed by the bias current, wherein the voltage level at the input node corresponds to the voltage drop across the input current source transistor and the input gain transistor. An intermediate gain transistor forms a first current mirror with the input gain transistor. An output current source transistor forms a second current mirror with the intermediate current source transistor. The voltage level at the output node corresponds to the voltage drop across the output current source transistor and the output gain transistor.

Claims

1. A current sensing circuit configured to provide an indication of a current through a first resistance, the first resistance having a first end and a second end, wherein the first end is coupled to an input node, the current sensing circuit comprising: an input current source transistor configured to provide a bias current; an input gain transistor arranged in series with the input current source transistor such that the serial input gain transistor is traversed by the bias current, wherein the voltage level at the input node corresponds to the voltage drop across the input current source transistor and the input gain transistor; an intermediate gain transistor forming a first current mirror with the input gain transistor; an intermediate current source transistor arranged in series with the intermediate gain transistor such that a current through the intermediate current source transistor corresponds to a current through the intermediate gain transistor; an output current source transistor forming a second current mirror with the intermediate current source transistor; and an output gain transistor arranged in series with the output current source transistor such that a current through the output current source transistor corresponds to a current through the output gain transistor, wherein a voltage level at an output node corresponds to the voltage drop across the output current source transistor and the output gain transistor; wherein sources of the current source transistors share a common potential; wherein sources of the input gain transistor and of the intermediate gain transistor correspond to the input node; and wherein a source of the output gain transistor corresponds to the output node; wherein the first resistance provides a load current to a load arranged in parallel to the serial input gain transistor and input current source transistor; wherein the current sensing circuit comprises an output transistor arranged in parallel to the serial output gain transistor and output current source transistor; and wherein the current through the output transistor provides an indication of the load current.

2. The current sensing circuit of claim 1, wherein a drain to source voltage of the output transistor corresponds to the voltage level at the output node.

3. The current sensing circuit of claim 2, wherein: the output transistor is arranged such that a gate-source voltage of the output transistor corresponds to a drain-source voltage of the output current source transistor; and a threshold voltage of the intermediate current source transistor is substantially equal to a threshold voltage of the intermediate gain transistor.

4. The current sensing circuit of claim 1, wherein a gate and a drain of the input gain transistor are short circuited and coupled to a gate of the intermediate gain transistor.

5. The current sensing circuit of claim 1, wherein: the gate of the input gain transistor, the gate of the intermediate gain transistor, and the gate of the output gain transistor are directly coupled; the gate of the intermediate current source transistor and the gate of the output current source transistor are directly coupled; and the gate of the intermediate current source transistor is coupled to the drain of the intermediate current source transistor.

6. The current sensing circuit of claim 1, wherein the transistors are metal oxide semiconductor field effect transistors.

7. The current sensing circuit of claim 1, wherein the gain transistors are P channel transistors and the current source transistors are N-channel transistors.

8. The current sensing circuit of claim 2, wherein the gain transistors are P-channel transistors and the output transistor is an N channel transistor.

9. The current sensing circuit of claim 1, further comprising: a current source configured to provide a pre-determined current; and a mirror transistor arranged in series with the current source, such that the mirror transistor is traversed by the pre-determined current, and forming a current mirror with the input current source transistor, thereby providing the bias current.

Description

SHORT DESCRIPTION OF THE FIGURES

(1) The invention is explained below in an exemplary manner with reference to the accompanying drawings.

(2) FIGS. 1a to 1c illustrate example current sensing circuits.

(3) FIGS. 2a to 2c show circuit diagrams of example current sensing circuits with reduced offset.

(4) FIG. 3a illustrates the effects of channel length modulation on the drain-source current of a transistor.

(5) FIGS. 3b to 3d illustrate various example experimental results.

(6) FIG. 4 shows the flow chart of an example method for mirroring a voltage.

DETAILED DESCRIPTION

(7) As outlined in the background section, the present document describes current sensing circuits, in particular lossless current sensing circuits which may be used as current sensing circuits for DC/DC converters, for fast switching, as well as for controlled active current sources, and/or for amplifier/LDO overcurrent detection/protection circuits.

(8) The current sensing circuit is described in the following for sensing the current through the high side switch of a DC/DC converter. It should be noted that the current sensing circuit can be extended to sense low side devices by providing a complementary circuit (see FIG. 2b) to be used for other topologies.

(9) As will be outlined in the context of FIGS. 1a to 1c, conventional current sensing circuits exhibit various disadvantages. In particular, significant static offsets may be introduced by channel length modulation effects (as is the case for the circuit shown in FIG. 1a), and/or the circuits may provide strongly decreased open loop gains and/or exhibit increased circuit areas (as is the case for the circuit shown in FIG. 1b), and/or the circuits may have a complex architecture and may require a significantly higher minimum supply voltage, an increased circuit area and an increased current consumption (as is the case for the circuit shown in FIG. 1c).

(10) The current sensing circuit described in the present document addresses these technical problems. In particular, the described current sensing circuit yields a static offset reduction, maintains a relatively high gain bandwidth and a relatively high open loop gain, and may be operated with a relatively low minimum supply voltage. The current sensing circuit may be implemented at reduced cost and makes use of an internal feed-forward. In particular, no additional amplifiers and/or loops which require compensation are introduced.

(11) FIG. 1a shows the circuit diagram of an example current sensing circuit 100. The current sensing circuit 100 comprises the resistors R1 101 and R2 102 which represent the on-resistances Ron of the high side transistor of a DC-DC converter (R1 101), when in on-state, and the on-resistances Ron of a mirror transistor (R2 102). Typically, R2 102 is significantly larger than R1 101 (e.g. R2=1000 times R1), which can be implemented by using transistors having different aspect ratios (e.g. different widths). By doing this, the losses of the current sensing circuit 100 can be reduced.

(12) The current sensing circuit 100 further comprises a voltage mirror or a current conveyer 110. The voltage mirror 110 comprises current sources using the transistors Mcs1 112 and Mcs2 114 (also referred to as current source transistors) and gain stages using the transistors M1 111 and M2 113 (also referred to as gain transistors). The V.sub.DS voltage of the M.sub.CS1 transistor 112 is close to the supply voltage minus the V.sub.Gs voltage of the M.sub.1 transistor 111 (by way of example, for a 5V supply voltage, the V.sub.DS voltage of the M.sub.CS1 transistor 112 is above 4V). On the other hand, the V.sub.DS voltage of the M.sub.CS2 transistor 114 is equal to the V.sub.GS voltage of the M.sub.out transistor 115 (e.g. around 1V). Due to the channel length modulation (CLM) effect of metaloxide semiconductor field effect transistors (MOSFET) illustrated in FIG. 3a, the different V.sub.DS voltage at the transistors 112, 114 leads to a difference in the current through the transistors 112 and 114. In other words, the difference in V.sub.DS voltage has an effect on the current generated by both current sources 112, 114.

(13) The current generated within the current sources is stimulated by the bias current provided by the bias current source 103 and mirrored onto the M.sub.CS1 transistor 112 using the current mirror formed by the bias current transistor 104 and the M.sub.CS1 transistor 112. In a similar manner, the bias current provided by the bias current source 103 is mirrored onto the M.sub.CS2 transistor 114 using the current mirror formed by the bias current transistor 104 and the M.sub.CS2 transistor 114.

(14) Within the gain stage, the V.sub.DS voltage of the M.sub.1 transistor 111 is equal to its V.sub.GS voltage (e.g. around 1 V) and the V.sub.DS voltage of the M.sub.2 transistor 113 is close to the supply voltage minus the V.sub.GS voltage of the M.sub.out transistor 115 (e.g. for a 5V supply voltage, the V.sub.DS voltage of the M.sub.2 transistor 113 is above 4V). This difference has an effect on the current flowing in both transistors 111, 113. In other words, due to the channel length modulation (CLM) effect, the different V.sub.DS voltages of the gain transistors 111, 113 yield a different current flowing through the gain transistors 111, 113.

(15) As such, the CLM effect introduces errors at the current sources and the gain stages of the voltage mirror 110. These errors cause a higher voltage at the node “D” 108 (compared to the voltage at the node “C” 109), i.e. at the gate of the M.sub.out transistor 115. This induces the voltage at node “B” 107, i.e. at the drain of the M.sub.out transistor 115 to be reduced and to be smaller than the voltage at node “A” 106 (i.e. the voltage at the source of the M.sub.1 transistor 111). However, in order to provide a correct indication of the current through the resistor R2 101, the voltage at the nodes “A” 106 and “B” 107 should be equal. In particular, a feedback loop of the DC-DC converter typically controls the current flowing through the resistor R.sub.2 101 under the assumption that the voltages in nodes “A” 106 and “B” 107 are the same.

(16) As such, the current sensing circuit 100 of FIG. 1a introduces a relatively large static offset which is caused by the channel length modulation effect. This offset also depends on the level of the supply voltage.

(17) The offset may be reduced e.g. by using cascode transistors (typically comprising two or more transistors) in the current source and gain stage (for the transistors 111, 112, 113, 114). However, the use of cascode transistors typically strongly reduces the bandwidth of the amplifier and increases the required minimum supply voltage of the current sensing circuit, as well requires increased silicon area.

(18) FIG. 1b illustrates a current sensing circuit 120 comprising a voltage mirror 130 using a PMOS transistor as an output transistor M.sub.out 135 (instead of an NMOS transistor 115 used in circuit 100). The gate of the PMOS transistor 135 (node “D” 108) is coupled to the drain of the M.sub.CS1 transistor 112 (instead of the drain of the M.sub.CS2 transistor 114). In this case, the voltages at the nodes “D” 108 and “C” 109 are close to each other, thereby causing the V.sub.DS voltages of the M.sub.CS1 transistor 112 and of the M.sub.CS2 transistor 113 to be the same. In a similar manner, the V.sub.DS voltages of the M.sub.1 transistor 111 and of the M.sub.2 transistor 113 are the same. Hence, the current sensing circuit 120 does not exhibit an offset. However, the disadvantage of this solution is a reduced open loop gain, because the output transistor 135 is working as a voltage follower and has a gain of 0 dB. Due to changes of the voltage in node “C” 109 subject to changing I.sub.load current 105, the size of the output PMOS transistor 135 typically has to be significantly larger than the NMOS transistor 113. As a result, the circuit area of the output transistor 135 is significantly increased and the bandwidth of the current sensing circuit is decreased.

(19) FIG. 1c shows the circuit diagram of another example current sensing circuit 140. The voltage mirror 150 of FIG. 1c comprises an additional amplifier 156 (e.g. an operational amplifier) which is used to minimize the channel length modulation effect. The M.sub.1 and M.sub.2 transistors are implemented as NMOS transistors 151, 153 (instead of PMOS transistors). This makes the voltages at the nodes “C” 109 and “D” 108 the same. In this case, the current sources (i.e. the M.sub.CS1 and M.sub.CS2 transistors 112, 114) are delivering the same current.

(20) The solution of FIG. 1c has various drawbacks. The offset seen between nodes “A” 106 and “B” 107 is determined by the offset of the amplifier 156 and the open loop gain of the amplifier 156. The bandwidth of the loop may be strongly reduced if the amplifier 156 is a standard OTA (Operational Transconductance Amplifier), as voltage amplifiers typically have a much smaller bandwidth than current amplifiers. Furthermore, the current sensing circuit 140 of FIG. 1c typically requires an increased current consumption. In addition, the minimum supply voltage required for operating the current sensing circuit 140 is higher than for the circuits 100, 120 of FIGS. 1a and 1 b.

(21) In the present document, it is proposed to make use of an offset compensation circuit to remove the offset incurred by the current sensing circuit 100 of FIG. 1a. As a result of such an offset compensation circuit, a current sensing circuit may be provided, which exhibits a reduced static offset, a relatively high gain bandwidth and a relatively high open loop gain, and which may be operated at relatively low supply voltages. An example current sensing circuit 200 comprising an offset compensation circuit 211 is illustrated in FIG. 2a. The offset compensation circuit 211 comprises the gain transistor M.sub.3 212 (also referred to as the intermediate gain transistor 212) and the current source transistor M.sub.CS3 213 (also referred to as the intermediate current source transistor 213). The dimensions of the gain transistor M.sub.3 212 and the current source transistor M.sub.CS3 213 are preferably selected such that the mirror factor between the gain transistors M.sub.3 212 and M.sub.2 113 is the same as between the current source transistors M.sub.CS3 213 and M.sub.CS2 114. i.e. 1/K=N/M. Furthermore, the current source transistors M.sub.CS3 213 and M.sub.CS2 114 are preferably chosen in a way that the V.sub.GS voltage of the transistor M.sub.CS3 213 is close to the V.sub.GS voltage of the M.sub.out transistor 115.

(22) Notably when using the above mentioned dimensions, the V.sub.Ds voltages of the current source transistors M.sub.CS3 213 and M.sub.CS2 114 are close to each other and by consequence, the channel length modulation effect is reduced. The current flowing in the gain transistor M.sub.3 212 is increased with respect to the current flowing in the gain transistor M.sub.1 111 due to the channel length modulation effect. This increased current is mirrored in the current mirror formed by the transistors M.sub.CS2 114 and M.sub.CS3 213. But because the \f.sub.DS voltage of the transistor M.sub.3 212 is close to the V.sub.DS voltage of the transistor M.sub.2 113, the channel length modulation effect in transistor M.sub.2 113 is compensated.

(23) FIG. 2b illustrates a circuit diagram of a complementary current sensing circuit 220. In the complementary circuit, the nodes “A” 106 and “B” 107 are at the bottom of the circuit 220. The current sensing circuit 220 is configured to sense the current through node “A” 106. The current sensing circuit 220 may be used to sense the current through the low side switch of a half bridge (used e.g. in a DC/DC converter).

(24) FIG. 2c illustrates a circuit diagram of an example active current source 240 which is configured to provide a current Isink 241. The current source 240 is configured to switch between an on-state and an off-state very rapidly.

(25) As indicated above, FIG. 3a illustrates the channel length modulation effect. FIG. 3a shows the drain-source current I.sub.DS 301 through a transistor as a function of the drain-source voltage V.sub.DS 303. It can be seen that the drain-source current I.sub.DS varies in the interval 302, subject to the drain-source voltage V.sub.DS varying in the interval 304.

(26) FIGS. 3b to 3d illustrate various experimental results for the current sensing circuits illustrated in FIGS. 1a to 1c and 2a. All circuits 100, 120, 140, 200 have been designed with 5V transistors in CMOS 130 nm technology. For the current sensing circuit 140 comprising an additional amplifier 156 the following parameters were taken: an open loop DC gain of 60 dB and a bandwidth of 10 MHz. In all circuits, the resistor value ratio between R1 101 and R2 102 was 1 to 1000.

(27) FIG. 3b shows a comparison of the open loop gain 310 of the different circuits, which was performed with a 5V supply voltage and a 1A load current I.sub.load 105. FIG. 3b shows the open loop gain 310 as a function of frequency 311. It can be seen that the bandwidth of the circuit 200 (curve 315) is similar to the bandwidth of the circuit 100 (curve 314) and significantly improved compared to the bandwidths of the circuits 120 (curve 312) and 140 (curve 313). In particular, the proposed circuit 200 exhibits a bandwidth which is increased by around 25% compared to the bandwidth of circuit 140. This increased bandwidth is due to the increased output impedance in the M.sub.2 and M.sub.CS2 transistors 113, 114. On the other hand, the DC gain 310 of circuit 200 is decreased by less than 1 dB with respect to the circuit 100 of FIG. 1a.

(28) FIG. 3c shows an offset 320 vs. load current 321 diagram. The simulations have been performed with a 5V supply voltage. It can be seen that the offset of the circuit 200 (curve 325) is significantly decreased compared to the offset of the circuit 100 (324), and similar to the offset of the circuits 120 (curve 322) and 140 (curve 323). As such, the derivative of the offset for the circuit 100 is in the same range as for the circuits 120 and 140, however, without the need of an additional amplifier and/or without using a PMOS output transistor. Furthermore, the static value is cancelled out.

(29) FIG. 3d shows an example offset 330 vs. supply voltage 331 diagram. The simulations have been performed with a 1A load current. It can be seen that the circuit 200 (curve 335) is able to work with very small supply voltages. This is advantageous e.g. in mobile (battery supplied) devices which are regularly operated at relatively small supply voltages. Mobile devices are designed in a way to fully use up the electrical energy stored within a battery of the device, and by consequence the mobile devices are regularly operated at relatively low supply voltages. The simulations show that the offset (curve 335) of the circuit 200 is well controlled down to a supply voltage of 1.3V, whereas for the circuit 140 (curve 333) with additional amplifier, the minimum supply voltage is above 2.2V assuming that the voltage amplifier keeps its parameters for this voltage range. Furthermore, it can be seen that the circuit 100 (curve 334) shows a very strong offset voltage dependency for supply voltage changes. In addition, it can bee seen that the offset for circuit 200 (curve 335) is reduced compared to the offset of circuit 120 (curve 332).

(30) FIG. 4 shows the flow chart of an example method 400 for mirroring a voltage level from an input node to an output node. In particular, the method 400 is directed at aligning the voltage level at the output node 107 with the voltage level at the input node 106. The method 400 comprises the step of providing 401 a bias current using an input current source transistor 112. Furthermore, the method 400 comprises providing 402 the bias current to an input gain transistor 111 arranged in series with the input current source transistor 112. Typically, the voltage level at the input node 106 corresponds to the voltage drop across the input current source transistor 112 and the input gain transistor 111. The method 400 may comprise mirroring 403 the bias current from the input gain transistor 111 to an intermediate gain transistor 212, thereby yielding the intermediate current. Furthermore, the method 400 may comprise providing 404 the intermediate current to an intermediate current source transistor 213 arranged in series with the intermediate gain transistor 212. In addition, the method 400 may comprise mirroring 405 the intermediate current from the intermediate current source transistor 213 to an output current source transistor 114, thereby yielding the output current. The method 400 may also comprise providing 406 the output current 406 to an output gain transistor 113 arranged in series with the output current source transistor 114. Typically, the voltage level at the output node 107 corresponds to the voltage drop across the output current source transistor 114 and the output gain transistor 113.

(31) It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiment outlined in the present document are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the proposed methods and systems. Furthermore, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.