Output stage for class AB amplifier

Abstract

The invention relates to a class AB amplifier for receiving an input current and generating an amplified output current and having first and second output transistors connected to provide the output current, wherein if the input current is less than a threshold the first output transistor is enabled and the second output transistor is disabled, and if the input current exceeds a threshold the second output transistor is enabled.

Claims

1. A class AB amplifier for receiving an input current and generating an amplified output current and having first, second, third, and fourth output transistors connected to provide the output current, wherein the first and third output transistors are configured to be enabled and the second and fourth output transistors are configured to be disabled when the input current is less than a threshold, and the second and fourth output transistors are configured to be enabled when the input current exceeds the threshold, and wherein the second output transistor is physically larger than the first output transistor.

2. The class AB amplifier of claim 1 wherein the first and second output transistors form part of first and second current mirrors.

3. The class AB amplifier of claim 2 further comprising first and second input transistors for controlling the first and second current mirrors in dependence on the input current.

4. The class AB amplifier of claim 3, wherein threshold voltages of the first and second input transistors are different, such that the first input transistor is responsive to input currents below the threshold and the second input transistor is responsive to input currents above the threshold.

5. The class AB amplifier of claim 3, wherein a voltage at at least one of a control node of the first input transistor or a control node of the second input transistor is fixed.

6. The class AB amplifier of claim 5, wherein the voltage at the at least one of the control node of the first input transistor or the control node of the second input transistor is set by a current source and a diode-connected transistor.

7. The class AB amplifier of claim 1 wherein the first and second output transistors are respectively connected to provide the output current through cascode transistors.

8. The class AB amplifier of claim 1, wherein the first and second output transistors are connected to a first polarity of a supply voltage, and wherein the third and fourth output transistors are connected to a second polarity of the supply voltage.

9. The class AB amplifier of claim 1, wherein the fourth output transistor is physically larger than the third output transistor.

10. The class AB amplifier of claim 1, wherein the third and fourth output transistors form part of third and fourth current mirrors.

11. The class AB amplifier of claim 10 further comprising third and fourth input transistors for controlling the third and fourth current mirrors in dependence on the input current.

12. The class AB amplifier of claim 11, wherein threshold voltages of the third and fourth input transistors are different, such that the third input transistor is responsive to input currents below the threshold and the fourth input transistor is responsive to input currents above the threshold.

13. The class AB amplifier of claim 11, wherein a voltage at at least one of a control node of the third input transistor or a control node of the fourth input transistor is fixed.

14. The class AB amplifier of claim 13, wherein the voltage at the at least one of the control node of the third input transistor or the control node of the fourth input transistor is set by a current source and a diode-connected transistor.

15. The class AB amplifier of claim 10, wherein the third and fourth output transistors are respectively connected to provide the output current through cascode transistors.

16. A method of controlling a class AB amplifier for receiving an input current and generating an amplified output current and having first second, third, and fourth output transistors connected to provide the output current, wherein the second output transistor is physically larger than the first output transistor, comprising: enabling the first and third output transistors and disabling the second and fourth output transistors when the input current is less than a threshold; and enabling the second and fourth output transistors when the input current exceeds the threshold.

17. The method of claim 16, wherein the first and second output transistors of the class AB amplifier form part of first and second current mirrors, wherein first and second input transistors control the first and second current mirrors in dependence on the input current, and wherein threshold voltages of the first and second input transistors are different, the method further comprising: enabling the first input transistor responsive to input currents below the threshold; and enabling the second input transistor responsive to input currents above the threshold.

18. The method of claim 16, wherein the first and second output transistors are connected to a first polarity of a supply voltage, and wherein the third and fourth output transistors are connected to a second polarity of the supply voltage.

19. A method of controlling a class AB amplifier for receiving an input current and generating an amplified output current and having first and second output transistors connected to provide the output current, wherein the second output transistor is physically larger than the first output transistor, wherein third and fourth output transistors form part of third and fourth current mirrors, wherein third and fourth input transistors control the third and fourth current mirrors in dependence on the input current, and wherein threshold voltages of the third and fourth input transistors are different, the method comprising: enabling the first output transistors and disabling the second output transistors when the input current is less than a threshold; enabling the second output transistors when the input current exceeds the threshold; enabling the third input transistor responsive to input currents below the threshold; and enabling the fourth input transistor responsive to input currents above the threshold.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) The invention is now described with reference to the following figures, in which:

(2) FIG. 1 illustrates a prior art example of a class AB output stage;

(3) FIG. 2 illustrates a gain plot of the prior art arrangement of FIG. 1;

(4) FIG. 3 illustrates an exemplary embodiment of an improvement to a class AB output stage in accordance with the invention;

(5) FIG. 4 illustrates a gain plot of an improved class AB output stage in accordance with the invention;

(6) FIG. 5 illustrates a gain plot; and

(7) FIG. 6 illustrates an improvement to the arrangement of FIG. 3 in accordance with an exemplary example.

DESCRIPTION OF THE PREFERRED EMBODIMENT

(8) In the following description the invention is described with reference to exemplary embodiments and implementations. The invention is not limited to the specific details of any arrangements as set out, which are provided for the purposes of understanding the invention.

(9) In general a class amplifier is provided for receiving an input current and for generating amplified output current. The class amplifier has first and second output transmitters connected to provide the output current. In accordance with a described arrangement, if the input current is less than a threshold then the first output transistor is enabled, and a second output transistor is disabled. If the input current exceeds a threshold then the second output transistor is enabled.

(10) In this way the output current of a class AB amplifier is provided from either physically small or physically large output transistors in accordance with the size of the output current relative to a threshold. The threshold may be implementation-dependent, according to the relative size of the output transistors. The threshold may be compared to the input current signal.

(11) In general, the threshold is set such that the physically smaller output transistors are used when the output signal is smaller, and the physically larger output transistors are used when the output is larger. In practice the threshold may be a range of values, with the larger transistor switching on as the bottom of the range of values is reached.

(12) A modified Class AB amplifier in accordance with an embodiment is shown in FIG. 3.

(13) Comparing FIG. 3 with FIG. 1, high-side (or positive) current mirror arrangement 14 is adapted to comprise of two current mirror arrangements 14a and 14b. Each of the current mirror arrangements 14a and 14b comprises a current mirror arrangement duplicating the current mirror arrangement 14 of FIG. 1. The high-side (or positive) current mirror arrangement 14a comprises transistors M3A and M4A in a current mirror arrangement, and the high-side (or positive) current mirror arrangement 14b comprises transistors M3B and M4B in a current mirror arrangement.

(14) The low-side (or negative) current mirror arrangement 16 is adapted to comprise of two current mirror arrangements 16a and 16b. Each of the current mirror arrangements 16a and 16b comprises a current mirror arrangement duplicating the current mirror arrangement 16 of FIG. 1. The low-side (or negative) current mirror arrangement 16a comprises transistors M5A and M6A in a current mirror arrangement, and the low-side (or negative) current mirror arrangement 16b comprises transistors MSB and M6B in a current mirror arrangement.

(15) The transistor M1 of the FIG. 1 arrangement is split in the FIG. 3 arrangement into two transistors M1A and M1B. The transistor M100 of the FIG. 1 arrangement is split in the FIG. 3 arrangement into two transistors M100A and M100B.

(16) The transistor M2 of the FIG. 1 arrangement is split in the FIG. 3 arrangement into two transistors M2A and M2B. The transistor M200 of the FIG. 1 arrangement is split in the FIG. 3 arrangement into two transistors M200A and M200B.

(17) Each of transistors M100A and M100B is connected to a different bias current, I.sub.bias+1 and I.sub.bias+2 respectively denoted by reference numerals 5A and 5B. This results in a different voltage being formed on the drain terminals of each of transistors M100A and M100B, according to their respective bias currents. In turn, this provides a different voltage on the gate terminals of transistors M1A and M1B. The gate of transistor M1A receives a reference voltage Vref, and the voltage on the gate of transistor M1B is the reference voltage Vref plus the voltage difference between the drains of transistors M100A and M100B. In this way the threshold voltage of the transistors M1A and M1B are effectively different, so that they have different responses to the input current.

(18) The transistor M1A controls the current mirror pair M3A and M4A, and the transistor M1B controls the current mirror pair M3B and M4B.

(19) At low input currents M1A, M3A and M4A only are active. M1B does not conduct, and hence the current mirror arrangement formed of M3B and M4B is disabled. This means that M4A can be sized just enough to handle most of the signal dynamics, which take place at low currents in the crossover region.

(20) As the input current signal increases toward its peak, M1B begins to turn on and begins to shunt current around M1A, and this enables M4B to start contributing to the output. At such higher levels of current M4A begins to approach saturation and the gain drops. At this point, the gain is mainly contributed by M4B.

(21) Thus as the input current approaches and exceeds a threshold, the larger output transistor turns on to provide the larger output current.

(22) Reference can be made to FIG. 4 which shows the operation of an extended class AB amplifier as described.

(23) Reference numeral 302 of FIG. 4 denotes a plot of the gain of the small output stage of FIG. 3, provided by transistor M4A. Reference numeral 304 denotes a plot of the gain of the large output stage of FIG. 3, provided by transistor M4B.

(24) Also denoted in FIG. 4 by reference numeral 300 is a typical distribution of signals that will be encountered when an exemplary amplifier is used as an error amplifier in a switched envelope tracker. This means that any non-linearity contributed by the changeover to the larger stage is negligible. Because of this much reduced size of the smaller stage, the crossover quiescent current can be made much lower, and can be as low as 2% of the overall maximum output current.

(25) The dashed line denoted by reference numeral 306 denotes the error amplifier signal distribution (on a logarithmic scale). As denoted by reference numeral 301, the majority of activity is on the left hand side of the Figure.

(26) The foregoing description describes the operation of the high-side of the class AB amplifier output. In certain arrangements only a high-side may be provided, but in more practical arrangements both a high-side and a low-side arrangement may be provided.

(27) The first and second output transistors may thus be connected to a first plurality of a supply voltage. A third and fourth output transistor may be provided connected to a second plurality of the supply voltage. If the input current is less than a threshold the first and third output transistors may be enabled, and if the input current exceeds the threshold the second and fourth output transistors may be enabled.

(28) The principle of operation for the high-side described above applies equally for the low-side.

(29) Each of transistors M200A and M200B is connected to a different bias current, I.sub.bias−1 and I.sub.bias−2 respectively denoted by reference numerals 7A and 7B. This results in a different voltage being formed on the drain terminals of each of transistors M200A and M200, according to their respective bias currents. In turn, this provides a different voltage on the gate terminals of transistors M2A and M2B. The gate of transistor M2A receives the voltage Vref, and the voltage on the gate of transistor M1B is the reference voltage Vref plus the voltage difference between the drains of transistors M200A and M200B.

(30) The transistor M2A controls the current mirror pair M6A and M5A, and the transistor M2B controls the current mirror pair M6B and M5B.

(31) At low input currents M2A, M6A and M5A only are active. M2B does not conduct, and hence the current mirror arrangement formed of M6B and M5B is disabled. This means that M5A can be sized just enough to handle most of the signal dynamics, which take place at low currents in the crossover region.

(32) As the input current signal decreases toward its negative peak, M2B begins to turn on and begins to shunt current around M2A, and this enables M5B to start contributing to the output. At such higher levels of current M5A begins to approach saturation and the gain drops. At this point, the gain is mainly contributed by M5B.

(33) Thus it can be understood that in the main region of operation—the crossover region—where output currents are relatively low, output transistors M4A and M5A are used to provide the output current which are appropriately sized for small currents. At the regions of operation where higher currents are required, different output transistors M4B and M5B—appropriately sized to handle larger currents—are used.

(34) Some means of providing the correct gate voltage between M1A and M1B (and M2A and M2B) is preferably required, which is preferably arranged to account for changes in process and temperature. This may be achieved by the use of replica transistors for the transistors M1A and M1B, that are reduced size compared to transistor M1 in FIG. 1, but the same geometries as M1 of FIG. 1. The same applies for the transistors M2A and M2B.

(35) The offset voltage necessary to generate the segmentation in current drives is obtained by providing two different bias currents in each side, which in the high side are denoted I.sub.bias+1 and I.sub.bias+2. Current I.sub.bias+1 is preferably proportional to the intended crossover current, whereas I.sub.bias+2 represents the transition current to the higher current segment.

(36) It can be understood that the segmentation of drive currents may be obtained by some other means, and the embodiment illustrated in FIG. 3 is merely exemplary.

(37) The effect on the bandwidth of the Class AB amplifier of FIG. 3 is illustrated with respect to FIG. 5. The analysis is simplified by assuming that each stage (M3A/M4A and M3B/M4B on the positive side) has identical gain.

(38) The small stage, provided by current mirror arrangements M3A/M4A and M5A/M6A has a gain plot 510 and a pole at β denoted by reference numeral 502. The large stage, provided by current mirror arrangements M3B/M4B and M5B/M6B, has a gain plot 508 and a lower frequency pole α denoted by reference numeral 506, as the larger transistors have a lower current density.

(39) When the sum of the two poles are factored as shown by the gain plot 512 of FIG. 5, the low frequency pole appears at the output, but is cancelled by a zero at (α+β)/2. The high frequency response is therefore dominated by the pole at β, and there is little negative impact on the phase margin of the complete amplifier.

(40) The phase of the prior art and the extended output stage are compared in FIG. 5. At low frequencies the extended stage has extra lag, but at higher frequencies when the amplifier unity gain is to be achieved, there is little difference between the two stages. As the current increases then the pole at α will begin to dominate, but at that point the pole will be at a high enough frequency to avoid comprising the output bandwidth.

(41) With reference to FIG. 6, a further optional enhancement to the arrangement of FIG. 3 is illustrated.

(42) A cascade transistor M7 is connected between transistor M4A and the current output, cascade transistor M8 is connected between transistor M4B and the current output, a cascade transistor M9 is connected between transistor M5A and the current output, and a cascade transistor M10 is connected between transistor M5B and the current output. The gates of the transistors M7 and M8 receive a voltage from a voltage source V.sup.+ 602 connected between the gates and V.sub.DD. The gates of the transistors M9 and M10 receive a voltage from a voltage source V.sup.− 604 connected between the gate and V.sub.ss.

(43) These additional cascode transistors M7, M8, M9, M10 introduce the benefit of separating the poles in each output transistor, thus maintaining bandwidth.

(44) A disadvantage is associated in using such a cascade arrangement, in that the transistors M4A and M5A must be made larger to accommodate the extra transistor in the output path. However in the presence of the parallel paths presented in the described arrangements, this is not a significant issue and the advantages of the cascade stage can be fully realised.

(45) The invention has been described herein by way of example with reference to embodiments. The invention is not limited to the described embodiments, not to specific combination of features in embodiments. Modifications may be made to the embodiments within the scope of the invention. The scope of the invention is defined by the appended claims.