Electronic drive circuit

Abstract

An electronic circuit includes an input configured to receive an input signal and an output configured to be coupled to load, an output transistor including a load path and a control node, the load path being connected between the output and a first supply node, a drive transistor including a load path and a control node, the load path being connected to the control node of the output transistor, a first electronic switch connected in series with the load path of the drive transistor, a biasing circuit including an internal impedance and connected between the control node of the drive transistor and the first supply node, and a control circuit configured to receive the input signal and to drive the first electronic switch based on the input signal.

Claims

1. An electronic circuit, comprising: an input configured to receive an input signal and an output configured to be coupled to a load; an output transistor comprising a load path and a control node, the load path being connected between the output and a first supply node; a drive transistor comprising a load path and a control node, the load path of the drive transistor being connected to the control node of the output transistor; a first electronic switch connected in series with the load path of the drive transistor; a biasing circuit comprising an internal impedance and connected between the control node of the drive transistor and the first supply node; and a control circuit configured to receive the input signal and to generate a first drive signal for driving the first electronic switch based on the input signal, the first drive signal having an on-level and an off-level which depend on a state of the input signal.

2. The electronic circuit of claim 1, wherein the first electronic switch is connected between the load path of the drive transistor and a second supply node.

3. The electronic circuit of claim 1, further comprising: a second electronic switch connected between the control node of the output transistor and the first supply node, wherein the control circuit is configured to generate a second drive signal for driving the second electronic switch based on the input signal, the second drive signal having an on-level and an off-level which depend on the state of the input signal.

4. The electronic circuit of claim 3, wherein the control circuit is configured to drive the first electronic switch and the second electronic switch such that at most one of the first electronic switch and the second electronic switch is driven in an on-state at the same time.

5. The electronic circuit of claim 1, further comprising: a resistor connected between the control node of the output transistor and the first supply node.

6. The electronic circuit of claim 1, wherein the internal impedance of the biasing circuit comprises at least one of a resistor and a capacitor connected between the control node of the drive transistor and the first supply node.

7. The electronic circuit of claim 6, wherein the drive transistor has an internal gate-drain capacitance, and wherein a capacitance of the capacitor is at least 10 times a capacitance value of the gate-drain capacitance.

8. The electronic circuit of claim 6, wherein the drive transistor has an internal gate-source capacitance, and wherein a capacitance of the capacitor is at least 5 times a capacitance value of the gate-source capacitance.

9. The electronic circuit of claim 1, wherein the output transistor and the drive transistor have the same conductivity type.

10. The electronic circuit of claim 9, wherein the first electronic switch is implemented as a transistor of a conductivity type complementary to the conductivity type of the output transistor and the drive transistor.

11. The electronic circuit of claim 1, wherein the biasing circuit further comprises a voltage regulator having a supply input connected between the first supply node and a second supply node, and having an output coupled to the control node of the drive transistor.

12. The electronic circuit of claim 2, wherein the first supply node is configured to receive a first electrical potential and the second supply node is configured to receive a second electrical potential higher than the first electrical potential, wherein each of the output transistor and the drive transistor is an n-type MOSFET, and wherein the first electronic switch is a p-type MOSFET.

13. The electronic circuit of claim 2, wherein the first supply node is configured to receive a first electrical potential and the second supply node is configured to receive a second electrical potential lower than the first electrical potential, wherein each of the output transistor and the drive transistor is a p-type MOSFET, and wherein the first electronic switch is an n-type MOSFET.

14. The electronic circuit of claim 2, further comprising: a further output transistor comprising a load path and a control node, the load path being connected between the output and a third supply node; a further drive transistor comprising a load path and a control node, the load path being connected to the control node of the further output transistor; a further first electronic switch connected in series with the load path of the further drive transistor; a further biasing circuit comprising an internal impedance and connected between the control node of the further drive transistor and the third supply node; and a further control circuit configured to receive the input signal and to drive the further first electronic switch based on the input signal.

15. The electronic circuit of claim 14, wherein the further first electronic switch is connected between the load path of the further drive transistor and a fourth supply node.

16. The electronic circuit of claim 15, wherein the first supply node and the fourth supply node are connected and the second supply node and the third supply node are connected.

17. The electronic circuit of claim 14, further comprising: a further second electronic switch connected between the control node of the output transistor and the third supply node, wherein the further control circuit is configured to drive the second electronic switch based on the input signal.

18. The electronic circuit of claim 17, wherein the control circuit is configured to drive the further first electronic switch and the further second electronic switch such that at most one of the further first electronic switch and the further second electronic switch is driven in an on-state at the same time.

19. The electronic circuit of claim 14, further comprising: a further resistor connected between the control node of the further output transistor and the third supply node.

20. An electronic circuit, comprising: an input configured to receive an input signal and an output configured to be coupled to a load; an output transistor comprising a load path and a control node, the load path being connected between the output and a first supply node; a drive transistor comprising a load path and a control node, the load path of the drive transistor being connected to the control node of the output transistor; a first electronic switch connected in series with the load path of the drive transistor; a biasing circuit comprising an internal impedance and connected between the control node of the drive transistor and the first supply node; and a control circuit configured to receive the input signal and to drive the first electronic switch based on the input signal, wherein the biasing circuit further comprises a voltage regulator having a supply input connected between the first supply node and a second supply node, and having an output coupled to the control node of the drive transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so that only aspects necessary for understanding these principles are illustrated. The drawings are not to scale. In the drawings the same reference characters denote like features.

(2) FIG. 1 shows an electronic drive circuit according to one embodiment;

(3) FIG. 2 shows timing diagrams of an input signal and of signals occurring in the electronic drive circuit shown in FIG. 1;

(4) FIG. 3 shows timing diagrams illustrating one way of operation of the electronic drive circuit shown in FIG. 1;

(5) FIG. 4 shows one embodiment of a biasing circuit in the electronic drive circuit;

(6) FIG. 5 shows one embodiment of a voltage regulator in the biasing circuit shown in FIG. 4 in greater detail;

(7) FIG. 6 shows an electronic drive circuit according to another embodiment;

(8) FIG. 7 shows timing diagrams illustrating one way of operation of the electronic drive circuit shown in FIG. 1; and

(9) FIG. 8 shows an electronic drive circuit according to yet another embodiment.

DETAILED DESCRIPTION

(10) In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and by way of illustration show specific embodiments in which the invention may be practiced. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

(11) FIG. 1 shows an electronic drive circuit according to one embodiment. This electronic drive circuit is configured to drive a load. In particular, the electronic drive circuit is configured to drive a capacitive load. For example, the capacitive load is an MOS transistor. An MOS transistor, such as a MOSFET or an IGBT, is a voltage controlled semiconductor device that switches on or off dependent on a charging state of an internal gate-source capacitance. Just for the purpose of illustration, FIG. 1 shows a capacitive load Z implemented as a MOSFET, in particular, an n-type enhancement MOSFET. However, this is only an example. Any other type of MOS-transistor may be driven by the electronic drive circuit as well. The internal gate-source capacitance of this MOSFET is represented by a capacitor CGS connected between a gate node G and a source node S of the MOSFET Z.

(12) Referring to FIG. 1, the electronic drive circuit includes an input 11 configured to receive an input signal S.sub.IN and an output 12 configured to be coupled to a load Z. In case the load Z is a MOSFET (as shown in FIG. 1) the output 12 of the electronic drive circuit is connected to the gate node of the MOSFET.

(13) The electronic drive circuit further includes an output transistor 1.sub.1, a drive transistor 2.sub.1, and a first electronic switch 3.sub.1. The output transistor 1.sub.1 includes a load path connected between the output 12 and a first supply node 13.sub.1, and a control node. The drive transistor 2.sub.1 includes a control node, and a load path connected to the control node of the output transistor 1.sub.1 and connected in series with the first electronic switch 3.sub.1. The first electronic switch 3.sub.1 is connected between a second supply node 14.sub.1 and the load path of the drive transistor 2.sub.1.

(14) The electronic circuit may include a second electronic switch 6.sub.1 connected between the control node of the output transistor 1.sub.1 and the first supply node 13.sub.1. Optionally, a resistor 7.sub.1 (illustrated in dashed lines in FIG. 1) is connected in parallel with the second electronic switch 6.sub.1 and, therefore, between the control node of the output transistor 1.sub.1 and the first supply node 13.sub.1.

(15) A biasing circuit 4.sub.1 is connected between the control node of the drive transistor 2.sub.1 and the first supply node 13.sub.1. The biasing circuit 4.sub.1 includes a voltage source 41.sub.1 configured to provide a biasing voltage V4.sub.1, and an internal impedance 42.sub.1. The biasing circuit 4.sub.1 is explained in greater detail herein below. A control circuit 5.sub.1 is configured to receive the input signal S.sub.IN and to drive the first electronic switch 3.sub.1 and the second electronic switch 6.sub.1 based on the input signal S.sub.IN.

(16) The circuit elements explained above, that is, the output transistor 1.sub.1, the drive transistor 2.sub.1, the first electronic switch 3.sub.1, the biasing circuit 4.sub.1, the control circuit 5.sub.1, the second electronic switch 6.sub.1, and the optional resistor 7.sub.1 are part of a first drive circuit 10.sub.1, which will briefly be referred to as first driver or low-side driver in the following. This first driver 10.sub.1 is configured to discharge a capacitive load coupled to the output 12. If, as shown in FIG. 1, the load Z is an enhancement MOSFET and has its gate node coupled to the output 12 the capacitive load is the internal gate-source capacitance CGS of the MOSFET. Discharging this internal capacitance CGS by the first driver 10.sub.1 is equivalent to switching of the MOSFET Z. Thus, if the load Z driven by the electronic drive circuit is an MOS transistor the first driver 10.sub.1 is configured to switch off the MOS transistor. Besides the first driver 10.sub.1 configured to discharge a capacitive load (switch off an MOS transistor) the electronic circuit may include a second driver (not shown in FIG. 1) configured to charge the capacitive load (switch on the MOS transistor).

(17) The first driver 10.sub.1 discharges the capacitive load CGS (switches off the MOS transistor Z) when the output transistor 1.sub.1 is in an on-state (is switched on). In the on-state, the output transistor 1.sub.1 electrically connects the output 12 with the first supply node 13.sub.1. In operation of the first driver 10.sub.1, the first supply 13.sub.1 may be connected to a load terminal of the capacitive load CGS facing away from the output 12 so that the load path of the output transistor 10.sub.1 is connected in parallel with the capacitive load CGS.

(18) In general, the operation state of the output transistor 1.sub.1 is dependent on operation states of the first electronic switch 3.sub.1 and the second electronic switch 6.sub.1, respectively. The output transistor 1.sub.1 is driven in the on-state when the first electronic switch 3.sub.1 switches on and the second electronic switch 6.sub.1 switches off, and the output transistor 1.sub.1 is driven in the off-state when the first electronic switch 3.sub.1 switches off and the second electronic switch 6.sub.1 switches on. The control circuit 8.sub.1 is configured to switch the first electronic switch 3.sub.1 and the second electronic switch 6.sub.1 based on the input signal S.sub.IN such that only one of the first electronic switch 3.sub.1 and the second electronic switch 6.sub.1 is switched on at the same time. In order to prevent a current shoot through, that is, an electrically conducting path between the first supply node 13.sub.1 and the second supply node 14.sub.1, the control circuit 8.sub.1 may be configured to drive the first electronic switch 3.sub.1 and the second electronic switch 6.sub.1 such that there is a delay time (dead time) between switching off one of the first electronic switch 3.sub.1 and the second electronic switch 6.sub.1 and switching on the other one of the first electronic switch and the second electronic switch 6.sub.1.

(19) One way of operation of the control circuit 8.sub.1 is shown in FIG. 2. FIG. 2 shows timing diagrams of the input signal S.sub.IN, the drive signal S3.sub.1 of the first electronic switch 3.sub.1 and the drive signal S6.sub.1 of the second electronic switch 6.sub.1. The input signal S.sub.IN defines the desired operation state of the load Z driven by the electronic switch 10. For the purpose of illustration, it is assumed that the input signal S.sub.IN can have one of two different signal levels, namely a first signal LE1 and a second signal level LE2. The first signal level LE1 indicates that it is desired to switch off the output transistor 1.sub.1, so as to prevent the capacitive load CGS from being discharged, and the second signal level LE2 indicates that it is desired to switch on the output transistor 1.sub.1, so as to discharge the capacitive load CGS. Just for the purpose of illustration, the first level LE1 is a high-level and the second level LE2 is a low-level in the example shown in FIG. 2.

(20) Each of the drive signals S3.sub.1, S6.sub.1 can have one of an on-level, which switches on the respective electronic switch 3.sub.1, 6.sub.1, and an off-level, which switches off the respective switch 3.sub.1, 6.sub.1. When the input signal S.sub.IN has the first level LE1 the control circuit 8.sub.1 switches off the first electronic switch 3.sub.1 by generating an off-level of the drive signal S3.sub.1 and switches on the second electronic switch 6.sub.1 by generating an on-level of the drive signal S6.sub.1. In this operation mode of the first driver 10.sub.1 the output transistor 1.sub.1 is switched off. When the signal level of the input signal S.sub.IN changes from the first level LE1 to the second level LE2 the control circuit 8.sub.1 switches off the second electronic switch 6.sub.1 by generating an off-level of the drive signal S6.sub.1 and, after an optional delay time T.sub.D, switches on the first electronic switch 3.sub.1, by generating an on-level of the drive signal S3.sub.1. In this operation mode of the first driver 10.sub.1 the output transistor 1.sub.1 is switched on.

(21) One way of operation of the first driver 10.sub.1 shown in FIG. 1 is explained in the following. For the purpose of explanation, it is assumed that each of the output transistor 1.sub.1 and the drive transistor 2.sub.1 is an n-type MOSFET, in particular, an n-type enhancement MOSFET. In this case, the control node of the output transistor 1.sub.1 and the drive transistor 2.sub.1, respectively, is the gate node of the MOSFET forming the respective transistor, and the load path is the drain-source path of the MOSFET forming the respective transistor. Referring to FIG. 1, the drain node of the MOSFET forming the output transistor 1.sub.1 (briefly referred to as the drain node of the output transistor 1.sub.1 in the following) is connected to the output 12, and the source node is connected to the first supply node 13.sub.1. The source node of the MOSFET forming the drive transistor 2.sub.1 (briefly referred to as the source node of the drive transistor 2.sub.1 in the following) is connected to the gate node of the output transistor 1.sub.1, and the drain node of the drive transistor 2.sub.1 is connected to the first electronic switch 3.sub.1.

(22) For the purpose of explanation, it is further assumed that the first electronic switch 3.sub.1 and the second electronic switch 6.sub.1 are transistors of complementary conductivity types. In the embodiment shown in FIG. 1, the first electronic switch 3.sub.1 is a p-type MOSFET, in particular, a p-type enhancement MOSFET, and the second electronic switch 6.sub.1 is an n-type MOSFET, in particular, an n-type enhancement MOSFET. The MOSFET forming the first electronic switch 3.sub.1 receives the drive signal S3.sub.1 from the control circuit 8.sub.1 at its gate node. The drain node of this MOSFET forming the first electronic switch 3.sub.1 is connected to the drain node of the drive transistor 2.sub.1, and the source node of the MOSFET forming the first electronic switch 3.sub.1 is connected to the second supply node 14.sub.1. The MOSFET forming the second electronic switch 6.sub.1 receives the drive signal S6.sub.1 from the control circuit 8.sub.1 at its gate node. The drain source path of this MOSFET forming the second electronic switch 6.sub.1 is connected between the gate node of the output transistor 1.sub.1 and the first supply node 13.sub.1. That is, the drain-source path of the MOSFET forming the second electronic switch 6.sub.1 is connected in parallel with an internal gate-source capacitance CGS1.sub.1 of the output transistor 1.sub.1. The output transistor 1.sub.1 further includes an internal gate-train capacitance. However, this capacitance is not explicitly illustrated in FIG. 1.

(23) The drive transistor 2.sub.1 includes an internal gate-source capacitance CGS2.sub.1 and an internal gate-drain capacitance CGD2.sub.1. In FIG. 1, these capacitances are represented by capacitors connected between the gate node and the source node and the drain node, respectively. VGS2.sub.1 and VGD2.sub.1 denote voltages across these capacitances CGS2.sub.1, CGD2.sub.1.

(24) If the first electronic switch 3.sub.1 is implemented as a p-type MOSFET, then, the off-level of the drive signal S3.sub.1 may correspond to the level of the electrically potential V2.sub.1 at the second supply node 14.sub.1, while the on-level may be a signal level that is less than the electrically potential V2.sub.1 at the second supply node 14.sub.1 minus the threshold voltage of this p-type MOSFET 3.sub.1. Those signal levels are shown in FIG. 2. If the second electronic switch 6.sub.1 is an n-type MOSFET, then the off-level of the drive signal S6.sub.1 may correspond to the level of the electrical potential V1.sub.1 at the first supply node 13.sub.1, while the on-level may be a signal level that is higher than the electrical potential V1.sub.1 at the first supply node 13.sub.1 plus the threshold voltage of this n-type MOSFET. These signal levels are also shown in FIG. 2.

(25) An operation mode of the first driver 10.sub.1 in which the output transistor 1.sub.1 is switched off will be referred to as off-state of the first driver 10.sub.1, and an operation mode in which the output transistor 1.sub.1 is switched on will be referred to as on-state of the first driver 10.sub.1. There are applications in which it is desirable for the first driver 10.sub.1 to rapidly switch from the off-state to the on-state, that is, to rapidly switch on the output transistor 1.sub.1. Switching on the output transistor 1.sub.1 includes charging the internal gate-source capacitance CGS1.sub.1 such that the gate-source voltage VGS1.sub.1 across this internal capacitance CGS1.sub.1 rises above the threshold voltage of the output transistor 1.sub.1. In order to rapidly switch on the output transistor 1.sub.1 it is desirable to rapidly charge the internal gate source capacitance CGS1.sub.1 without causing the voltage VGS1.sub.1 to exceed a predefined voltage threshold. The drive transistor 2.sub.1, which has its gate node biased by the biasing circuit 4.sub.1, is capable of rapidly charging the gate-source capacitance CGS1.sub.1 of the output transistor 1.sub.1. This is explained below.

(26) When the first electronic switch 1.sub.1 is in the off-state and the gate-source capacitance CGS1.sub.1 of the output transistor 1.sub.1 has been discharged, then the electrical potential at the source node S2.sub.1 of the drive transistor 2.sub.1 corresponds to the electrical potential V1.sub.1 at the first supply node 13.sub.1 so that the gate-source voltage VGS2.sub.1 of the drive transistor 2.sub.1 corresponds to the biasing voltage V4.sub.1 provided by the biasing circuit 4.sub.1. This biasing voltage V4.sub.1 is such that it is higher than the threshold voltage of the drive transistor 2.sub.1 so that the drive transistor 2.sub.1 is in the on-state. However, a current IDS2.sub.1 through the drive transistor 2.sub.1 is zero until the first electronic switch 3.sub.1 switches on. Before the first electronic switch 3.sub.1 switches on, the electrical potential at the drain node D2.sub.1 of the drive transistor 2.sub.1, which is a circuit node between the drive transistor 2.sub.1 and the first electronic switch 3.sub.1, substantially corresponds to the electrical potential V1.sub.1 at the first supply node 13.sub.1. Thus, a gate-drain-voltage VGD2.sub.1 of the drive transistor 2.sub.1 also equals the biasing voltage V4.sub.1 provided by the biasing circuit 4.sub.1. In FIG. 1, VG2.sub.1 denotes a voltage between the gate node G2.sub.1 of the drive transistor 2.sub.1 and the first supply node 13.sub.1. This voltage will be referred to as gate voltage in the following. In the steady state, before the first electronic switch 3.sub.1 switches on, the gate voltage VG2.sub.1 substantially equals the biasing voltage V4.sub.1.

(27) FIG. 3 shows timing diagrams of the drive signal S3.sub.1 of the first electronic switch 3.sub.1, the gate voltage VG2.sub.1 of the drive transistor 2.sub.1, the gate-source voltage VGS1.sub.1 of the output transistor 1.sub.1, and the current IDS1.sub.1 through the output transistor 1.sub.1. The timing diagrams shown in FIG. 3 begin at a time shortly before the electronic switch 3.sub.1 switches on. Before the first electronic switch 3.sub.1 switches on, the gate-source voltage VGS1.sub.1 of the output transistor 1.sub.1 is zero, the current IDS1.sub.1 (the drain-source current) through the output transistor 1.sub.1 is zero, and each of the gate voltage VG2.sub.1, the gate-source voltage VGS2.sub.1, and the gate-drain voltage VGD2.sub.1 of the drive transistor 2.sub.1 substantially equal the biasing voltage V4.sub.1.

(28) When the control circuit 8.sub.1 switches on the first electronic switch 3.sub.1 based on the input signal S.sub.IN the gate-source capacitance CGS1.sub.1 of the output transistor 1.sub.1 is rapidly charged because the drive transistor 2.sub.1 is already conducting when the first electronic switch 3.sub.1 switches on. The first electronic switch 3.sub.1 switches on as soon as the drive signal S3.sub.1 reaches the threshold voltage of the MOSFET forming the first electronic switch 3.sub.1. As soon as the drive signal S3.sub.1 reaches the threshold voltage a current IDS2.sub.1 with a current level defined by the drive transistor 2.sub.1 flows through the drive transistor 2.sub.1 and into a gate-source capacitance CGS1.sub.1 of the output transistor 1.sub.1. A further increase of the signal level between the gate node and the source node of the first electronic switch 3.sub.1 to above the threshold voltage may reduce the losses occurring in the first electronic switch but does not change the current IDS2.sub.1. This is by virtue of the drive transistor 2.sub.1 being pre-biased by the biasing source 4.sub.1. The level of the current IGS2.sub.1 through the drive transistor 2.sub.1 is substantially defined by the gate-source voltage VGS2.sub.1 of the drive transistor 2.sub.1.

(29) The current IGD2.sub.1 which flows right after the first electronic switch 3.sub.1 switches on, rapidly charges the gate-source capacitance CGS1.sub.1 of the output transistor 1.sub.1, thus causing a rapidly increasing current IDS1.sub.1 through the output transistor 1.sub.1. This current IDS1.sub.1 decreases as the capacitive load CGS is discharged.

(30) Referring to FIG. 3, the gate voltage VG2.sub.1 of the drive transistor 2.sub.1—which corresponds to the gate-source voltage VGS2.sub.1 before the gate-source capacitance CGS1.sub.1 of the output transistor is charged—increases to a voltage level which is above the level of the biasing voltage V4.sub.1 when the electronic switch 3.sub.1 switches on. That is,
VG2.sub.1=V4.sub.1+ΔV  (1),
where ΔV is the increase of the gate potential relative to the biasing voltage V4.sub.1. This increase ΔV of the gate voltage VG2.sub.1, which is equal VGS2.sub.1 at the time of switching on the first electronic switch, results in an increase of the current IDS2.sub.1 as compared to a scenario in which the drive transistor 2.sub.1 is only biased by the biasing voltage 41.sub.1 The reason for this increase ΔV in the gate voltage VG2.sub.1 is as follows.

(31) Basically, there are two effects that cause the gate voltage VG2.sub.1 to increase. The first effect is based on the fact that the gate node G2.sub.1 is capacitively coupled to the drain node D2.sub.1 through the internal gate-drain capacitance CGD. When the first electronic switch 3.sub.1 switches on, the electrical potential VD2.sub.1 at the drain node D2.sub.1 of the drive transistor 2.sub.1 rises from the first supply potential V1.sub.1 to the second supply potential V2.sub.1. By virtue of the capacitive coupling of the gate node G2.sub.1 to the drain node D2.sub.1 the electrical potential at the gate node G2.sub.1 increases as the electrical potential VD2.sub.1 at the drain node D2.sub.1 increases. The internal impedance 42.sub.1 of the biasing circuit 4.sub.1 prevents the biasing circuit 4.sub.1 from instantaneously balancing such increase ΔV of the electrical potential at the gate node G2.sub.1 of the drive transistor 2.sub.1.

(32) According to one embodiment, shown in FIG. 4, the internal impedance 42.sub.1 of the biasing circuit 4.sub.1 includes a parallel circuit with a resistor 422.sub.1 and a capacitor 423.sub.1 between the gate node G2.sub.1 of the drive transistor 2.sub.1 and the first supply node 13.sub.1. The capacitor 432.sub.1 of the biasing circuit 4.sub.1 and the gate-drain capacitance CGD2.sub.1 of the drive transistor 2.sub.1 form a capacitive voltage divider. In the steady state, before the first electronic switch 3.sub.1 switches on, the capacitor 423.sub.1 of the biasing circuit 4.sub.1 has been charged to the biasing voltage V4.sub.1 and the gate-drain capacitance CGD2.sub.1 has been charged to the biasing voltage V4.sub.1. When the electrical potential VD2.sub.1 at the drain node increases the gate voltage VG2.sub.1 of the drive transistor 2.sub.1 increases. It can be shown that right after switching on the first electronic switch 3.sub.1 an increase ΔV′ of the gate voltage VG2.sub.1, as a first approximation, is as follows:

(33) $\begin{array}{cc}\Delta V^{\prime }=\frac{\mathrm{CGD}{2}_1}{\mathrm{CGD}{2}_1+C{423}_1}.Math.\left(V{2}_1-V{1}_1\right),& \left(2\right)\end{array}$
where C423.sub.1 is the capacitance of the capacitor, CGD2.sub.1 is the capacitance value of the gate-drain capacitance. This first approximation neglects the gate-source capacitance CGS2.sub.1 of the drive transistor, that is, it is based on the assumption that the capacitive voltage divider between the drain node D2.sub.1 and the first supply node only includes the gate-drain capacitance CGD2.sub.1 and the capacitor 423.sub.1. If, however, the capacitance of the capacitor 423.sub.1 is significantly higher than the gate-drain capacitance CGD2.sub.1 this assumption is valid. If the gate-source capacitance CGS2.sub.1 is taken into account additionally, the voltage increase ΔV′ is less than the value obtained by applying equation (2). Referring to equation (2), the voltage difference ΔV′ can be adjusted by suitably designing the capacitance C423.sub.1 of the capacitor 423.sub.1 relative to the capacitance value of the gate-drain capacitance CGD2.sub.1.

(34) After switching on the first electronic switch 3.sub.1, an increase of the drive transistor's gate potential VG2.sub.1 to above the level of the biasing voltage V4.sub.1 is not only caused by the increase of the drain potential VG2.sub.1 of the drive transistor 2.sub.1, but is also caused by an increase of the gate-source voltage VGS1.sub.1 of the output transistor 1.sub.1. This is a second effect that causes an increase of the gate voltage VG2.sub.1. The gate node of the output transistor 1.sub.1 is capacitively coupled to the gate node G2.sub.1 of the drive transistor 2.sub.1 via the gate-source capacitance CGS2.sub.1 of the drive transistor 2.sub.1, so that an increase of the gate-source voltage VGS1.sub.1 of the output transistor 1.sub.1 causes an increase of the gate potential VG2.sub.1 of the drive transistor 2.sub.1. As a first approximation, that neglects the gate-drain capacitance CGD2.sub.1, an increase ΔV″ of the gate potential VG2.sub.1 resulting from this effect is given as follows:

(35) $\begin{array}{cc}\Delta V^{″}=\frac{\mathrm{CGS}{2}_1}{\mathrm{CGS}{2}_1+C{423}_1}.Math.\mathrm{VGS}{1}_1,& \left(3\right)\end{array}$
where VGS1.sub.1 denotes the voltage level of the output transistors gate-source voltage, CGS2.sub.1 denotes the capacitance value of the drive transistor's 2.sub.1 gate-source capacitance, and C423.sub.1 denotes the capacitance of the capacitor 423.sub.1 in the biasing circuit 4.sub.1. Based on equation (3) it can be seen that by suitably designing the capacitance of the capacitor 423.sub.1 relative to the capacitance value of the gate-source capacitance CGS2.sub.1 of the drive transistor 2.sub.1 the increase ΔV″ of the gate potential VG2.sub.1 can be limited.

(36) The overall increase ΔV of the gate voltage VG2.sub.1 referred to in equation (1) takes into account both of the effects explained with reference to equations (2) and (3). According to one embodiment, the capacitance C423.sub.1 is adapted to capacitance values of the gate-drain capacitance CGD2.sub.1 and the gate-source capacitance CGS2.sub.1 and to the voltage swings at the drain node D2.sub.1 and the source node S2.sub.1 of the drive transistor such that overall increase ΔV of the gate voltage VG2.sub.1 is between 5% and 25%, in particular between 10% and 20% of the biasing voltage V4.sub.1. According to one embodiment, the capacitance C423.sub.1 of the capacitor 423.sub.1 is at least 10 times, in particular at least 50 times the maximum capacitance value of the gate-drain capacitance CGD2.sub.1. According to one embodiment, the capacitance C423.sub.1 of the capacitor 423.sub.1 is at least 5 times, in particular at least 10 times the maximum capacitance value of the gate-source capacitance CGS2.sub.1.

(37) The supply voltage V2.sub.1−V1.sub.1 between the second supply node 14.sub.1 and the first supply node 13.sub.1 is higher than the biasing voltage V4.sub.1. According to one embodiment, the supply voltage is at least 2 times, at least 3 times, or even at least 5 times the biasing voltage. According to one embodiment, the biasing voltage V4.sub.1 is between 2.5V and 3.5V while the supply voltage is 10V or higher.

(38) Referring to FIG. 3 the gate-source voltage VGS1.sub.1 of the output transistor 1.sub.1 is below the electrical potential VG2.sub.1 at the gate node of the drive transistor 2.sub.1 because the drive transistor 2.sub.1 switches off when the gate-source voltage VGS1.sub.1 of the output transistor 1.sub.1 reaches a voltage level that equals the electrical potential VG2.sub.1 at the gate node G2.sub.1 of the drive transistor 2.sub.1 minus the threshold voltage of the drive transistor 2.sub.1. Thus, the gate-source voltage VGS1.sub.1 of the output transistor 1.sub.1 is always lower than the biasing voltage V4.sub.1 plus the voltage difference ΔV so that the maximum gate-source voltage VGS1.sub.1 of the output transistor can be adjusted by suitably designing the biasing circuit 41.sub.1 in particular, by suitably selecting the biasing voltage V4.sub.1 and the capacitor 423.sub.1. In the biasing circuit 4.sub.1, the resistor 422.sub.1 connected in parallel with the capacitor 423.sub.1 discharges the capacitor 423.sub.1 so that a voltage level of the gate voltage VG2.sub.1 gradually decrease to the level of the biasing voltage V4.sub.1. The rate at which the gate potential VG2.sub.1 decreases is dependent on the time constant of the parallel circuit with the resistor 422.sub.1 and the capacitor 423.sub.1. In general, the rate at which the gate potential VG2.sub.1 decreases is the higher the lower a resistance R422.sub.1 of the resistor 422.sub.1 is, and vice versa.

(39) Referring to FIG. 4, the internal impedance 42.sub.1 includes a further resistor 421.sub.1 connected between the voltage source 41.sub.1 and the gate node G2.sub.1 of the drive transistor 2.sub.1. This further resistor 421.sub.1 defines the biasing circuit's 4.sub.1 capability to counteract a decrease of the gate potential VG2.sub.1 to below the biasing voltage V4.sub.1. The lower a resistance R421.sub.1 of this resistor 421.sub.1 is the faster the biasing circuit 4.sub.1 regulates the gate potential V2.sub.1 from a level of below the biasing voltage V4.sub.1 to a level corresponding to the biasing voltage V4.sub.1.

(40) FIG. 5 shows one embodiment of the voltage source 41.sub.1 in the biasing circuit 4.sub.1 in greater detail. In this embodiment, the voltage source 41.sub.1 is implemented as a linear voltage regulator connected between the first supply node 13.sub.1 and the second supply node 14.sub.1. In this embodiment, the voltage regulator includes an output transistor 411.sub.1 that has a load path connected between the second supply node 14.sub.1 and the parallel circuit with the resistor 422.sub.1 and the capacitor 423.sub.1. The further resistor 421.sub.1 shown in FIG. 4 is defined by the characteristic of the output transistor 411.sub.1 in the embodiment shown in FIG. 5. In particular, the resistor is defined by the transconductance, often referred to as gm, of the output transistor 422.sub.1. In the embodiment shown in FIG. 5, the output transistor 411.sub.1 is implemented as a MOSFET, in particular as an n-type MOSFET. In this voltage regulator 41.sub.1, the output transistor 411.sub.1 is driven such that, in the steady state, the voltage across the parallel circuit with the resistor 422.sub.1 and the capacitor 423.sub.1 corresponds to the biasing voltage V4.sub.1. This biasing voltage V4.sub.1 is defined by a reference current source 412.sub.1 and a further resistor 414.sub.1. The reference current source 412.sub.1 drives a reference current I412.sub.1 through the resistor 414.sub.1 and a MOSFET 415.sub.1 that has its gate node connected to its drain node. A series circuit with the further resistor 414.sub.1 and the further transistor 415.sub.1 is connected between the gate node of the output transistor 411.sub.1 and the first supply node 13.sub.1. According to one embodiment a resistance of the further resistor 414.sub.1 equals a resistance of the resistor 422.sub.1 and the output transistor 411.sub.1 and the further transistor 415.sub.1 are transistors of the same type, in particular, of the same channel width, the same channel length and the same threshold voltage. In this case, the gate-source voltage of the further transistor 415.sub.1 and the gate-source voltage of the output transistor 411.sub.1 are equal, and a voltage V414.sub.1 across the further resistor corresponds to the biasing voltage V4.sub.1. That is, the biasing voltage V4.sub.1 is defined by the level of the reference current I412.sub.1 multiplied with a resistance R414.sub.1 of the further resistor 414.sub.1:
V414.sub.1=V4.sub.1=I412.sub.1.Math.R414.sub.1  (4).

(41) Referring to FIG. 5, a capacitor 413.sub.1 may be connected in parallel with the series circuit including the resistor 414.sub.1 and the transistor 415.sub.1. Referring to the above, the voltage across the series circuit with the resistor 414.sub.1 and the transistor 415.sub.1 is a reference voltage that drives the transistor and defines the biasing voltage V4.sub.1. The gate node of the output transistor 411.sub.1 is capacitively coupled with the output of the voltage regulator 41.sub.1, that is, with the parallel circuit including the resistor 422.sub.1 and the capacitor 423.sub.1. Thus, rapid changes of the biasing voltage V4.sub.1, such as the increase of the biasing voltage at the time of switching on the first electronic switch 3.sub.1, may change the electrical potential at the gate node of the output transistor 411.sub.1 and, therefore, the reference voltage if no additional measures are taken. The capacitor 413.sub.1 filters such changes of the electrical potential at the gate node of the output transistor 411.sub.1 and, therefore, stabilizes the reference voltage.

(42) The electronic circuit 1 with the first driver 10.sub.1 explained above is configured to discharge a capacitive load CGS connected to output 12. FIG. 6 shows one embodiment of an electronic drive circuit that is configured to charge a capacitive load CGS connected to the output 12 based on an input signal S.sub.IN. Like in the embodiment shown in FIG. 1, the capacitive load is a gate-source capacitance of a MOSFET Z.

(43) The electronic circuit shown in FIG. 6 includes a driver 10.sub.2, which will be referred to as second driver or high-side driver in the following. The tropology of the driver 10.sub.2 corresponds to the tropology of the driver 10.sub.1 shown in FIG. 1 to which reference is made. In the drivers 10.sub.1, 10.sub.2 shown in FIGS. 1 and 6 like features have the same reference characters that are only different by a subscript index “1” added to the reference characters in FIG. 1 and a subscript index “2” added to the reference characters in FIG. 6. In particular, the driver 10.sub.2 shown in FIG. 6 an output transistor 1.sub.2, a drive transistor 2.sub.2, and a first electronic switch 3.sub.2. The output transistor 1.sub.2 includes a control node and a load path connected between the output 12 and a first supply node 13.sub.2. The drive transistor 2.sub.1 includes a control node, and a load path connected to the control node of the output transistor 1.sub.2 and connected in series with the first electronic switch 3.sub.2. The first electronic switch 3.sub.2 is connected between a second supply node 14.sub.1 and the load path of the drive transistor 2.sub.1.

(44) The driver 10.sub.2 may include a second electronic switch 6.sub.2 connected between the control node of the output transistor 1.sub.2 and the first supply node 13.sub.2. Optionally, a resistor 7.sub.2 (illustrated in dashed lines in FIG. 6) is connected in parallel with the second electronic switch 6.sub.2 and, therefore, between the control node of the output transistor 1.sub.2 and the first supply node 13.sub.2.

(45) A biasing circuit 4.sub.2 is connected between the control node of the drive transistor 2.sub.2 and the first supply node 13.sub.2. The biasing circuit 4.sub.2 includes a voltage source 41.sub.2 configured to provide a biasing voltage V4.sub.2, and an internal impedance 42.sub.2. A control circuit 5.sub.2 is configured to receive the input signal S.sub.IN and to drive the first electronic switch 3.sub.2 and the second electronic switch 6.sub.2 based on the input signal S.sub.IN.

(46) Referring to FIG. 7, which shows timing diagrams of the input Signal S.sub.IN, a drive signal S3.sub.2 of the first electronic switch 3.sub.2, and a drive signal S6.sub.2 of the second electronic switch 6.sub.2. The input signal S.sub.IN defines the desired operation state of the load Z driven by the electronic switch 10. For the purpose of illustration, it is assumed that the input signal S.sub.IN can have one of two different signal levels, namely a first signal LE1 and a second signal level LE2. The first signal level LE1 indicates that it is desired to switch on the output transistor 1.sub.2, so as to charge the capacitive load CGS, and the second signal level LE2 indicates that it is desired to switch off the output transistor 1.sub.2. Just for the purpose of illustration, the first level LE1 is a high-level and the second level LE2 is a low-level in the example shown in FIG. 7.

(47) Each of the drive signals S3.sub.2, S6.sub.2 can have one of an on-level, which switches on the respective electronic switch 3.sub.2, 6.sub.2, and an off-level, which switches off the respective switch 3.sub.2, 6.sub.2. When the input signal S.sub.IN has the second level LE2 the control circuit 8.sub.2 switches off the first electronic switch 3.sub.2 by generating an off-level of the drive signal S3.sub.2 and switches on the second electronic switch 6.sub.2 by generating an on-level of the drive signal S6.sub.2. In this operation mode of the first driver 10.sub.2 the output transistor 1.sub.2 is switched off. When the signal level of the input signal S.sub.IN changes from the second level LE2 to the first level LE1 the control circuit 8.sub.2 switches off the second electronic switch 6.sub.2 by generating an off-level of the drive signal S6.sub.2 and, after an optional delay time T.sub.D, switches on the first electronic switch 3.sub.2, by generating an on-level of the drive signal S3.sub.2. In this operation mode of the first driver 10.sub.2 the output transistor 1.sub.2 is switched on.

(48) The driver 10.sub.2 shown in FIG. 6 is different from the driver 10.sub.1 shown in FIG. 1 in that the output transistor 1.sub.2 and the drive transistor 2.sub.2 are p-type MOSFETs, wherein the drain node of the output transistor 1.sub.2 is connected to the output 12, and the source node of the drive transistor 2.sub.2 is connected to the gate of the output transistor 1.sub.2. Further, the first electronic switch 3.sub.2 is an n-type MOSFET and the second electronic switch 6.sub.2 is a p-type MOSFET, wherein a source node of the MOSFET forming the first electronic switch 3.sub.2 is connected to the second supply node 14.sub.2. Furthermore, an electrical potential V1.sub.2 at the first supply node 13.sub.2 is higher than an electrical potential V2.sub.2 at the second supply node 14.sub.2.

(49) If, in the driver 10.sub.2 shown in FIG. 6, the first electronic switch 3.sub.2 is implemented as an n-type MOSFET, then the off-level of the drive signal S3.sub.1 may correspond to the level of the electrically potential V2.sub.2 at the second supply node 14.sub.2, while the on-level may be a signal level that is higher than the electrically potential V2.sub.2 at the second supply node 14.sub.2 plus the threshold voltage of this n-type MOSFET 3.sub.2. Those signal levels are shown in FIG. 7. If the second electronic switch 6.sub.2 is a p-type MOSFET, then the off-level of the drive signal S6.sub.1 may correspond to the level of the electrical potential V1.sub.1 at the first supply node 13.sub.1, while the on-level may be a signal level that is lower than the electrical potential V1.sub.2 at the first supply node 13.sub.2 minus the threshold voltage of this p-type MOSFET. These signal levels are also shown in FIG. 7.

(50) Everything that has been explained with regard to the functionality of the first driver 10.sub.1 shown in FIG. 1 applies to the second driver 10.sub.2 shown in FIG. 6 as well. In particular, at the time of switching on the first switch 3.sub.1 the magnitude of the gate voltage VG2.sub.2 of the drive transistor 2.sub.2 increases to above the magnitude of the biasing voltage by virtue of the capacitive coupling of the gate node G2.sub.2 to the drain node D2.sub.2 and the source node S2.sub.2, respectively, and by virtue of the internal impedance 42.sub.2 of the biasing source 4.sub.2. The biasing source may be implemented as explained with reference to FIGS. 4 and 5 herein below, wherein the output transistor (not shown) in the biasing source 4.sub.2 may be implemented as a p-type transistor instead of the n-type transistor 411.sub.1 shown in FIG. 5.

(51) FIG. 8 shows one embodiment of an electronic switch that includes a low side driver 10.sub.1 as shown in FIG. 1 and a high side driver 10.sub.2 as shown in FIG. 6. This electronic circuit is configured to charge the capacitive load CGS or discharge the capacitive load based on the input signal. In this embodiment, the second supply node 14.sub.1 of the low side driver 10.sub.1 is connected to the first supply node 13.sub.2 of the high side driver 10.sub.2 so that the second supply potential V2.sub.1 of the low-side driver 10.sub.1 equals the first supply potential V1.sub.2 of the high-side driver 10.sub.2, that is, V2.sub.1=V1.sub.2=V2. Furthermore, the second supply node 14.sub.2 of the high side driver 10.sub.2 is connected to the first supply node 13.sub.1 of the low side driver 10.sub.1 so that the second supply potential V2.sub.2 of the high-side driver 10.sub.2 equals the first supply potential V1.sub.1 of the low-side driver, that is, V2.sub.2=V1.sub.1=V1. V1 denotes of an electrical potential received at the first supply node 13.sub.1 (the second supply node 142) of the low side driver 10.sub.1 (the high side driver 10.sub.2), and V2 denotes an electrical potential received at the second supply node 14.sub.1 (the first supply node 13.sub.2) of the low side driver 10.sub.1 (the high side driver 10.sub.2). The electrical potential V1 may correspond to the electrical potential at a load terminal of the capacitive load CGS facing away from the output 12.

(52) Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.