Pixel sensor cell for CMOS image sensors with enhanced conversion gain at high dynamic range capability

Abstract

The present invention relates to a pixel sensor cell (1) for a CMOS sensor device comprising: —a photodiode (11) for generating photoelectrons; —a first transfer transistor (12) coupling the photodiode (11) with an intermediate node (IN) and configured to be controlled by a first control signal (TX.sub.1); —a gain reducing capacitance (C.sub.HD) applied on the intermediate node (IN); —a second transfer transistor (14) coupling the intermediate node (IN) with a sense node (SN) and configured to be controlled by a second control signal (TX.sub.2); —an output buffer (15) coupled with the sense node (SN) and configured to amplify a potential on the sense node (SN).

Claims

1. A method for operating a pixel sensor cell comprising: a photodiode for generating photoelectrons; a first transfer transistor coupling the photodiode with an intermediate node in response to a first control signal; a second transfer transistor coupling the intermediate node with a sense node in response to a second control signal; wherein the method comprises: accumulating photoelectrons in the photodiode during a predetermined integration time, the first transfer transistor coupling the photodiode with the intermediate node in response to the first control signal; in a first phase, coupling the intermediate node with the sense node with the second transfer transistor and providing a charge threshold for accumulated photoelectrons so that only excess photoelectrons are allowed to pass to the intermediate node, wherein the potential generated by the excess photoelectrons is read out as high dynamic range sampling output signal; and in a second phase, controlling the second transfer transistor to set a threshold of the second transfer transistor to a potential where the second transfer transistor isolates the intermediate node and the sense node and which is substantially equal or higher than the potential of the intermediate node, coupling the intermediate node with the sense node and reading out the potential on the sense node as a low light sampling output signal; and wherein after resetting the sense node and after the threshold of the second transfer transistor has been set to a potential where the second transfer transistor isolates the intermediate node and the sense node and which is substantially equal or higher than the potential of the intermediate node, reading out a reference sampling output signal, wherein the cell output is further determined depending on the reference sampling output signal.

2. The method according to claim 1, wherein the pixel sensor cell further comprises: a gain reducing capacitance applied on the intermediate node; an output buffer coupled with the sense node and configured to amplify a potential on the sense node.

3. The method according to claim 2, wherein a reset transistor is provided which is configured to receive a reset signal and to selectively couple a supplied reset voltage to the intermediate node.

4. The method according to claim 2, wherein the intermediate node is provided with a gain reducing capacitance which particularly is formed as a p+n junction.

5. The method according to claim 2, wherein a control unit is provided to control operation of the pixel sensor cell by timely providing the first and second control signal.

6. The method according to claim 2, wherein the photodiode is formed as a pinned photodiode.

7. The method according to claim 2, wherein the transistors are formed as MOSFET transistors.

8. The method according to claim 2, wherein the output buffer is formed with a selectable source follower.

9. The method according to claim 2, further comprising a CMOS image sensor including an array of multiple pixel sensor cells.

10. The method according to claim 1, wherein a cell output is determined depending on the low light sampling output signal and the high dynamic range sampling output signal.

11. The method according to claim 10, wherein after the first phase a first reset potential is loaded on the sense node and a second reset potential which is in a range between a pin voltage pin of the photodiode and the first reset potential.

12. The method according to claim 11, wherein after reading out the potential on the sense node as the low light sampling output signal, the second transfer transistor is controlled to electrically merge the intermediate node and the sense node, reset the intermediate and sense nodes onto the first reset potential.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments are described in more detail in conjunction with the accompanying drawings in which:

(2) FIG. 1 shows a schematic of the pixel sensor cell;

(3) FIG. 2 a flowchart for illustrating the operating method for the pixel sensor cell of FIG. 1;

(4) FIG. 3 shows a timing diagram of signals to control the operation of the pixel sensor cell of FIG. 1;

(5) FIGS. 4a to 4f show potential levels for the photoelectrons' path from the photodiode to the sense node during the read-out steps;

(6) FIG. 5 shows a diagram illustrating the conversion gate with two linear ranges; and

(7) FIG. 6 shows a block diagram of a low-noise, high-dynamic CMOS image sensor including the pixel sensor cells of FIG. 1.

DESCRIPTION OF EMBODIMENTS

(8) FIG. 1 depicts a schematic of a pixel sensor cell 1 that has an increased dynamic range and a reduced read-out noise.

(9) As shown in the exemplary circuit of FIG. 1, there is a pinned photodiode 11 substantially formed by a reversely coupled pn junction, a ground terminal 11a of which is connected to a ground potential V.sub.GND and a pin terminal 11b is coupled with a source terminal 12S of a first transfer transistor 12. A gate terminal 12G of the first transfer transistor 12 is applied with a first control signal TX.sub.1, and a drain terminal 12D is coupled to an intermediate node IN.

(10) The intermediate node IN is coupled with a gain reducing capacitance C.sub.HD which may be explicitly or intrinsically formed e.g. by an n+p junction layer. The intermediate node IN is further coupled with a source terminal 13S of a reset transistor 13. A drain terminal 13D of the reset transistor 13 is supplied by a reset voltage V.sub.RST. The gate terminal 13G of the reset transistor 13 is coupled with a supplied reset signal RST.

(11) The intermediate node IN is further coupled with a source terminal 14S of a second transfer transistor 14, while a drain terminal 14D of the second transfer transistor 14 is coupled with a sense node SN. The gate terminal 14G of the second transfer transistor 14 is supplied with a second control signal TX.sub.2.

(12) Furthermore, the sense node SN is coupled with a read-out buffer 15 which is formed in the present embodiment by a selectable (can be enabled and disabled) source follower. The selectable source follower of the read-out buffer 15 may comprise a source follower transistor 16 and a row selection transistor 17 which may be controlled by a row select signal RS to enable the source follower. A drain terminal 16D of the source follower transistor 16 is coupled with a high supply potential VDD, while the source terminal 16S of the source follower transistor 16 is coupled with a drain terminal 17D of the selection transistor 17, while the source terminal 17S of the selection transistor 17 is coupled with an output node ON for obtaining sampling outputs. The gate terminal 16G of the source follower transistor 16 is connected with the sense node SN.

(13) The control signals TX.sub.1, TX.sub.2, RST, RS as well as the reset potential V.sub.RST are provided by a control unit 20 which controls the read-out operation of the pixel sensor cell 1. The control unit 20 controls the operation of the pixel sensor cell 1 to obtain sampling outputs at the sampling node ON.

(14) The operation of the pixel sensor cell 10 is described in detail with respect to the flowchart of FIG. 2, the timing diagram of FIG. 3 and the potential levels in the photoelectron's path of FIGS. 4a to 4f.

(15) Initially, the intermediate node IN and the sense node SN had been reset to a well-defined potential. So, the potential of the intermediate and sense nodes IN, SN corresponds substantially to the reset potential V.sub.RST.

(16) In a step S1 which is also illustrated in FIG. 4a, a threshold TX1L (potential barrier) of the first transfer transistor 12 is set. This is achieved by setting the first control signal TX.sub.1 to a low voltage that blocks charge flow from the photodiode 11 and allows filling the photodiode 11 with an amount of photoelectrons (pin potential V.sub.pin) below the saturation level. In other words, the first transfer transistor 12 is controlled that it forms a potential barrier which isolates the photodiode 11 from the merged intermediate and sense nodes IN, SN when photoelectrons are generated in the photodiode 11. The charge threshold defined by the control of the first transfer transistor 12 by means of the first control signal TX.sub.1 defines a saturation level of a low-light signal.

(17) In step S2, the second transfer transistor 14 is made conductive, so that the intermediate node IN and the sense node SN are coupled/merged. This is achieved by setting the second control signal TX.sub.2 to the highest voltage attracting electrons in the channel area of the second transfer transistor 14 and making the threshold level VTX2H very low.

(18) Under low light conditions, the integrated photoelectrons corresponding to (resulting from) the Low Light Signal (LLS) remain stored in the photodiode 11 as charge generation is too slow for the potential of the photodiode 11 to reach the saturation level. In other words, the gate voltage (of the first control signal TX.sub.1) applied on the first transfer transistor 12 is set to a potential where it prevents the photoelectrons to flow to the intermediate node IN as long as the accumulated charge in the photodiode 11 has not reached a saturation level defined by the potential of the first control signal TX.sub.1.

(19) Under high-light conditions, more photoelectrons are generated during integration time so that the charge in the photodiode 11 overflows as it reaches the saturation level and a part (the overflow) of the generated photoelectrons may pass through the first transfer transistor 12 to the higher potential of the intermediate node IN and the sense node SN which are merged via the conductive second transfer transistor 14.

(20) In a step S3, the sense node SN potential is read-out by means of the output buffer 15 as a first sampling output signal V.sub.HDS, when the row select signal RS activates the output buffer 15. The potential at the sense node SN results from the charge of the photoelectrons which could pass over the saturation level formed by the control of the first transfer transistor 12 in case of high-light conditions. Under low-light conditions, the first sampling output signal V.sub.HDS has a potential associated with the reset potential on the sense node SN indicating the low light condition.

(21) The high dynamic capacitance formed by the gain reducing capacitance C.sub.HD is allowed for high light conditions as the shot noise dominates the read noise. Further a large capacitance is beneficial to ensure a high saturation level which is obtained by merging the gain reducing capacitor C.sub.HD with the MOSFET capacitor of the second transfer transistor 14 and the sense node SN. In low light condition, the photodiode 11 is not completely filled with photoelectrons, and the integrated charge remains in the photodiode 11. In this case, the read noise is the dominating noise source, and a small capacitance at the sense node SN is required.

(22) After the HDS sampling output signal V.sub.HDS has been obtained, a second phase starts in case the light signal is a low light signal so that the amount of remaining charge carriers in the photodiode 11 has to be determined.

(23) In step S4, as also shown in FIG. 4b, by applying of the reset signal RST (high level) on the reset transistor 13 a first reset potential V.sub.RST1 is loaded on the merged intermediate node IN and sense node SN, so that the sense node SN has a predefined potential V.sub.RST1.

(24) After resetting the electrically merged intermediate and sense nodes IN, SN to the first reset potential V.sub.RST1, in a next step S5, the sense node SN is isolated from the intermediate node IN by controlling the second transfer transistor 14 so that it forms a high threshold (high potential barrier) V.sub.TX2L. The threshold V.sub.TX2L is selected so that the intermediate node IN when charged with the photoelectrons of the photodiode 11 remains in the intermediate node IN as shown in FIG. 4c. Substantially, the second control voltage TX.sub.2 is therefore set to its lowest voltage level TX2L.

(25) In step S6, the reset voltage V.sub.RST is then set to a second reset potential V.sub.RST2 which is in a range between the pin voltage V.sub.pin of the photodiode 11 and the stored first reset potential V.sub.RST1 of the sense node SN. The pin voltage V.sub.pin of the photodiode 11 corresponds to a built-in potential like the one of a simple pn junction diode. The pin voltage V.sub.pin is the voltage inside the photodiode 11 when it is completely emptied from electrons. It ranges between 0.6 and 1V and depends on the technology process.

(26) After resetting, the reset transistor 13 is switched off in order to sample the achieved potential level at the intermediate node IN as shown in FIG. 4d. The reset potentials in the intermediate node IN and sense node SN are set to be not equal to ensure that the two nodes are not electrically merged. In case of equal node potentials, the total capacitance of the sense node SN will be the sum of the capacitances of the two nodes SN, IN. With differing reset potentials in the nodes IN, SN the sense node capacitance can be kept as low as possible.

(27) In step S7, the second control signal TX.sub.2 is set to a potential TX2l that makes the potential in the channel of the second transfer transistor 14 equal or slightly higher than the potential of the intermediate node IN as shown in FIG. 4e. In this switching state, the potential of the intermediate node IN is still isolated from the sense node SN so that the higher charge VRST2 of the intermediate node IM can be prevented to flow to the sense node SN even before the first transfer transistor 12 is fully closed. Any charge leaking from the sense node SN during this step just changes slightly the voltage of the sense node SN from VRST1 to a slightly lower value V1. This does not affect the signal because the latter corresponds to the difference between that value V1 and the sense node voltage after the TX.sub.1 is clocked high to remove the barrier between the photodiode 11 and the other nodes IN, SN. Also, by a simple calibration it is possible to obtain the exact voltage to apply on the TX.sub.2 to have the voltage in the channel of the second transfer transistor 14 exactly equal to VRST2.

(28) In step S8, the potential of the sense node SN can be read out as a reference sampling output signal V.sub.Ref which serves as a reference for analyzing a LLS sampling output V.sub.LLS.

(29) In a step S9, the first control signal TX.sub.1 is controlled so that the threshold between the photodiode 11 and the intermediate node IN is lowered to a level between the pin voltage V.sub.pin of the photodiode 11 and the potential of the intermediate node IN. The photoelectrons accumulated in the photodiode 11 transfer directly to the sense node SN and reduce its voltage as shown in FIG. 4f. Substantially, this is achieved by increasing the potential of the first control signal TX.sub.1 to TX1H to a level that set the voltage in the channel to a value between the pin voltage V.sub.pin of the photodiode 11 and the potential of the intermediate node IN. The photogenerated charges accumulated in the photodiode 11 transfer directly to sense node SN and reduce its voltage.

(30) In step S10, the LLS sampling output signal V.sub.LLS can be read-out.

(31) In step S11, the pixel sensor cell 1 is reset by controlling the second transfer transistor 14 to electrically merge the intermediate node IN and the sense node SN, set the reset voltage V.sub.RST to the first reset potential V.sub.RST1 and apply the reset signal RST to bring the intermediate and sense nodes IN, SN onto the first reset potential V.sub.RST1 to set the initial condition.

(32) Hence, three sampling outputs, namely the HDS sampling output signal V.sub.HDS, the reference sampling output signal V.sub.RST, and the HDS sampling output signal V.sub.LLS, can be obtained at the end of each read-out process. The HDS sampling output signal V.sub.HDS corresponds to the high dynamic condition signal, the reference sampling output signal V.sub.ref corresponds to the reset level and the LLS sampling output signal V.sub.LLS corresponds to a low-light condition signal.

(33) In step S12, the overall cell output can now be determined by the sum of the two components as

(34) $V_{\mathrm{out}}=\left(V_{HDS}-V_{ref}\right)+\frac{A_{\mathrm{CD},\mathrm{HD}}}{A_{CD,LL}}\left(V_{LLS}-V_{ref}\right)$
where A.sub.CG,HD and A.sub.CG,LL correspond to the pixel conversion gains for the high dynamic signal and low-light signal read-outs, respectively. The conversion gain is generally determined by

(35) $A_{\mathrm{CG}}=\frac{\frac{1}{n}}{C_{SN}-\frac{2}{3n}{C}_{ox}\mathrm{WL}}.$
wherein n is the slope factor of the read-out buffer 15, C.sub.SN the sense node capacitance C.sub.OX is the oxide capacitance per unit area, and W and L are its gate width and length (of the source follower transistor 16). As shown in the diagram of FIG. 5, the sense node capacitance C.sub.SN is much smaller during the low-light signal read-out so that A.sub.CG,LL is much larger than A.sub.CG,HD.

(36) The overall cell output is a representation of the amount of light detected by the pixel sensor cell 1 and can be further processed.

(37) FIG. 6 shows a configuration of a CMOS image sensor 100, having a plurality of pixel sensor cells 1 arranged in an array. The pixel sensor cells 1 are arranged in rows wherein each row is addressed by its first and second control signals TX.sub.1_1 . . . n, TX.sub.2_1 . . . n, reset signal RST.sub.1 . . . n and row select signal RS.sub.1 . . . n, while each one of the pixel sensor cells 1 of each row have coupled its output nodes ON with a respective column line CL.sub.1 . . . m. A column line is coupled with a column level amplifier and the multiple sampling and ADC unit.