Wide Frequency Range Delay Locked Loop

Abstract

A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Claims

1. A delay locked loop comprising: a digital delay circuit comprising a plurality of identical first delay elements, the digital delay circuit configured to enable the plurality of identical first delay elements to provide coarse phase adjustment in the delay locked loop, and provide a coarse delayed clock signal; an analog delay circuit comprising a plurality of identical second delay elements, each second delay element comprising parallel loads configurable by a control signal to change an effective resistance of the analog delay circuit, the analog delay circuit configured to receive the coarse delayed clock signal, provide fine phase adjustment in the delay locked loop in response to the control signal using the plurality of identical second delay elements, and produce a fine delayed clock signal; a phase detector configured to detect a phase difference between an external clock signal and the fine delayed clock signal; and a lock detector communicatively coupled to the phase detector and the analog delay circuit, the lock detector configured to hold the digital delay circuit at a fixed delay, and provide the control signal to the analog delay circuit.

2. The delay locked loop of claim 1, wherein the coarse delayed clock signal comprises a differential clock signal.

3. The delay lock loop of claim 1, further comprising circuitry for causing a shift of the digital delay circuit when the analog delay circuit approaches a delay limit.

4. The delay lock loop of claim 1, wherein the lock detector is comprised in the digital delay circuit.

5. The delay lock loop of claim 1, wherein the plurality of identical first delay elements are fixed digital delay elements.

6. The delay lock loop of claim 1, wherein the analog delay circuit is in series with the digital delay circuit.

7. The delay lock loop of claim 1, wherein the analog delay circuit is configured to be held at a second fixed delay before the digital delay circuit completes the coarse phase adjustment.

8. The delay lock loop of claim 1, wherein the plurality of identical first delay elements is comprised in a digitally controlled delay line, the digitally controlled delay line further comprising a demultiplexer.

9. The delay lock loop of claim 8, wherein the digitally controlled delay line further comprises a plurality of multiplexers uniformly interspaced between the plurality of identical first delay elements.

10. The delay lock loop of claim 9, wherein each of the plurality of identical first delay elements comprises a fixed digital delay element.

11. A method for performing phase adjustment in a delay locked loop comprising: enabling a plurality of identical first delay elements of a digital delay circuit in providing coarse phase adjustment in the delay locked loop to provide a coarse delayed clock signal; receiving the coarse delayed clock signal at an analog delay circuit of the delay locked loop; applying a fine delay to the coarse delayed clock signal to output a fine delayed clock signal using a plurality of identical second delay elements of the analog delay circuit, each second delay element comprising parallel loads configurable by a control signal to vary the effective resistance of the analog delay circuit, the control signal provided by a lock detector circuit of the delay locked loop; detecting, by a phase detector circuit of the delay locked loop, a phase difference between an external clock signal and the fine delayed clock signal; and holding, by the lock detector circuit, the digital delay circuit at a fixed delay.

12. The method of claim 11, wherein the coarse delayed clock signal comprises a differential clock signal.

13. The method of claim 11, wherein each of the plurality of identical first delay elements comprises a fixed digital delay element.

14. The method of claim 11, further comprising: when a delay limit of the analog delay circuit is approached during the fine phase adjustment, performing one of enabling and disabling an additional second delay element of the digital delay circuit.

15. The method of claim 11, wherein the analog delay circuit operates in series with the digital delay circuit.

16. The method of claim 11, further comprising holding the analog delay circuit at a second fixed delay before the digital delay circuit completes the coarse phase adjustment.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

[0017] FIG. 1 is a block diagram of a prior art analog delay locked loop (DLL);

[0018] FIG. 2 is a graph illustrating the non-linear controlling voltage characteristic for the voltage controlled delay line shown in FIG. 1;

[0019] FIG. 3 is a block diagram of a wide frequency range delay locked loop according to the principles of the present invention;

[0020] FIGS. 4, 4A and 4B illustrates delay cells in the DCDL and the VCDL;

[0021] FIG. 5 is a schematic of one embodiment of any one of the delay cells shown in FIG. 4;

[0022] FIG. 6 is a graph illustrating the non-linear controlling voltage characteristic for the narrow frequency range of the VCDL in the DLL shown in FIG. 3;

[0023] FIG. 7 is a schematic of an embodiment of the lock detector and the analog switch shown in FIG. 3;

[0024] FIGS. 8A-C are timing diagrams illustrating the relationship of the phase detector output to the phase difference between the clocks; and

[0025] FIG. 9 is a timing diagram illustrating signals in the schematic shown in FIG. 7.

DETAILED DESCRIPTION OF THE INVENTION

[0026] While this invention has been particularly shown and described with references to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.

[0027] A description of preferred embodiments of the invention follows.

[0028] FIG. 3 is a block diagram of a wide frequency range delay locked loop (DLL) 300 according to the principles of the present invention. The wide frequency range DLL 300 has two domains of operation: a digital domain which includes a digital delay circuit 302 and an analog domain which includes an analog delay circuit 304.

[0029] In a DLL, high accuracy, small silicon area usage and lower power are typically achieved using an analog technique, while good stability and shorter lock times are typically achieved with a digital technique. The wide frequency range DLL 300 combines the two techniques to provide high accuracy, good stability and a fast lock time over a wide frequency range. The digital delay circuit 302 is responsible for coarse phase adjustment during initialization and the analog delay circuit 304 is responsible for fine phase adjustment during normal operation, after coarse phase adjustment is completed by the digital delay circuit 302. The digital delay circuit 302 operates within the wide delay range and brings the delay locked loop 300 to a stable operation point during power-up initialization. In normal operation, the analog delay circuit 304 operates within a small delay range of the stable operation point within the wide delay range and maintains the delay locked loop at the stable operation point while the digital delay circuit 302 is held at a fixed delay.

[0030] The overall delay provided by the DLL includes a digitally controlled delay line (DCDL) 306 having a set of delay elements, each having a fixed delay and a voltage controlled delay line (VCDL) 312. The combination of the DCDL delay provided by the DCDL 306 and the VCDL delay provided by the VCDL 312 provides an accurate delay. Only one of the domains can vary the DLL delay at any time. At power-up initialization, the digital delay circuit 302 varies the DCDL 306 (coarse delay). After coarse phase adjustment is complete (lock is reached), the DCDL delay is held at a fixed number of DCDL delay elements (frozen) and the analog delay circuit 304 varies the DLL delay to provide fine phase adjustment by varying the VCDL delay.

[0031] The digital delay circuit 302 operates within the wide delay range to bring the DLL 300 to the operation point (lock) quickly to provide a short lock time. A lock detector 310 in the digital delay circuit 302 detects when the digital delay circuit 302 has brought the DLL delay to the stable operation point and enables control of the DLL delay to be switched to the analog delay circuit 304.

[0032] A phase detector 320 detects the phase difference between the external clock signal CK.sub.E and the internal clock signal CK.sub.I. The phase detector 320, can be any phase detector well known to those skilled in the art. In the embodiment shown, the phase detector 320 (FIG. 3) includes a D-type flip-flop with CK.sub.I connected to the clock input and CK.sub.E connected to the D-input. The rising edge of CK.sub.I latches the state of CK.sub.E at the output (Ph_det) of the D-type flip-flop.

[0033] The analog delay circuit 304 includes a multiplexor 314, a VCDL 312 and a charge pump 316. The VCDL 312 is a chain of differential-input-differential-output stages (delay elements) with voltage control. The multiplexor 314 selects the source of the VCDL bias voltage 322 to the VCDL 312. The VCDL bias voltage 322 is a fixed bias voltage V.sub.BPI, V.sub.BNI provided by bias voltage generator 318 or a variable bias voltage V.sub.BP2, V.sub.BN2 provided by charge pump 316. During initialization, before the DCDL 306 achieves lock, differential bias voltage V.sub.BPI, V.sub.BNI provides the VCDL bias voltage 322 through multiplexor 314. Thus, while the digital delay circuit 302 selects the DCDL delay, the VCDL bias voltage 322 provides a constant VCDL delay. That delay may be in the middle of the full delay range of the VCDL to enable fine tuning in both positive and negative directions as discussed below.

[0034] At initialization, the code stored in a counter 308 is initialized to zero, which corresponds to the minimum delay; that is, the minimum number of delay cells in the DCDL 306 that are engaged. The lock detector 310 allows the DCDL 306 to increase the DCDL delay by adding delay cells as the counter 318 is incremented until the nearest rising edge of the internal clock signal CK.sub.I is aligned with the external clock signal CK.sub.E. The counter 308 is incremented by the external clock signal CK.sub.E until lock is reached (the clocks are aligned). In one embodiment, the counter 308 is an up counter which increments on each rising edge of the external clock signal CK.sub.E while enabled by the SW signal from the lock detector 310. Delay cells in the DCDL 306 are added to the DCDL delay line based on the n-bit count value output by the counter 308 to engage the minimum number of DCDL delay cells necessary dependent on the bias voltage V.sub.BP1, V.sub.BN1.

[0035] After the clocks are aligned, the SW signal output by the lock detector 310 disables any further incrementing of the counter 308. The VCDL bias voltage 322 is provided by bias voltage V.sub.BP2, V.sub.BN2, the output of charge pump 316, through multiplexor 314. The charge pump 316 can be any charge pump well known to those skilled in the art.

[0036] By engaging only the minimum number of delay cells in the DCDL 306, the overall delay line is minimum length to minimize noise. Once lock is reached, the digital delay circuit 302 is held at a fixed delay by disabling further incrementing of the counter 308. Only the VCDL portion of the DLL delay line can be varied by the analog delay circuit 304. The analog delay circuit 304 fine tunes the DLL delay to compensate for all drifts and condition changes to keep the external and internal clock signal edges aligned, by varying the VCDL delay, which is added to the fixed delay provided by the DCDL. The analog controlled delay line 310 varies the VCDL delay up or down by varying the bias voltage to the VCDL delay cells 402 based on detected phase difference between the clocks.

[0037] FIG. 4 illustrates delay cells in the DCDL and the VCDL. The digitally controlled delay line (DCDL) includes a chain of DCDL delay cells 400 and the voltage controlled delay line (VCDL) includes a chain of VCDL delay cells 402. The delay of each DCDL cell 400 is fixed by permanently connecting the bias voltage for each DCDL cell 400 to a fixed bias voltage V.sub.BP1, V.sub.BN1. The fixed bias voltage V.sub.BP1, V.sub.BN1 is provided by a bias voltage generator 318 (FIG. 3) which can be any type of voltage stabilizing device, for example, a band-gap reference and need not correspond to the VCDL bias voltage 322 initially applied to the VCDL.

[0038] At initialization, none of the delay elements 400 in the DCDL 306 are engaged. The DLL delay includes only the fixed delay provided by demultiplexor 404, multiplexor 408 and the VCDL delay elements 402 in the VCDL connected to the fixed bias voltage V.sub.BP1, V.sub.BN1. The VCDL delay provided by VCDL is dependent on the fixed bias voltage V.sub.BP1, V.sub.BN1. In the embodiment shown, the DCDL delay cells 400 and the VCDL delay cells 402 are the same delay cell with voltage controlled delay. However, in an alternate embodiment, the DCDL delay cell 400 can differ from the VCDL delay cell 402.

[0039] The DCDL is initially variable by increasing the number of DCDL delay elements 400 with each DCDL delay element 400 having the same delay fixed by the fixed bias voltage V.sub.BP1, V.sub.BN1. In the embodiment shown, during initialization the same fixed bias voltage V.sub.BP1, V.sub.BN1 is coupled to the DCDL delay elements 400 and the VCDL elements 402. However, in alternate embodiments, the fixed bias voltage coupled to the VCDL delay elements 402 and the DCDL delay elements 400 can be different; for example, a first bias voltage may be set to 0.7V.sub.DD coupled to the DCDL and a second bias voltage may be set to 0.5V.sub.DD coupled to the VCDL. The VCDL delay is initially fixed with each of the three VCDL delay elements 402 numbered 1-3 coupled to the fixed bias voltage V.sub.BP1, V.sub.BN1, but the VCDL delay varies with changes in the VCDL bias voltage 322 during normal operation.

[0040] The number of engaged elements in the DCDL 306 is dependent on the n-bit count 406 output by the counter 308. The n-bit count 406 is coupled to the de-multiplexor 404 to select the output of the de-multiplexor 404 through which the external clock is output to the DCDL 306. The n-bit count 406 is also coupled to multiplexor select logic 430 which provides an m-bit multiplexor select signal, with one of the m-bits coupled to each multiplexor in the DCDL 306. In one embodiment the multiplexor select logic 430 is a decoder which decodes the n-bit count to provide the m-bit multiplexor select signal. In the embodiment shown m is 7 and n is 3. There are with six delay elements 400 labeled 4-9. The multiplexor select logic 430 decodes a three bit count 406 to select one of the seven multiplexors through which to forward the external clock as shown in Table 1 below. The Most Significant Bit (MSB) of the seven bit multiplexor select signal corresponds to the select signal for multiplexor 420 and the Least Significant Bit (LSB) of the seven bit multiplexor signal corresponds to the select signal for multiplexor 408. Thus, as the count increases the number of delay elements engaged increases. In an alternate embodiment, the multiplexor select logic can be implemented as a shift register clocked by the external clock and enabled by the SW signal.

TABLE-US-00001 TABLE 1 Count Multiplexor select De-multiplexor select count [2:0] mux_en [6:0] demux_sel[6:0] 000 1111110 1111110 001 1111101 1111101 010 1111011 1111011 011 1110111 1110111 100 1101111 1101111 101 1011111 1011111 110 0111111 0111111

[0041] After lock has been reached, the external clock signal CK.sub.E is delayed through DCDL delay elements engaged dependent on the n-bit count output by counter 308. Control of the DLL delay is switched to the VCDL 312 by switching the bias voltage V.sub.BP1, V.sub.BN1 to the bias voltage V.sub.BP2, V.sub.BN2 through the multiplexor 314 (FIG. 3).

[0042] Thus, the DLL delay includes minimum delay provided by the engaged DCDL delay elements 400 in the DCDL 306 and additional delay provided by the VCDL 312 to provide an accurate DLL delay. The stability of the DLL is increased by using the digital domain to cover a wide delay range to obtain a minimum delay, then freezing the digital domain to allow the analog domain to operate within a small delay range to control the DLL delay. The bias voltage coupled to the VCDL bias voltage 322 is set so that the VCDL does not control the DLL delay until after lock is detected by the digital domain. Before lock, the VCDL merely provides a constant delay independent of the phase difference between the clocks.

[0043] Initially the counter 308 is reset to 0. The de-multiplexor 404 directs the external clock CLK.sub.E to engage delay elements dependent on the n-bit count 406 output by the counter 308. With count 406 set to ‘0’, CLK.sub.E is directed through output 422 of de-multiplexor 404 coupled to multiplexor 408 and no delay DCDL elements 400 are engaged.

[0044] After the counter 308 is incremented to ‘1’ by CLK.sub.E, CLK.sub.E is directed through output 424 of the de-multiplexor 404 by count 406 set to ‘1’ to engage DCDL delay stage labeled 4. Multiplexor 410 is enabled to allow CLK.sub.E through to DCDL delay stage 400 labeled 4 and the m-bit multiplexor select signal output by multiplexor select logic 430 allows delayed CLK.sub.E through multiplexor 408 to the VCDL.

[0045] All six DCDL delay stages are engaged when the count 406 is six, and CLK.sub.E is directed through de-multiplexor output 426 through multiplexors 420, 418, 416, 414, 412, 410, 408 and delay elements labeled 9-4. The DCDL line is frozen when the counter 308 is disabled by the SW signal.

[0046] FIG. 5 is a schematic of one embodiment of any one of the delay elements shown in FIG. 4. The delay cell 400 includes a source-coupled pair of NMOS devices T1, T2 with symmetric loads 500, 502.

[0047] The differential input clock signal CLK.sub.EI−, CLK.sub.EI+, is coupled to the respective gates of NMOS devices T1, T2 with CLK.sub.EI+ coupled to the gate of NMOS device T1 and CLK.sub.EI− coupled to the gate of NMOS device T2. The differential output clock signal CLK.sub.EO−, CLK.sub.EO+, is coupled to the respective drains of NMOS devices T1, T2. The sources of NMOS devices T1 and T2 are coupled and are also coupled to the drain of NMOS current source T3. NMOS current source T3 compensates for drain and substrate voltage variations.

[0048] Symmetric load 500 includes a diode-connected PMOS device T4 connected in parallel with a biased PMOS device T5. Symmetric load 502 includes a diode-connected PMOS device T7 connected in parallel with a biased PMOS device T6. The effective resistance of the symmetric loads 500, 502 changes with changes in the bias voltage V.sub.BP1 resulting in a corresponding change in delay through the delay stage from the differential clock input to the differential clock output.

[0049] FIG. 6 is a graph illustrating the non-linear control voltage characteristic for the narrow delay range of the VCDL 312 in the DLL 300 shown in FIG. 3. In the embodiment shown, the digital domain provides the minimum delay to bring the operating range of the DLL 300 to point B. After lock, the analog domain operates within a narrow delay range 600 from point B-High to point B-Low. This delay range is much smaller than the wide delay range supported by the DLL, but may be controlled by the same large voltage range as applied in the pure analog case of FIG. 2. The small delay range controlled by a large voltage range ensures the stability of the analog domain during normal operation of the DLL.

[0050] As shown, the analog delay circuit 304 operates within the delay range 85 ns to 80 ns over voltage range 200 mV to 800 mV. In contrast to the wide delay range over the same voltage range shown in FIG. 2, a small variation in control voltage (ΔV) does not substantially affect the delay.

[0051] FIG. 7 is a schematic of an embodiment of the lock detector 310 and the multiplexor 314 shown in FIG. 3. The lock detector 310 includes two SR flip-flops 700, 702, AND gate 706 and inverter 704. SR flip-flop 700 detects when the internal clock signal CK.sub.I is within a phase detection window. SR flip-flop 702 detects when the internal clock signal CK.sub.I is in phase with the external clock signal CK.sub.E. Once the internal clock signal CK.sub.I is in phase with the external clock signal CK.sub.E the SW signal is set to logic ‘0’ to disable further changes to the DCDL delay.

[0052] The lock detector output SW is set to logic ‘0’ prior to lock being reached and set to logic ‘1’ after lock is reached. Prior to lock being reached, the logic ‘0’ on the SW signal couples the fixed bias voltage through multiplexor 314 to provide the VCDL bias voltage 322. After lock has been reached, the logic ‘1’ on SW couples the variable bias voltage V.sub.BPN2, V.sub.BPN2 through multiplexor 314 to provide the VCDL bias voltage 322, to allow the VCDL 312 to fine tune the overall delay.

[0053] On power up, the reset signal coupled to the R-input of the SR flip-flop 700 and the SR flip-flop 702 is set to logic ‘1’. Both flip-flops 700, 702 are reset with the respective Q outputs (LC1, SW) set to logic ‘0’. The SR flip-flops 700, 702 remain in a reset state with logic ‘0’ on the respective Q outputs until the phase detector 320 detects that the phase difference between clock signals CK.sub.E, CK.sub.I are in the phase detection window. The phase difference is within the phase detection window while the rising edge of the internal clock signal CK.sub.I is after the falling edge of the external clock signal CK.sub.E. The output of the phase detector (Ph_det) changes to logic ‘0’. The logic ‘0’ on Ph_det changes the S-input of SR flip flop 700 to logic ‘1’ through inverter 704 which sets SR flip-flop 700 (i.e. the Q output changes to logic ‘1’). The delay provided by the DCDL 306 continues to increase further delaying the rising edge of the internal clock signal until the internal clock signal and the external clock signals are in phase. SR flip-flop 702 is set on the next rising edge of Ph-det which occurs when the rising edge of CK.sub.E is detected after the rising edge of CK.sub.I. The Q output of SR flip-flop 702 is set to logic ‘1’. The logic ‘1’ on the output of SR flip-flop 702, the SW signal, disconnects the VCDL bias signal 322 from bias voltage V.sub.BP1, V.sub.BN1 through multiplexor 314 and connects the bias signal V.sub.BP2, V.sub.BN2 from charge pump 316 (FIG. 3) to the VCDL bias signal 322 to the VCDL 312.

[0054] The lock detector 310 remains in a locked state with SW set to logic ‘1’ until the system is reset. While in the locked state, the digital domain no longer controls the delay because, while SW is set to logic ‘1’, the code stored in the counter 308 is frozen to freeze the DCDL delay.

[0055] FIGS. 8A-C are timing diagrams illustrating the relationship of the phase detector output (Ph-det) to the phase difference between the clocks. Referring to FIG. 8A, at initialization, the phase detector 320 (FIG. 3) detects that the internal clock rising edge is after the external clock rising edge. The rising edge of CK.sub.I latches a ‘1’ on the Ph_det output of the D-type flip-flop. The CK.sub.E rising edge continues to increment the code to add additional delay to the DCDL.

[0056] Referring to FIG. 8B, the phase detector detects that the CK.sub.I rising edge is now after the falling edge of CK.sub.E. The rising edge of CK.sub.I latches a ‘0’ on the Ph_det output of the D-type flip-flop. The CK.sub.E rising edge increments the code to add further delay cells to the DCDL.

[0057] Referring to FIG. 8C, the phase detector detects the lock condition when the CK.sub.I rising edge moves after the CK.sub.E rising edge. The rising edge of CK.sub.I latches a ‘1’ on the Ph_det output of the D-type flip-flop.

[0058] FIG. 9 is a timing diagram illustrating signals in the schematic shown in FIG. 7. The timing diagram shows the state of signals in the schematic when the system is reset, upon detecting that the phase detection window has been reached and upon detecting lock. FIG. 9 is described in conjunction with FIG. 3 and FIG. 7.

[0059] At time 900, the system is reset and the reset signal set to logic ‘1’. The reset signal is coupled to the R-inputs of flip-flops 700, 702 to reset the flip-flops. The Ph_det signal is reset to logic ‘1’. The Q outputs (LC1, SW) of both flip-flops are reset to ‘0’. The internal clock signal CK.sub.I has the same frequency as the external clock signal CK.sub.E but there is an initial phase difference due to the delay of CK.sub.E through the clock tree buffers 328.

[0060] At time 802, after the system is reset, the reset signal changes to logic ‘0’. Initially delay is added to CK.sub.E through the VCDL and no delay is added through the DCDL. The rising edge of CK.sub.I occurs later than the rising edge of CK.sub.E due to the delay through the clock tree buffers 328 (FIG. 3) and the delay through the VCDL. The SW signal set to logic ‘0’ allows CK.sub.E to increment the code stored in the counter 308 (FIG. 3). As the code stored in the counter 308 (FIG. 3) is incremented by CK.sub.E (rising edge or falling edge), more delay elements 400 (FIG. 4) are added to the DCDL 306 (FIG. 3) to further delay CK.sub.E. The delay between CK.sub.E and CK.sub.I increases until the phase detection window is reached.

[0061] At time 904, the phase detector 320 (FIG. 3) detects that the phase detection window has been reached. The Ph_det signal output from the phase detector changes state from logic ‘1’ to logic ‘0’ indicating that the phase detector 320 has detected a rising edge of CK.sub.I signal after a falling edge of CK.sub.E. SR flip-flop 600 is set, and LC1 at the Q output is set to ‘1’. In successive clock periods, the phase difference between Ck.sub.E and Ck.sub.I decreases as the DCDL delay is increased.

[0062] At time 906, the phase detector 320 (FIG. 3) detects that the minimum DCDL delay has been added by the DCDL; that is the rising edge of CK.sub.I occurred after the rising edge of CK.sub.E. The Ph-det output of the phase detector 320 changes to logic ‘1’. LC2 at the output of AND gate 706 changes to logic ‘1’, the SR flip-flop 702 is set and the Q output (SW) changes to logic ‘1’. Further changes on the Ph-det signal do not affect the state of LC1 and SW. The SW signal set to ‘1’ disables further incrementing of the counter 308.

[0063] During normal DLL operation, the delay adjustment of the clock path to compensate for drifts and condition changes covers a narrow range of the wide delay range. Thus, after the lock has been reached, the DCDL provides the minimum delay. The DLL delay is varied by the VCDL inside a smaller delay range. Monitoring the smaller delay range during normal operation provides more stability and reduces the controlling voltage node sensitivity.

[0064] The invention has been described for an embodiment having a single fixed bias voltage level. In an alternate embodiment, more than one fixed bias voltage level can be used to provide a more compact DLL that is less noise sensitive. This allows the wide delay range to be modified in order to reduce the number of DCDL delay elements by selecting a fixed bias voltage level dependent on the frequency of the external clock. Reducing the number of DCDL delay elements, reduces sensitivity to noise. For example, in one embodiment, with a fixed bias voltage of 0.6V.sub.DD, fifteen DCDL delay elements are required to provide the DCDL delay. When the fixed bias voltage is 0.7V.sub.DD, only eight DCDL delay elements are required to provide the DCDL delay. However, changing the delay range may result in the delay range covering an unstable region, for example, at point C in the graph shown in FIG. 2.

[0065] The invention can be used in integrated circuits requiring high accuracy of input/output data synchronization, for example, in memory integrated circuits.

[0066] While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims. For example, while the delay of the DCDL remains fixed over short times, it may be allowed to occasionally shift as, for example, the VCDL approaches its delay limits.