LED display control circuit with PWM circuit for driving a plurality of LED channels

Abstract

The current disclosure provides an LED display control circuit. The control circuit has a device configured to separate a first PWM data into LSB data and MSB data. The control circuit also comprises a LSB circuit coupled to a plurality of LED channels. The LSB circuit is configured to supply LSB data to each of the plurality of LED channels.

Claims

1. An LED display control circuit, comprising: a device configured to separate a first PWM data into an LSB data and a MSB data; an LSB circuit coupled to a plurality of LED channels, wherein the LSB circuit comprises a LSB SRAM that stores the LSB data; a ROM coupled to the LSB SRAM, wherein the ROM stores a look up table; a LSB multiplexer coupled to the ROM for multiplexing the LSB data into each of the plurality of LED channels, a MSB multiplexer for multiplexing the MSB data to each of the plurality of LED channels, wherein each of the plurality of LED channels comprises a MSB SRAM for storing the MSB data received from the MSB multiplexer, a shift register for storing the LSB data received from the LSB multiplexer, and a latch coupled to the shift register, wherein the latch is configured to block or release the LSB data received from the LSB multiplexer.

2. The LED display control circuit of claim 1, wherein the LSB data stored in the shift register in each of the plurality of LED channels is released from the latch sequentially and the released LSB data combines the MSB data in the MSB SRAM to generate a second PWM data.

3. The LED display control circuit of claim 1, further comprising a pipeline register located between the SRAM and the ROM.

Description

DESCRIPTIONS OF DRAWINGS

(1) The teachings of the present disclosure can be readily understood by considering the following detailed description in conjunction with the accompanying drawings.

(2) FIG. 1 schematically illustrates PWM and S-PWM having 5 LSB bits.

(3) FIG. 2 schematically illustrates a timing diagram of a PWM signal according the current disclosure.

(4) FIG. 3 schematically illustrates a method of driving the LED display according to the current disclosure.

(5) FIG. 4 schematically illustrates a circuit according to the current disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENT

(6) The Figures (FIG.) and the following description relate to the embodiments of the present disclosure by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and/or methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of the claimed inventions.

(7) Reference will now be made in detail to several embodiments of the present disclosure(s), examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments of the present disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the disclosure described herein.

(8) FIG. 2 schematically illustrates a scan mechanism according to the current disclosure, in which each data frame is divided into 2.sup.BIT.sup._.sup.NUMBER.sup._.sup.OF.sup._.sup.LSB segments. In each segment a plurality of scan lines (16 scan lines in this case) are driven (or “scanned”) sequentially. There is a deadtime period (not shown in FIG. 2) between the completion of displaying of the line data of one scan and the start of the next scan line. According to the current disclosure, the scan line data for the next scan line is read and processed during the current scan period, e.g., data for Scan 1 is processed during Scan 0.

(9) FIG. 3 shows details in the scan sequence. In particular, it illustrates Scan 0 and Scan 1 in Segment 0 of the embodiment of FIG. 2. According to FIG. 3, each scam line is allocated 2048 GCLK cycles for display, i.e., GCLK0 to GCLK2047. A deadtime exists between adjacent scan lines, e.g., Scan 0 and Scan 1. Furthermore, when Scan Line 0 is being displayed, data for the next scan line, i.e., scan line 1, is processed. Note that in this case, data for Channel 0 (CH0) to Channel 47 (CH47)—a total of 48 channels—are processed in the first 48 GCLK cycles (GCLK0-GCLK47). The same process is repeated for the next scan line in the current segment and for all remaining scan lines. When the processing of all scan lines in the current segment is finished, the same process is repeated for the next segment, and sequentially for each of all the remaining segments in the frame. Once a frame has been displayed, the next frame follows. In this way, the frame data is displayed circularly and repeatedly.

(10) The number of channels can be any suitable number greater or less than 48 as long as the LSB circuit can finish processing the LSB data for all channels during the allocated time. In addition, when the LSB circuit also include pipeline registers, more GCLK cycles are required to process the LSB data for all channels.

(11) In the embodiment shown in FIG. 3, since the LSB data for the next scan line is processed and ready to be loaded while the current scan line is being displayed, only one LSB circuit is needed to process the LSB data for all channels.

(12) FIG. 4 is a block diagram for the circuit in accordance with one embodiment of the present disclosure. As shown in FIG. 4, the first PWM data is transmitted into a serial interface 411 and from there to a shift register 410. The shift register 410 divides the PWM data into the MSB data and the LSB data. The MSB data is transmitted into a memory in each channel while the LSB data is transmitted to a LSB circuit. In particular, the LSB circuit has SRAM 401 and ROM 402. The LSB data is initially stored in SRAM 401. During a display, the LSB data for the next scan line is read out from SRAM memory 401. The content of the SRAM memory 401 then goes through the ROM 402 and is translated into the LSB pulse locations according to the look up table in ROM 402 (i.e., the ROM table). The MUX 403 determines whether the LSB data needs to be counted based on the segment information. In this case, the LSB data for all the channels are processed and loaded into their corresponding shift registers, such as the DFF (D Flip-Flop) 452 in the channels 451. While the scan line is being displayed, the latches 453 are turned off so that the LSB data is blocked. At the start of the deadtime, an update signal is sent to the latch 453 in all channels 451 and turns the latch 453 on so that the LSB data for all channels 451 are updated. Therefore, both the LSB data and the MSB data from the MSB SRAM 455 input into the adders 456 to generate the second PWM data for the next scan. Accordingly, the data for the next scan, e.g., Scan 1, is ready during the deadtime between Scan 0 and Scan 1. In this embodiment, the LSB circuit is shared among all the channels. Because of this simplification of the circuit, the top chip area for the control circuit is smaller compared with the scenarios when each channel has its own designated LSB circuit.

(13) Note that the embodiment in FIG. 4, the each channel has its own designated storage for the MSB data—SRAM 455, whereby the MSB data, through the MSB MUX 412, is loaded into SRAM 455 for each channel. Alternatively, the MSB data for each channel may be stored on one memory and shared among all channels.

(14) In a further embodiment, pipeline registers 404 are implemented between the SRAM 401, the ROM 402, and the MUX 403 for faster clock cycle and higher throughput design.

(15) Many modifications and other embodiments of the disclosure will come to the mind of one skilled in the art having the benefit of the teaching presented in the forgoing descriptions and the associated drawings. For example, the LED array in the display may be arranged in a common cathode configuration, in which each of a plurality of common cathode nodes is connected with cathodes of the LEDs of a same color in a same row. The common cathode nodes are operably connected to power sources. Alternatively, the LED array may be arranged in a common anode configuration, in which each of a plurality of common anode nodes is connected with anodes of LEDs of a same color in the same column. The common anode nodes are operably connected to power sources. Details of common anode configuration have been disclosed in U.S. application Ser. No. 13/041,427, filed Mar. 6, 2011, incorporated herein by reference.

(16) Elements in the LED array can be single color LEDs or RGB units or any other forms of LEDs available. The control circuit can be scaled up or scaled down to drive LED arrays of various sizes. Multiple control circuits may be employed to drive a plurality of LED arrays in a LED display system. The components in the driver can either be integrated on a single chip or on more than one chip or on the PCB board. Such variations are within the scope of this disclosure. It is to be understood that the disclosure is not to be limited to the specific embodiments disclosed, and that the modifications and embodiments are intended to be included within the scope of the dependent claims.