Laminate substrates having radial cut metallic planes
09818682 · 2017-11-14
Assignee
Inventors
Cpc classification
Y10T29/4913
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
H05K2201/0191
ELECTRICITY
B32B5/16
PERFORMING OPERATIONS; TRANSPORTING
H05K1/0271
ELECTRICITY
Y10T428/24322
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
H01L2924/0002
ELECTRICITY
B32B37/02
PERFORMING OPERATIONS; TRANSPORTING
B32B27/04
PERFORMING OPERATIONS; TRANSPORTING
H01L21/4803
ELECTRICITY
B32B37/182
PERFORMING OPERATIONS; TRANSPORTING
Y10T428/24314
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
B32B3/08
PERFORMING OPERATIONS; TRANSPORTING
Y10T29/49126
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
B32B38/0004
PERFORMING OPERATIONS; TRANSPORTING
B32B3/266
PERFORMING OPERATIONS; TRANSPORTING
H01L2924/0002
ELECTRICITY
Y10T428/25
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y10T428/24331
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
B32B3/10
PERFORMING OPERATIONS; TRANSPORTING
H01L2924/00
ELECTRICITY
B32B15/20
PERFORMING OPERATIONS; TRANSPORTING
Y10T428/24298
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
H01L23/49833
ELECTRICITY
B32B2250/40
PERFORMING OPERATIONS; TRANSPORTING
H01L2924/00
ELECTRICITY
B32B27/20
PERFORMING OPERATIONS; TRANSPORTING
H01L23/49827
ELECTRICITY
International classification
B32B5/16
PERFORMING OPERATIONS; TRANSPORTING
B32B7/02
PERFORMING OPERATIONS; TRANSPORTING
B32B27/04
PERFORMING OPERATIONS; TRANSPORTING
H01L23/48
ELECTRICITY
B32B37/02
PERFORMING OPERATIONS; TRANSPORTING
H01L23/498
ELECTRICITY
B32B3/26
PERFORMING OPERATIONS; TRANSPORTING
B32B38/00
PERFORMING OPERATIONS; TRANSPORTING
Abstract
A laminate substrate for receiving a semiconductor chip. Included are laminate layers stacked to form the laminate substrate, each laminate layer includes a core that includes particle-filled epoxy and a metallic layer on the core. At least one laminate layer has a radial cut through the metallic layer, the radial cut extending from a periphery of the at least one laminate layer towards a center of the at least one laminate layer. The radial cut cuts only through the metallic layer and does not cut through the core.
Claims
1. A laminate substrate for receiving a semiconductor chip comprising: a plurality of laminate layers stacked to form the laminate substrate, each laminate layer comprising a core comprising particle-filled epoxy, a top metallic layer on top of the core and a bottom metallic layer underneath the core; a plurality of insulating layers devoid of metallic layers such that one insulating layer is placed between each pair of laminate layers and is in direct contact with the top metallic layer and the bottom metallic layer wherein each insulating layer has a thickness that is less than a thickness of the core of the plurality of laminate layers; wherein at least one laminate layer having a radial cut through at least one of the top metallic layer and the bottom metallic layer, the radial cut extending from a periphery of the at least one laminate layer towards a center of the at least one laminate layer, the radial cut cutting only through the at least one of the top metallic layer and the bottom metallic layer and not cutting through the core; and further comprising a central core layer comprising a central core comprising particle-filled epoxy and a first metallic layer on a first side of the central core and a second metallic layer on a second side of the central core, the central core being thicker than the core of each of the plurality of laminate layers wherein there are a plurality of laminate layers above the central core layer and a plurality of laminate layers below the central core layer, wherein there is placed one insulating layer devoid of metallic layers between the central core layer and one laminate layer above the central core layer and there is placed one insulating layer devoid of metallic layers between the central core layer and one laminate layer below the central core and wherein a top layer above the central core layer is for receiving the semiconductor chip.
2. The laminate substrate of claim 1 wherein the at least one laminate layer having at least two radial cuts.
3. The laminate substrate of claim 1 wherein the at least one laminate layer radial cut from the periphery towards the center of the at least one laminate layer is not continuous.
4. The laminate substrate of claim 1 wherein the at least one laminate layer radial cut from the periphery towards the center of the at least one laminate layer is continuous.
5. The laminate substrate of claim 1 wherein the at least one laminate layer radial cut from the periphery towards the center of the at least one laminate layer is not in a straight line.
6. The laminate substrate of claim 1 wherein a second laminate layer having a radial cut through at least one of the top metallic layer and the bottom metallic layer of the second laminate layer, the radial cut extending from a periphery of the second laminate layer towards a center of the second one laminate layer, the radial cut cutting only through the at least one of the top metallic layer and the bottom metallic layer of the second laminate layer and not cutting through the core of the second laminate layer such that the radial cut is devoid of the metallic material and the insulating material.
7. The laminate substrate of claim 6 wherein the radial cut of the first laminate layer is offset from the radial cut of the second laminate layer so that the radial cut of the first laminate layer is not directly in line with the radial cut of the second laminate layer wherein the radial cut of the first laminate layer and the radial cut of the second laminate layer are devoid of the metallic material and the insulating material.
8. A laminate substrate for receiving a semiconductor chip comprising: a plurality of laminate layers, each laminate layer comprising a core comprising particle -filled epoxy, a top metallic layer on top of the core and a bottom metallic layer underneath the core; a plurality of insulating layers devoid of metallic layers such that one insulating layer is placed between each pair of laminate layers and is in direct contact with the top metallic layer and the bottom metallic layer wherein each insulating layer has a thickness that is less than a thickness of the core of the plurality of laminate layers; a central core layer comprising a central core comprising particle-filled epoxy and a first metallic layer on a first side of the central core and a second metallic layer on a second side of the central core, the central core being thicker than the core of the plurality of laminate layers wherein there is placed one insulating layer devoid of metallic layers between the central core layer and one laminate layer above the central core layer and there is placed one insulating layer devoid of metallic layers between the central core layer and one laminate layer below the central core and; and wherein some of the plurality of laminate layers are top laminate layers, are positioned above the central core layer and the topmost of the top laminate layers is configured to receive a semiconductor chip and some of the plurality of laminate layers are bottom laminate layers and are positioned below the central core layer, such that the top laminate layers, central core layer and bottom laminate layers are stacked to form the laminate substrate; wherein at least one laminate layer of the top laminate layers and bottom laminate layers having a radial cut through at least one of the top metallic layer and the bottom metallic layer of the at least one laminate layer, the radial cut extending from a periphery of the at least one laminate layer towards a center of the at least one laminate layer, the radial cut cutting only through the at least one of the top metallic layer and the bottom metallic layer of the at least one laminate layer and not cutting through the core of the at least one laminate layer.
9. The laminate substrate of claim 8 wherein the at least one laminate layer having at least two radial cuts.
10. The laminate substrate of claim 8 wherein the at least one laminate layer radial cut from the periphery towards the center of the at least one laminate layer is not continuous.
11. The laminate substrate of claim 8 wherein the at least one laminate layer radial cut from the periphery towards the center of the at least one laminate layer is continuous.
12. The laminate substrate of claim 8 wherein the at least one laminate layer radial cut from the periphery towards the center of the at least one laminate layer is not in a straight line.
13. The laminate substrate of claim 8 wherein a second laminate layer of the top laminate layers and bottom laminate layers having a radial cut through the at least one of the top metallic layer and the bottom metallic layer of the second laminate layer, the radial cut of the second laminate layer extending from a periphery of the second laminate layer towards a center of the second laminate layer , the radial cut of the second laminate layer cutting only through the at least one of the top metallic layer and the bottom metallic layer of the second laminate layer and not cutting through the core of the second laminate layer such that the radial cut of the second laminate layer is devoid of the metallic material and the insulating material.
14. The laminate substrate of claim 13 wherein the radial cut of the first laminate layer is offset from the radial cut of the second laminate layer so that the radial cut of the first laminate layer is not directly in line with the radial cut of the second laminate layer wherein the radial cut of the first laminate layer and the radial cut of the second laminate layer are devoid of the metallic material and the insulating material.
15. The laminate substrate of claim 13 wherein the first laminate layer and the second laminate layer are selected from the bottom laminate layers.
16. The laminate substrate of claim 13 wherein the first laminate layer and the second laminate layer are selected from the top laminate layers.
17. The laminate substrate of claim 13 wherein the first laminate layer is selected from the top laminate layers and the second laminate layer is selected from the bottom laminate layers.
18. A method of forming a laminate substrate for receiving a semiconductor chip comprising: forming a central core layer comprising a central core comprising particle-filled epoxy and a first metallic layer on a top side of the central core and a second metallic layer on a bottom side of the central core; placing a top insulating layer devoid of metallic layers directly on the top side of the central core layer; placing a bottom insulating layer devoid of metallic layers directly underneath the bottom side of the central core layer; forming a top laminate layer directly on the top insulating layer and forming a bottom laminate layer directly on the bottom insulating layer , each laminate layer comprising a core comprising particle-filled epoxy, a top metallic layer on top of the core and a bottom metallic layer underneath the core; forming additional insulating and laminate layers on previous laminate layers to form additional bottom insulating layers and bottom laminate layers and top insulating layers and top laminate layers until a required number of top insulating layer layers and top laminate layers and bottom insulating layers and bottom laminate layers have been formed; wherein the central core being thicker than the core of each of the top and bottom laminate layers; wherein each insulating layer has a thickness that is less than a thickness of the core of the laminate layers; and wherein at least one laminate layer of the top and bottom laminate layers being formed with a radial cut through at least one of the top metallic layer and the bottom metallic layer of the at least one laminate layer, the radial cut extending from a periphery of the at least one laminate layer towards a center of the at least one laminate layer, the radial cut cutting only through the at least one of the top metallic layer and the bottom metallic layer of the at least one laminate layer and not cutting through the core of the at least one laminate layer.
19. The method of claim 18 wherein a second laminate layer having a radial cut through the metallic layer of the second laminate layer, the radial cut extending from a periphery of the second laminate layer towards a center of the second laminate layer, the radial cut cutting only through the at least one of the top metallic layer of the second laminate layer and the bottom metallic layer and not cutting through the core of the second laminate layer such that the radial cut is devoid of the metallic material and the insulating material wherein the radial cut of the first laminate layer is offset from the radial cut of the second laminate layer so that the radial cut of the first laminate layer is not directly in line with the radial cut of the second laminate layer and wherein the radial cut of the first laminate layer and the radial cut of the second laminate layer are devoid of the metallic material and the insulating material.
Description
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
(1) The features of the exemplary embodiments believed to be novel and the elements characteristic of the exemplary embodiments are set forth with particularity in the appended claims. The Figures are for illustration purposes only and are not drawn to scale. The exemplary embodiments, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which:
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DETAILED DESCRIPTION
(12) In an organic laminate substrate, copper wiring planes are the element with the highest Young's modulus, which is 5 to 20 times that of other substrate elements at room temperature. At solder reflow temperature, due to the softening of organic laminate components, this ratio increases to a factor of several hundred. Due to the high stiffness of copper wiring planes, copper wiring planes have a dominant effect in generating and reacting to stresses from thermal expansion. Another element of the composite with high stiffness is the core reenforcing glass epoxy, if used.
(13) Since copper density is low in the top center of the substrate and higher in the periphery and bottom, and since non-copper elements such as epoxy dielectric and glass fibers have mechanical properties differing significantly from those of copper, heating and cooling generates radial stresses, either tensile or compressive depending on the materials used, radiating from the die center. If the peripheral copper planes are continuous, stiff peripheral copper resists expansion and contraction through circumferential hoop stresses absorbed by the stiff material. By radially cutting this peripheral copper, the organic laminate substrate is rendered unable to resist expansion and contraction and so hoop stresses may be relieved. Further, since the hoop stresses drive out-of-plane warpage, relieving hoop stresses may also reduce out-of-plane warpage.
(14) Referring to the drawings in more detail, and particularly referring to
(15) Referring to
(16) According to the invention, the present inventors have proposed that at least one of the laminate layers in the organic substrate laminate has a radial “cut” through one or both of the copper planes. By “cut”, it is meant that the copper plane has a discontinuity so that the periphery of the copper plane is not stiff and hoop stresses may be relieved. The copper plane may not actually be “cut” by an instrumentality such as a saw but during the patterning of the copper plane, the copper plane may be patterned so that no copper is present in certain areas of the copper plane which appear as if cut by a saw or some such instrument.
(17) The radial cut extends from a periphery of the copper plane towards a center of the at least one laminate layer. The radial cut may further continue from a point near or at the center of the at least one laminate layer to an opposite side of the periphery of the copper plane. It should be understood that while the copper planes may extend to the periphery of the organic core of the laminate layer, as shown in
(18) Referring to
(19) Referring now to
(20) In
(21)
(22)
(23) Laminate layer 12G is the top layer of the organic laminate substrate and may or may not have any radial cuts. As presently shown, laminate layer 12G has no radial cuts. The laminate layer 12G may have a semiconductor device joining area 50 for joining a semiconductor device (not shown) such as a semiconductor chip.
(24) It should be understood that while
(25) Referring now to
(26) Referring to
(27) Referring now to
(28) Referring to
(29) Moreover, it may be that some or all of the laminate layers 12A to 12C below the core laminate layer 22 may have radial cuts while some or all of the laminate layers 12D to 12F, as well as the top laminate layer 12G, above the core laminate layer 22 may have no radial cuts which may be especially useful to reduce an anticipated concave shape of the organic laminate substrate. Alternatively, it may be that some or all of the laminate layers 12A to 12C below the core laminate layer 22 may have no radial cuts while some or all of the laminate layers 12D to 12F, as well as the top laminate layer 12G, above the core laminate layer 22 may have radial cuts which may be especially useful to reduce an anticipated convex shape of the organic laminate substrate.
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(31) In general, the number of laminate layers having radial cuts may be increased to increase the effectiveness of the exemplary embodiments. Spacing the radial cuts closely together in adjacent layers may also increase the effectiveness of the exemplary embodiments.
(32) Referring now to
(33)
(34) Referring now to
(35) It will be apparent to those skilled in the art having regard to this disclosure that other modifications of the exemplary embodiments beyond those embodiments specifically described here may be made without departing from the spirit of the invention. Accordingly, such modifications are considered within the scope of the invention as limited solely by the appended claims.