System for balancing a series of cells

Abstract

System for balancing series of cells, including circuits each having three or four cells, including: one or two central cells and additional neighboring cells in each circuit, each neighboring cell being adjacent to one central cells; a local capacitor for each neighboring cell, within a local section of each circuit; one global capacitor at a global section which is common to all the circuits; a plurality of controlled switches; a controller which periodically, repeatedly, and alternately opens and closes some switches to: within each circuit, connect each local capacitor in parallel to a respective neighboring cell; within each circuit, connect each local capacitor in parallel to the central cell if one central cell exists, or to another central cell if two central cells exist, respectively; within each circuit, connect said central cells of all circuits separately or simultaneously to said global capacitor.

Claims

1. A hierarchical-hybrid system for balancing a series of cells, said system being divided into a plurality of m modules, each module having k cells, the system comprising: one or two central cells and additional neighboring cells in each module, each neighboring cell being adjacent to one of said central cells; a local capacitor for each neighboring cell, within a local section of each module; one global capacitor at a global section which is common to all said modules; a plurality of controlled switches; a controller configured to periodically, repeatedly, and alternately open and close certain switches from said controlled switches to: (a) within each module, connect each local capacitor in parallel to a respective one of said neighboring cells; (b) within each module, connect each said local capacitors in parallel to the central cell provided that one central cell exists, or connect each local capacitor to another central cell provided that two central cells exist, respectively; and (c) within the system, connect all said central cells of all modules separately or simultaneously to said global capacitor; wherein each module further comprises connecting circuitry which in turn comprises one or more isolation elements that connects said local section of the module to said global section which is common to all the modules.

2. The system of claim 1, wherein said controller is configured to alternate the states of said controlled switches at a high-frequency rate.

3. The system of claim 1, wherein said isolation element is a transformer comprising primary and secondary sides, while said global capacitor is located at the secondary side.

4. The system of claim 3, further comprising a serial inductance at each of said primary sides of the transformer.

5. The system of claim 4, wherein said serial inductance in the primary side of the transformer is formed either by a leakage inductance of the primary coil of the transformer or by an additional inductor in series to the primary of the transformer.

6. The system of claim 4, further comprising an additional serial capacitor, wherein said additional serial capacitor and said serial inductor are configured to form a serial resonant-type circuitry.

7. A method for balancing a series of cells, the method comprising: dividing the series of cells into a plurality of m modules, each module comprising one or two central cells, and additional neighboring cells, each neighboring cell being adjacent to one of said central cells; providing a local capacitor for each neighboring cell, within a local section of each module; providing connecting circuitry in each module which in turn comprises one or more isolation elements that connect said local section of the module to said global section which is common to all the modules, and further providing within the global section a global capacitor; providing a plurality of controlled switches; periodically, repeatedly, and alternately opening and closing each time certain switches from said controlled switches to: (a) connect each local capacitor in parallel to a respective one of said neighboring cells; (b) within each module, connect each said local capacitors in parallel to the central cell provided that one central cell exists, or connect each local capacitor to another central cell, respectively, provided that two central cells exist; and (c) connect said central cells of all the modules separately or simultaneously to said global capacitor.

8. The method of claim 7, wherein the period of opening and closing is divided into two intervals: t.sub.1=t.sub.on1+t.sub.off1 and t.sub.2=t.sub.on2+t.sub.off2, wherein: during t.sub.on1 each neighboring cell is balanced against a local capacitor, tone respectively, and the one or more central cells are balanced against the global capacitor; during t.sub.off1 a flow of current is zeroed; during t.sub.on2 both local capacitors are balanced against the one or more central cells, and the one or more central cells are again balanced against the global capacitor; and during t.sub.off2 the flow of current is again zeroed.

9. The method of claim 7, wherein during operation said local capacitors within each circuit serially balance the cells in the circuit, and said global capacitor parallelly balance the central cells of all the circuits.

10. The method of claim 7, wherein during operation said local capacitors within each circuit parallelly balance respective cells of the circuit, and said global capacitor serially balances the central cells of all the circuits.

11. The method of claim 7, wherein during operation charge quantities that are proportional to a difference between a voltage of a respective central cell of the circuit and between a voltage of said global capacitor are transferred by means of said connecting circuitry.

12. The method of claim 7, further comprising periodically altering the states of the controlled switches in a cyclical frequency rate, while at each said frequency cycle a charge quantity is transferred from cells or capacitors of higher voltage to cells or capacitors of lower voltage, respectively.

13. The method of claim 7, further comprising: providing an additional serial capacitor at a primary side of the isolation element which together with an additional inductance at the primary side forms a serial resonant-type circuitry; and setting the period of opening and closing of the switches to result in a resonance operation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention is illustrated by way of example in the accompanying drawings, in which similar references consistently indicate similar elements and in which:

(2) FIGS. 1(a) to 1(c) illustrate some prior art balancing structures;

(3) FIG. 2 illustrates an embodiment of the present invention;

(4) FIG. 3 illustrates an additional embodiment of the present invention, having a half-bridge rectification at the primary side;

(5) FIGS. 4(a)-4(d) illustrate various states of the balancing process of the embodiment of FIG. 2;

(6) FIGS. 5(a)-5(d) are simplified circuits of the states shown in FIGS. 4(a)-4(d);

(7) FIG. 6 shows a typical waveform of the parallel balancer current for a case that V.sub.cell>V.sub.bus in the embodiment of FIG. 2;

(8) FIG. 7 shows the convergence of the balancing process as obtained in a simulation;

(9) FIGS. 8(a)-8(d) show the voltage equalization mechanism for the balancing system of FIG. 3;

(10) FIG. 9 shows a structure of the invention having a parallel balancing with a serial link;

(11) FIGS. 10(a)-10(d) show the voltage equalization mechanism for the balancing system of FIG. 9;

(12) FIGS. 11(a)-11(d) are simplified circuits of the states shown in FIGS. 10(a)-10(d);

(13) FIG. 12 shows the balancing current for the parallel balancing circuit for one switching period;

(14) FIG. 13 shows convergence results of the balancing structure as obtained in a simulation;

(15) FIG. 14 shows a hardware prototype as used in a simulation;

(16) FIG. 15 shows still another embodiment of the invention which operates without an isolation transformer;

(17) FIG. 16 shows various operational states of the embodiment of FIG. 15;

(18) FIG. 17 shows the current I.sub.L (top) and voltage (bottom) waveforms for the case that V.sub.cell,1>V.sub.bus in the embodiment of FIG. 16;

(19) FIG. 18 depicts the convergence of four cells (emulated by large capacitances), as obtained in a simulation for the embodiment of FIG. 17;

(20) FIG. 19 two MOSFETs connected back-to-back, that construct the switches of the embodiment of FIG. 15;

(21) FIG. 20 shows an example of an implementation of a bidirectional switch and an independent gate driver per transistor using a conventional bootstrapped driver, that can be used in the embodiment of FIG. 15;

(22) FIG. 21 presents a steady-state operation current-waveforms in L.sub.1 and L.sub.2 for unbalanced cells, in the embodiment of FIG. 15; and

(23) FIG. 22 shows a convergence of the cells' voltages in the embodiment of FIG. 15, when cell no. 1 is connected to a 12V DC power supply.

DETAILED DESCRIPTION OF THE INVENTION

(24) Three typical active balancing schemes are shown in FIGS. 1(a) to 1(c).

(25) A switched-capacitor balancing scheme is generally shown in FIG. 1 (a). This scheme is relatively simple in structure and control, however, it is characterized by a long convergence time due to a sequential balancing, particularly when there is a necessity for a charge transfer through many battery cells.

(26) A multi-winding transformer scheme is generally shown in FIG. 1(b). This scheme enables a short convergence time and simple control, but is expensive and not modular.

(27) FIG. 1 (c) generally shows a parallel scheme which utilizes a plurality of DC-DC converters, one for each cell. Here, a fast convergence and modularity are obtained, however, this scheme involves a high magnetic component count, and the control over the components of the system is quite complex.

(28) A hierarchical-type structure is also commonly known. As previously noted, the hierarchical structure combines a serial scheme with a parallel scheme. This prior art scheme, however, suffers from a high component count, among others, due to the use of two separate sets of switches, one for the serial scheme, and another one for the parallel scheme. In more general terms, the hierarchical structures of the prior art typically apply multiple and separate converters: a set of converters carries out a series balancing, whereas a different decoupled set of converters establishes a parallel connecting link.

(29) The prior art scheme suffers from still another drawback—as current flows within this scheme even during a fully balanced state. As will be discussed, the present invention overcomes these two drawbacks.

(30) The present invention relates to hybrid structures for active balancing of a serially connected string of batteries. The structures of the present invention feature simple sensor-less implementation, modularity, design flexibility and reduced component count. A major point of the balancing concept of the invention is that by merging two active balancing approaches (in a manner as will be explained herein), additional power paths between battery cells are created, but without the penalty of extra conversion stages. Furthermore, the balancing system operates in DCM (Discontinuous Current Mode)—the inductor current starts at zero and returns to zero, for every switching period and energy is transferred according to voltage difference between the cells. Therefore, no energy circulates in the system when the cells are balanced, resulting in expedited convergence and low power losses.

(31) The necessity of multiple energy paths for the action of balancing dc sources stems primarily from the tradeoff between the complexity of the system and the convergence characteristics (e.g., losses, duration etc.). The use of a hybrid-type balancing structure enables the flexibility in modular operation without extra conversion stages. This advantage becomes further apparent for cases that long strings are considered.

(32) The hybrid-balancing of the present invention is implemented by a serial balancing with a parallel link and by a setup that serially links parallel modules. The present invention utilizes the link between modules without interference of the primary power flow and minimal hardware additions. In the present invention, each string consists of n cells and balanced using m modules where each module is in charge of balancing k cells, hence n=mk.

(33) According to a first aspect of the present invention (series balancing with a parallel link), the balancing of the serially connected battery string is performed by serially balancing the battery cells within each module and connecting at least one of the battery cells in the module in a parallel manner to an energy buffer, e.g., a capacitor (hereinafter, “global capacitor”). The global capacitor is in balancing contact with one or two central battery cells in each of the modules. Thus, the cell voltages within each module are each affected by their adjacent cell voltage, by either receiving extra energy (charge/voltage) from an adjacent cell having a higher voltage, or contributing/transferring energy (charge/voltage) to an adjacent cell having a lower voltage. The central cell within each module that is in balancing contact with the energy buffer capacitor (namely, the global capacitor) either affects the voltage of the global capacitor by transferring charge thereto (in case its voltage is higher than that of the global capacitor) or is affected by the voltage of the global capacitor by receiving charge therefrom (in case its voltage is lower than that of the global capacitor). Eventually, each of the central battery cells within each of the modules, respectively, becomes balanced due to its interaction with the global capacitor, while the rest of the adjacent cells are balanced relative to the respective central battery cell—thus after some merging period, the entire string becomes fully balanced.

(34) The system structure shown in FIG. 2, shows equalization of the voltage of all the cells to their average value using a serial Differential Power Processor (DPP) and a common bus energy buffer, e.g. capacitor, for the parallel power flow. The parallel balancing is facilitated by utilizing conduction paths of a neighboring module to link with the global capacitor C.sub.bus. Thus, the energy buffer capacitor C.sub.bus is connected in parallel with each of the modules. An additional significant advantage of the present invention topology is that the quiescent power loss is minimal since no energy circulates in the system when the batteries are balanced.

(35) The balancing system depicted in FIG. 2 enables adding of a parallel power path to an already existing serial balancing structure, which is in turn uses two “local” capacitors C.sub.sw and respective switches that are timely activated to balance the voltage between each adjacent cell and its neighboring central cell. As can be realized, the string is in fact balanced using a serial DPP that uses a switched capacitor converter (SCC). The parallel link is facilitated by connecting the primary side of a transformer to the switching nodes of a SCC module via an inductor (can be replaced by the transformer's leakage inductance), whereas the secondary side of the transformer connects to a global capacitor through a bridge rectifier. In such a manner, the global capacitor links to other modules and additional energy paths are formed that potentially expedite the balancing speed and reduce the amount of conversions to equalize distant cells. It should be noted that the primary side of the parallel link can be realized in a variety of ways, for example as a full-bridge assembly as shown in FIG. 2, or in case that the DPPs are synchronized, a half-bridge configuration is sufficient as depicted, for example, in FIG. 3.

(36) The principle of operation is now described for the system of FIG. 2. The switching frequency is set the same for the switches at the primary side of the transformer and for those at the secondary side (those at the secondary side are used solely in the parallel link). As will be shown, the switches at the primary side of each module are common to both the serial link within this module and to the parallel link, therefore in that sense the system in fact becomes “hybrid”. The switches at the primary side of the transformer, as well to those at the secondary side all receive control from a same control unit (not shown). To avoid a scenario that the inductor of a parallel link (namely, the inductor at the primary of the transformer) connects to a cell with a nonzero current, the operation of these modules is set to DCM (Discontinuous Current Mode)—the inductor current starts at zero and returns to zero, for each switching period. This further simplifies the circuitry for a bidirectional operation, as the circuit does not use sensors, while it can use smaller magnetic elements.

(37) For reasons of symmetry, the parallel circuits have been assigned to the middle (central) cells of each module. The global (bus) capacitor C.sub.bus holds the average voltage of the pack V.sub.bus, which is a common voltage for all modules. Assuming that a one parallel link is used every k=3 cells, V.sub.bus can be expressed as:

(38) $\begin{array}{cc}{V}_{\mathrm{bus}}=\frac{1}{m}\underset{k=1}{\overset{m}{.Math.}}{V}_{\mathrm{cell},3k-1}& \left(1\right)\end{array}$

(39) It should be noted that since isolation is used and each of the secondary circuits has an independent rectifier, the balancing action per cell is independent of the other cells in the string. This means that no synchronization between modules is required. The SCC can be activated in several operation modes, namely complete-charge, partial-charge or no-charge. The operation of the SCC as DPP forces voltage equalization between adjacent cells, as described in depth in the following references: US 2015/0214887; A. Blumenfeld, A. Cervera and M. M. Peretz, “Enhanced differential power processor for PV systems: Resonant switched-capacitor gyrator converter with local MPPT,” in Proc. IEEE Appl. Power Electron. Conf. Expo., pp. 2972-2979, March 2014; S. Ben-Yaakov, A. Blumenfeld, A. Cervera and M. Evzelman, “Design and evaluation of a modular resonant switched capacitors equalizer for PV panels,” in 2012 IEEE Energy Conversion Congress and Exposition, 2012, pp. 4129-4136; C. Pascual and P. T. Krein, “Switched capacitor system for automatic battery equalization,” U.S. Pat. No. 5,710,504, Jan. 20, 1998.

(40) The balancing operation of one module within an entire string of cells, each module comprising 3 battery cells, is described in the sub-circuits of FIGS. 4(a)-4(d), and in the simplified circuits of FIGS. 5A-5D respectively. To distinguish the contribution of the series and parallel balancers, the current flow per mode and direction are highlighted in FIGS. 4A-4D for each time interval respectively, for a case that:
V.sub.cell,2>V.sub.bus, V.sub.cell,1>V.sub.Cell,2>V.sub.cell,3

(41) As noted, each module comprises three cells Cell,1, Cell,2 and Cell,3, that are connected in series and having a voltage of V.sub.cell,1, V.sub.cell,2 and V.sub.cell,3, (respectively). During the serial operation (and locally within each module), Cell,1 is balanced against Cell,2, and Cell,3 is also balanced against Cell,2. More specifically, Cell,1 is balanced against Cell,2 by first connecting C.sub.sw1 in parallel to Cell,1, and in the next period C.sub.sw1 is connected in parallel to Cell,2. A similar procedure is performed with respect to the balancing of Cell,3 against Cell,2.

(42) The current i.sub.sw represents the current that is processed by the series path (i.sub.sw1 via the capacitor C.sub.sw1 and i.sub.sw2 via the capacitor C.sub.sw2). The inductor current i.sub.L indicates the current that flows through the primary side of the parallel link (transformer). The switching period is divided into two equal intervals: t.sub.1=t.sub.on1+t.sub.off1 and t.sub.2=t.sub.on2+t.sub.off2. In the first half-cycle t.sub.1, the switches S.sub.1, S.sub.3, S.sub.6, S.sub.8, S.sub.9 and S.sub.12 are turned on for t.sub.on1 (shown in FIG. 4a), allowing the current to flow in both directions. During this interval, the current flows from cell,1 to C.sub.sw1, from C.sub.sw2 to cell,3 and from cell,2 to the bus capacitor C.sub.bus. Simplified equivalent circuits for the operation of the parallel link and the SCC are depicted in FIG. 5(a) to FIG. 5(d), respectively—all assume for the sake of simplicity use of a 1:1 ratio between the primary and secondary of the transformer (although use of this ration is not a necessity). In the following time interval, t.sub.off1. (shown in FIG. 4b), the switches are turned off, i.sub.sw1 and i.sub.sw2 are zero and i.sub.L flows through the body diodes of S.sub.4, S.sub.5, S.sub.9 and S.sub.12 until the current becomes zero, and the current remains zero until the next switching period.

(43) In the second half-cycle, t.sub.2, switches S.sub.2, S.sub.4, S.sub.5, S.sub.7, S.sub.10 and S.sub.11 are turned on for tone (shown in FIG. 4c) so that cell,1 and cell,3 are idle and cell,2 is balanced. Throughout this interval current flows from C.sub.sw1 to cell,2, and from cell,2 to C.sub.sw2 and to the bus capacitor C.sub.bus (via the transformer). FIGS. 5c and 5d show the equivalent circuits during this interval. In the next time interval, t.sub.off2 (shown in FIG. 4d), the switches are turned off, i.sub.sw1 and i.sub.sw2 are zero and i.sub.L flows through the body diodes of S.sub.3, S.sub.6, S.sub.10 and S.sub.11 until the current becomes zero—this current remains zero until the next switching period. The serial-balancing current depends on the voltage difference between nearby cells, whereas for the parallel link it depends on the voltage difference between the respective central cell and the voltage V.sub.bus of the global capacitor C.sub.bus. The resulting current for the primary side of the parallel link (transformer) can be expressed as:

(44) $\begin{array}{cc}{i}_L=\frac{\Delta V_{\mathrm{int}}}{L}t& \left(2\right)\end{array}$
where the index int={on1, off1, on2, off2} refers to the time interval of operation, and ΔV.sub.int refers to the applied voltage on the inductance of the parallel link, reflected to the primary side.

(45) The voltage V.sub.bus over the global capacitor C.sub.bus is affected by all of the central battery cells of all the modules. Thus all of the modules affect V.sub.bus and V.sub.bus affects all modules, whereas the current direction is always from either the respective central cell to C.sub.bus or vice versa (always from the component having a higher voltage level to the one having a lower voltage level). This procedure repeats in a high rate (for example, 200 kHz) such that a small amount of charge passes during each period to the respective direction. Eventually, V.sub.bus converges to the average voltage of all of the serially connected cells and vice versa, all the serially connected cells converge to this average voltage.

(46) FIG. 6 shows a typical waveform of the parallel balancer current for a case that V.sub.cell>V.sub.bus. As implied from formula (2) and can be observed from FIG. 6, the current slope during the on times is a function of the voltage difference between the cell and the bus. However, at the off intervals it is proportional to the sum of voltages and is much steeper than the one of the on time. This means that its effect on the total charge per cycle is small and, can be neglected for the design of the circuit.

(47) As shown, the signal which is supplied to the primary of the transformer is created by the closure and opening of the same switches that are used in the serial balancing process. More specifically, the system of the present invention (as for example in FIG. 2) utilizes a same set of controlled switches for these two, serial and parallel balancing processes. Therefore, the number of controlled switches is significantly reduced in the hybrid-hierarchical system of the invention relative to the conventional hierarchical structure.

(48) FIG. 7 shows the convergence of the balancing process as obtained in a simulation. A pack of six batteries (emulated by large capacitances) has been preset to different voltages. By the balancing action, their voltages converge to the average value of the pack within about 30 mS, validating the operation of the system.

(49) FIG. 3 shows an additional possibility (Aspect 1—resonant configuration) for facilitating the parallel link. In this case a resonant-type, half bridge configuration is used. The current that flows through the primary of the transformer is resonant and therefore ZCS—Zero Current Switching is obtained. In this system the global capacitor Cbus holds half of the average voltage of the middle cells, and can be expressed as:

(50) $\begin{array}{cc}{V}_{\mathrm{bus}}=\frac{1}{2m}\underset{k=0}{\overset{m-1}{.Math.}}{V}_{\mathrm{cell},3k+2}& \left(3\right)\end{array}$

(51) The switching cycle, T.sub.s, is set longer than the resonant period and is divided into two equal intervals,
t.sub.1=t.sub.on1+t.sub.off1; and
t.sub.2=t.sub.on2+t.sub.off2,
where t.sub.on1=t.sub.on2=π√{square root over (L.sub.r/C.sub.r)}

(52) In the first half-cycle t.sub.1, the switches S.sub.1, S.sub.3, S.sub.5, S.sub.7, and are turned on for ton1, allowing the current to flow in both directions. During this interval (and for the case that: V.sub.cell,2>2V.sub.bus, V.sub.cell,1>V.sub.cell,2>V.sub.cell,3), the current flows from V.sub.cell,1 to C.sub.sw1, from V.sub.cell,2 to C.sub.sw2 and to the global capacitor C.sub.bus. In the following time interval, t.sub.off1, the switches are turned off, and no current circulates in the system. Simplified equivalent circuits for the operation of the parallel link (assuming a 1:1 ration in the transformer, although use of this ratio is not a necessity) and the SCC are depicted in FIGS. 8a and 8b, respectively.

(53) In the second half-cycle, t.sub.2, switches S.sub.2, S.sub.4, S.sub.6, S.sub.8, and S.sub.9, are turned on for tone so that current flows from C.sub.sw1 to V.sub.cell,2, from C.sub.sw2 to V.sub.cell,3 and a resonant current discharges the resonant capacitor C.sub.r. In the next time interval, t.sub.off2, the switches are turned off and the current is zero. The current remains zero until the next switching cycle. FIGS. 8c and 8d show the equivalent circuits during this interval. FIGS. 8(a)-8(d) show the voltage equalization mechanism for the balancing system of FIG. 3, for the case where Vcell >Vbus and Vcell,i>Vcell,i+1. FIG. 8(a) shows the central battery cell and the global capacitor C.sub.bus during t1; (b) a battery cell i and local (switched) capacitor C.sub.SW during t1 (the same circuit is applicable with respect to the two local capacitor and respective battery cells); (c) the central battery cell and the global capacitor during t2, (d) the battery cell i+1 and the respective switched capacitor case during t2 (again, this is applicable with respect to the two local capacitors C.sub.sw and respective battery cells i+1).

(54) According to still another aspect (aspect 2—parallel balancing with a serial link) of the present invention (shown in FIG. 9), the balancing core consists of parallel balancing for the primary energy flow and SCCs that serially link between them. This creates an additional path for the energy to flow between adjacent cells. The balancing system is divided into m modules, each comprises k=4 cells. The two inner (central) cells are connected to a parallel balancing circuit whereas the upper and lower cells use the serial link to equate their voltages with the central cells. This way, the primary energy flow of the string as well as the differential energy paths are intact.

(55) Among the variety of options to realize a parallel balancing circuit, the present invention employs a resonant converter approach recently presented in I. Zeltser, O. Kirshenboim, N. Dahan, and M. M. Peretz, “ZCS resonant converter based parallel balancing of serially connected batteries string,” in Proc. IEEE Appl. Power Electron. Conf. Expo., pp. 802-809, March 2016, and demonstrated benefits of ZCS, no quiescent power loss, relatively low component count and very simple control without synchronization between modules. The parallel balancer is constructed of two cells cell,2 and cell,3, each of them is connected to a half bridge transistor assembly that connects to the primary side of the transformer via a series resonant network. The secondary side connects to the bus capacitor via a full bridge transistor assembly. In a similar manner to the configuration of FIG. 2, the global capacitor, and therefore its voltage is common for all modules and can be expressed as:

(56) $\begin{array}{cc}{V}_{\mathrm{bus}}=\frac{1}{4m}\underset{k=0}{\overset{m-1}{.Math.}}\left(V_{\mathrm{cell},4k+2}+V_{\mathrm{cell},4k+3}\right)& \left(4\right)\end{array}$
The switching frequency f.sub.s is set lower than the resonant frequency f.sub.r (i.e. f.sub.s<f.sub.r) to allow operation in DCM. By doing so, ZCS is obtained for the parallel balancing circuit. The balancing time is shared equally between the top cells and bottom ones, that is V.sub.cell,1 and V.sub.cell,2 are balanced for some period of time (several switching cycles, and then V.sub.cell,3 and V.sub.cell,4 are balanced for the same period of time in next cycles. The details of the balancing operation for one switching cycle are provided using the sub-circuits in FIGS. 9a-9d and assisted by the corresponding simplified circuits illustrated in FIGS. 10a-10d.

(57) FIGS. 10a-10d relate to the system having 4 battery cells in each module, and for the case: V.sub.bus<0.5V.sub.cell,2; 0.5V.sub.cell,3<V.sub.bus; and V.sub.cell,1>V.sub.cell,2>V.sub.cell,3>V.sub.cell, 4.

(58) The currents flow are highlighted in FIGS. 10a-10d. i.sub.sw represents the current that flows in the series path (i.sub.sw1 via the capacitor C.sub.sw1 and i.sub.sw2 via the capacitor C.sub.sw2). The resonant current i.sub.L indicates the current that flows through the primary side of the transformer.

(59) The switching cycle is divided into four intervals, t.sub.1 and t.sub.2, for the top cells (described in FIG. 10(a) and FIG. 10(b)), and t.sub.3,t.sub.4 (described in FIG. 10(c) and FIG. 10(d)) for the bottom cells of each module.

(60) In the first interval t.sub.1 (see FIG. 10a), switches S.sub.1, S.sub.3, S.sub.9, and S.sub.12 are turned on, allowing bi-directional current flow. During this interval, (a) current flows from V.sub.cell,1 to C.sub.sw1 to charge C.sub.sw1 to the voltage of V.sub.cell,1. Simultaneously, the global (bus) capacitor C.sub.bus is charged by a balancing signal which is proportional to V.sub.cell,2, and C.sub.bus is also charged in parallel by respective signals that are created in all the other modules (these signals charge or discharge C.sub.bus, depending on where is the higher voltage among the two cells/capacitor involved).

(61) In the second interval t.sub.2 (see FIG. 9b), switches S.sub.2, S.sub.4, S.sub.5, S.sub.10, and S.sub.11 are turned on, again allowing a bi-directional current flow. During t.sub.2 V.sub.cell,2 is connected in parallel to C.sub.SW,1, therefore it is now balanced against the voltage of Cell,1 (as the voltage level over C.sub.SW,1 reflects the voltage level as previously taken from Cell,1). In the third interval t.sub.3 (see FIG. 9c), S.sub.4, S.sub.6, S.sub.8, S.sub.9, and S.sub.12 are turned on such that: capacitor C.sub.SW2 is in parallel to cell,4 such that it is charged to the voltage level of Cell,4, while simultaneously the bottom-central cell Cell,3 is balanced against capacitor C.sub.bus. In the fourth interval t.sub.4 S.sub.4, S.sub.5, S.sub.7, S.sub.10, and S.sub.11 are closed, therefore Cell,3 becomes parallel with C.sub.SW2, therefore Cell,3 is in fact balanced against Cell,4 (as the voltage level of C.sub.SW2 was previously equated to the voltage level of Cell,4).

(62) FIGS. 11(a)-11(d) illustrate the Voltage equalizing mechanism for the case V.sub.cell>V.sub.bus and V.sub.cell,i>V.sub.cell,i: (a) battery cell and the bus capacitor during t.sub.1, (b) battery cell and switched (global) capacitor case during t.sub.1, (c) battery cell and the bus (global) capacitor during t.sub.2, (d) battery cell and switched (local) capacitor case during t.sub.2.

(63) The balancing current for the parallel circuit for one switching period is depicted in FIG. 12. It is a function of the voltage difference between the cell and the bus capacitor, and can be expressed as:

(64) $\begin{array}{cc}{i}_L\left(t\right)=\frac{\Delta V}{\left(i-e^{-\frac{\pi }{4Q}}\right)Z_r}{e}^{-\frac{2\pi f_r}{2Q}t}\sin \left(2\pi f_{r}t\right)& \left(5\right)\\ \mathrm{where},& \\ Z_r=\sqrt{L_r\text{/}{C}_r}& \end{array}$
is the characteristic impedance of the resonant tank; ΔV=0.5V.sub.cell−V.sub.bus is the voltage applied on the resonant network, Q is the quality factor of the resonant tank, and f.sub.r is the resonant frequency, given by:

(65) $\begin{array}{cc}{f}_r=\frac{1}{2\pi \sqrt{L_r{C}_r}}& \left(6\right)\end{array}$

(66) FIG. 13 shows convergence results of the balancing structure as obtained through simulation. A pack of eight batteries (emulated by large capacitances) has been preset to different voltages, by the balancing action their voltages converge to the average value of the pack, validating the operation of the system. As FIG. 13 shows, at the initial state, battery 1 was at 4.1V, battery 2 was at 3.8V, battery 3 was at 3.2V, battery 4 was at 4.0V, battery 5 was at 3.3, battery 6 was at 3.9V, battery 7 was at 3.7V, and battery 8 was at 3.6V. A convergence was obtained after less than 200 ms.

(67) Experiment

(68) TABLE-US-00001 TABLE I EXPERIMENTAL PROTOTYPE VALUES Component Value Batteries (emulated by large capacitors) 45 mF Transformer leakage inductances L.sub.1, L.sub.2 2 μH Transformer magnetizing inductances L.sub.m1, 2.5 mH L.sub.m2 SCC capacitors 10 μF MOSFETs S.sub.m1-S.sub.m12 30 V, 5.7 mΩ Bus capacitor C.sub.bus 15 mF Switching frequency ƒ.sub.s 200 kHz

(69) TABLE-US-00002 TABLE II EXPERIMENTAL PROTOTYPE VALUES - RESONANT LINK Component Value Resonant inductances L.sub.r1, L.sub.r2 45 mF Resonant capacitance C.sub.r1, C.sub.r2 150 nF Resonant frequency ƒ.sub.r 220 kHz

(70) To demonstrate the balancing operation and verify the theoretical analysis and simulation results, several experiments have been carried out using two modules of the series balancing system with parallel links as described in FIGS. 2 and 3. Each module consists of three battery cells and all six-battery cells are connected in series. Table I shows the components types and values of the experimental setup described in FIG. 2. Table II summarizes the experimental parameters for the prototype described in FIG. 2. The hardware prototype is shown in FIG. 14.

(71) The experiments have proven the applicability of the circuits of the invention. The voltages of all six cells that have been used converge to their average value. Furthermore, once balance has been obtained, the current decayed to zero since, upon balancing, the voltage difference between all cells were zero. Convergence to voltage difference of 300 mV took 240 ms, where with the hybrid configurations, the duration has been trimmed down by 37.5% to 150 ms and by 12.5% to 210 ms.

(72) According to a third aspect of the present invention, the balancing system comprises a non-isolated parallel batteries balancing topology with a simple sensorless implementation and reduced component count that reduces the complexity of the balancing solution.

(73) FIG. 15 shows an embodiment of the present invention comprising a string of a plurality of cells connected in series. Balancing of the string is achieved through voltage equalization of all cells. As before, the system comprises a topology that equalizes the voltage of each of the cells to their average voltage using a common global (bus) capacitor C.sub.bus. The overall volume and complexity of the system is small, since neither transformers nor sensors are required. This is facilitated by utilizing conduction paths of a neighboring module to link with the energy buffer C.sub.bus. The converter operates in DCM and the current that flows between the cells and the bus is a function of their voltage difference. As a result, the quiescent power loss is minimal since no energy circulates in the system when the cells are balanced (this is in similarity to the previous embodiments).

(74) The operation of the balancing system of FIG. 15 is based on voltage equalization between the batteries and the bus capacitor C.sub.bus. By connecting a cell to the bus capacitor through an inductor, as shown in a simplified manner in FIGS. 16(a)-16(d), the inductor current direction is governed by the polarity of the voltage difference and the current naturally flows toward to the source with the lower voltage and charges it.

(75) In the system of FIG. 15, the bus capacitor is common for all the n battery cells using n balancing modules, each module comprises a battery cell, 4 switches and an inductor. The modules are bidirectional converters that operate sequentially, for example, every switching cycle a different module (or a different current flow relating to that module) is active. This procedure is repeated for all the battery cells. Assuming similar cells, this results in a bus capacitor voltage that converges to the average of the cells' voltages, given by:

(76) $\begin{array}{cc}{V}_{\mathrm{bus}}=\frac{1}{n}\underset{m=1}{\overset{n}{.Math.}}{V}_{\mathrm{cell},m}& \left(7\right)\end{array}$
where V.sub.bus is the bus capacitor voltage and n is the number of cells in the string. Since the bus (global) capacitor is common for the entire string, the respective voltages of all the cells eventually balanced and their voltages converge to (7).

(77) The circuit of this embodiment uses the adjacent balancing module for a return conduction path for the current when balancing a certain cell takes place. As a result, fewer switches are required and the inductor per module is of lower volume. For example, as can be seen in FIG. 16, when balancing V.sub.cell,1, the inductor L.sub.2 of the adjacent module is used in the return path of the current. The system operation is set to DCM, so that the inductors' current at the beginning of the switching cycle is zero. This guarantees that there is no current imbalance between the inductors. The direction of the current flow is governed by the voltage difference between V.sub.bus and V.sub.cell, eliminating the need for current sensing. In the case that the voltages are equal, no current circulates through the circuit.

(78) The balancing method of the system showing two adjacent modules (with two adjacent battery cells) is shown in FIGS. 16a-16d. The system comprises cells Cell,1, and Cell,2 connected in series having a voltage of V.sub.cell,1 and V.sub.cell,2 respectively, wherein Cell,1 is connected to Cell,2. During the first balancing period of the cell (FIG. 16a or FIG. 16c), the adjacent module (with V.sub.cell,2) switches S.sub.21 and S.sub.24 are turned on to create a return path for the current. In the first step, switches S.sub.11 and S.sub.13 are on and the current in the inductors L.sub.1 and L.sub.2 ramp up or down, determined by the voltage difference polarity of ΔV=V.sub.cell,1−V.sub.bus. In the case when:

(79) V.sub.cell,1>V.sub.bus (FIG. 16a) the energy is transferred from V.sub.cell,1 to the bus capacitor V.sub.bus, and in the case when:

(80) V.sub.cell,1<V.sub.bus (FIG. 16c) the energy is transferred in the opposite direction.

(81) In the second step (FIG. 16b or FIG. 16d), after the predefined on time that ensures operation in DCM, and regardless of the current direction, switches S.sub.11 and S.sub.13 are turned off. At this point, due to continuity of the inductors current, either the body diodes of switches S.sub.12 and S.sub.13 (for case of FIG. 16b) or S.sub.11 and S.sub.14 (for case of FIG. 16d) are forward biased for the case V.sub.cell,1>V.sub.bus (FIG. 16b) or V.sub.cell,1<V.sub.bus (FIG. 162d), respectively. The applied voltage on the inductors when the body diodes conduct is the minimum between V.sub.cell,1 and V.sub.bus, ramping down the current back to zero. The current remains zero until the start of the next switching cycle.

(82) FIG. 17 shows the current I.sub.L (top) and voltage (bottom) waveforms for the case that V.sub.cell,1>V.sub.bus. During the on time, the inductors current ramps up with a slew rate of:

(83) $\begin{array}{cc}\frac{{\mathrm{di}}_L}{\mathrm{dt}}=\frac{V_{\mathrm{cell},1}-V_{\mathrm{bus}}}{L_1+L_2}& \left(8\right)\end{array}$

(84) During the off time, the applied voltage on the inductors is the minimum between the two voltages, and therefore the inductors current ramps down with a slew rate of:

(85) $\begin{array}{cc}\frac{{\mathrm{di}}_L}{\mathrm{dt}}=\frac{\min \left(V_{\mathrm{cell},1},V_{\mathrm{bus}}\right)}{L_1+L_2}& \left(9\right)\end{array}$

(86) The body diodes stop conducting at the point where the current is zero. Neglecting the parasitic oscillations that are common for any DCM operation, the current remains zero until the next switching cycle.

(87) The balancing of the adjacent cell no. 2 (V.sub.cell,2) is performed in a similar manner to the balancing operation of cell no. 1 As described above.

(88) To demonstrate the balancing operation of the system, a simulation case experiment has been carried out and the results are shown in FIG. 18. It depicts the convergence of four cells (emulated by large capacitances), each set with different initial voltages, to the cells' average voltage, validating the balancing capability of the system. The top curve refers to V.sub.cell,1, the next one to V.sub.cell,4, then V.sub.bus, V.sub.cell,3, and finally V.sub.cell,2 (the bottom curve).

(89) The use of a non-isolated topology forces the balancing modules to operate sequentially. This is carried out to avoid undesired current loops that may occur as a result of two distant modules that are operated at the same time. In addition, according to a preferred embodiment of the present invention, to eliminate additional current loops through the body diodes of the switches in the non-active modules when other modules are active, the switches on the bus side (i.e. near V.sub.bus) are realized as four-quadrant devices, constructed using two MOSFETs connected back-to-back, as depicted in FIG. 19.

(90) The use of bidirectional switches presents an additional challenge related to the sensorless operation of this embodiment. The body diodes of the switches conduct due to the continuity of the inductors current, and the specific body diodes that are forward biased depend on the current direction (e.g. S.sub.13 in FIG. 16b and S.sub.14 in FIG. 16d). Therefore, to still benefit from the natural diode conduction, the bidirectional switches need to operate as diodes during the off time of the balancing operation. This fact rules out the possibility of driving them with the same gate signal and each should have its own driver with respect to the proper source potential. According to one embodiment, such configuration is realized by a simple bootstrapped driver as shown in FIG. 20. This Figure shows an example of an implementation of a bidirectional switch and an independent gate driver per transistor using a conventional bootstrapped driver (wherein the bootstrap capacitor's current charging loop is marked in by bold lines). In this configuration, the bootstrap capacitor is connected to the source of the upper MOSFET, and when the lower MOSFET is on, the capacitor is charged through two diodes: the bootstrap diode D.sub.B and body diode of the upper MOSFET, as highlighted. A similar arrangement is used for the switches S.sub.m3 and S.sub.m3a.

(91) The main objective of the single inductor in the module is to limit the balancing current as a result of two low-impedance sources (the cell and the bus capacitor) connect to each other. Therefore, the inductance value L, the on time of the switches T.sub.on, and the voltage difference between the battery cell voltage and the bus capacitor voltage ΔV govern the current that flows through the inductor in every switching cycle. In the following analysis it is assumed that the inductors of all the balancing modules are equal to inductance L.

(92) Since each balancing module operates in DCM, the peak inductor current I.sub.pk and the inductor's current ripple ΔI.sub.L are equal. As described earlier, the current flows through two inductors and therefore I.sub.pk and ΔI.sub.L are given by:

(93) 0$\begin{array}{cc}{I}_{\mathrm{pk}}=\Delta I_L=\frac{\Delta V}{2L}{T}_{\mathrm{on}}& \left(10\right)\end{array}$

(94) After turning off the switches, the time it takes for the current to ramp down back to zero can be expressed as:

(95) $\begin{array}{cc}{T}_{\mathrm{off}}^{\prime }=\frac{\Delta V}{\min \left(V_{\mathrm{cell}},V_{\mathrm{bus}}\right)}{T}_{\mathrm{on}},& \left(11\right)\end{array}$
and the average inductors current in a single switching cycle is:

(96) $\begin{array}{cc}{I}_L=\frac{\Delta V}{4L}\left(1+\frac{\Delta V}{\min \left(V_{\mathrm{cell}},V_{\mathrm{bus}}\right)}\right)\frac{T_{\mathrm{on}}^2}{T_s},& \left(12\right)\end{array}$
where T.sub.s is the switching period.

(97) As can be seen in (12), in the case that the cells are balanced and no voltage difference exists, i.e. ΔV=0, the inductors current is zero and no energy circulates through the system, resulting in a minimal quiescent power loss. To expedite the convergence time, small inductance values may be selected. This is due to the higher current that can be delivered. However, it would require a design with lower stray resistance (switches and inductors) to avoid high conduction losses during balancing.

(98) To guarantee the system's operation in DCM, T.sub.on has to be limited. The maximum on time T.sub.on,max depends on the given maximum voltage difference ΔV.sub.max and the minimum voltage between the battery and the bus, and it is given by:

(99) $\begin{array}{cc}{T}_{\mathrm{on},\max }=\frac{\min \left(V_{\mathrm{cell}},V_{\mathrm{bus}}\right)\text{/}\Delta V_{\max }}{1+\min \left(V_{\mathrm{cell}},V_{\mathrm{bus}}\right)/\Delta V_{\max }}{T}_s,& \left(13\right)\end{array}$

(100) This implies that for a case where ΔV is expected to be high, the upper limit of T.sub.on should be set sufficiently low to limit the peak current. However, the more practical case is where the string has relatively small voltage differences, i.e. ΔV is relatively low, in the range of tens of millivolts (in particular in Li-ion cells). In this case, the upper limit for the on time (along with the inductance value) would determine the total convergence time.

(101) The capacitance of the bus capacitor that acts as an energy buffer between the cells should be sufficiently low with respect to the capacity of the batteries. This is to assure relatively fast convergence to the cells' voltages average value, as in (7). On the other hand, a small voltage ripple is desired at the bus voltage to minimize its effect on the balancing operation. Therefore, the minimum bus capacitance that should be used must satisfy the condition:
V.sub.ripple<<ΔV  (14)
where V.sub.ripple is the voltage ripple of the bus capacitor. Using (12), (13) and after some manipulations, condition (14) translates into:

(102) $\begin{array}{cc}{C}_{\mathrm{bus}}>>\frac{T_{\mathrm{on},\max }^2}{4L},& \left(15\right)\end{array}$
where f.sub.s is the switching frequency.
Experiments

(103) In order to demonstrate the balancing operation of the third aspect of the present invention and to verify the corresponding theoretical analysis and simulation results, several experiments have been carried out using two cells connected in series, emulated by large capacitors. Table III shows the components types and values of the experimental setup. The balancing time between the cells is shared equally, where one cell is being balanced for a switching cycle and the other is being balanced in the consecutive switching cycle.

(104) TABLE-US-00003 TABLE III EXPERIMENTAL PROTOTYPE VALUES Component Value Batteries (emulated by large capacitors) 60 mF Module inductors L.sub.1, L.sub.2 3.3 μH MOSFETs S.sub.m1-S.sub.m8 30 V, 5.7 mΩ Bus capacitor C.sub.bus 100 μF Balancing operation on time T.sub.on ½ ƒ.sub.s Switching frequency ƒ.sub.s 100 kHz

(105) FIG. 21 presents the steady-state operation current waveforms in L.sub.1 and L.sub.2 for unbalanced cells with T.sub.on=0.5 T.sub.s. The measurements are taken when the cells' voltages are V.sub.cell,1=8V and V.sub.cell,2=12V and the bus voltage is V.sub.bus=10V. Since the cells voltages are symmetrical with respect to the bus voltage (same voltage difference, but opposed polarity), the currents i.sub.L1 and i.sub.L2 are 180° out of phase and have the same magnitude. FIG. 21 shows the inductors currents for an unbalanced steady-state operation.

(106) FIG. 22 shows convergence of the cells' voltages when cell no. 1 is connected to a 12V DC power supply. As can be observed, when the convergence starts, the balancing system charges cell no. 2 and as a consequence V.sub.Cell,2 rises, while V.sub.bus changes according to the instantaneous cell's voltages average value, in agreement with (7). Also, the inductor current decreases as the cells' voltages converge and ΔV decreases, as predicted by (12). Convergence of the two cells is depicted in FIG. 30. Also here, after the cells have been balanced, the inductor current reaches zero since ΔV=0. More specifically, FIG. 22, shows the convergence of the cells' voltages when Vcell,1 is connected to a 12V DC power supply; Vcell,2 and Vbus converge toward Vcell,1. C1—Vcell,1 (1V/div), C2—Vcell,2 (1V/div), C3—Vbus (1V/div), C4—inductor current iL1 (1A/div). Time scale is div.

(107) As shown the present invention discloses a hybrid-hierarchical system that are characterized by small component count. In the first and second aspects of the invention, the number of the controlled switches is significantly reduced, as several of the switches a commonly used by both the local balancing scheme and by the global scheme. In the third aspect, the circuit does not at all use a transformer, nor local capacitors, wherein each module has only one inductor, while in order to carry out the invention, during each balancing period the balancing circuit is closed through the inductor of the adjacent module. Furthermore, in the present invention the DCM operation and the fact that no energy circulates in the system when the cells are balanced result in extremely low quiescent power loss. The control and operation of the modules is simple and does not require any current or voltage sensors to regulate or control the system. The results of the experimental prototypes have been found in excellent agreement with the theoretical analysis and showed fast convergence of the cells to negligibly small voltage difference.

(108) While some of the embodiments of the invention have been described by way of illustration, it will be apparent that the invention can be carried into practice with many modifications, variations and adaptations, and with the use of numerous equivalents or alternative solutions that are within the scope of a person skilled in the art, without departing from the spirit of the invention, or the scope of the claims.