Health monitoring and failure prognosis of power electronics devices

Abstract

A system, method and machine-readable instructions for monitoring a power electronics device. The system involves a semiconductor device, at least one sensor and a processor. The processor is configured to monitor a junction temperature of the semiconductor device by determining from the at least one sensor an on-state resistance of the semiconductor device and calculating the junction temperature of the semiconductor device according to a relationship between the on-state resistance of the semiconductor device and the junction temperature of the semiconductor device. The processor may apply an ageing coefficient to the on-state resistance.

Claims

1. A system for monitoring a power electronics device, the system comprising: a semiconductor device having a case; at least one sensor; and a processor, wherein the processor is configured to monitor a junction temperature of the semiconductor device by: determining from the at least one sensor an on-state resistance of the semiconductor device, and calculating the junction temperature of the semiconductor device according to a relationship between the on-state resistance of the semiconductor device, based on aged samples lookup table data, and a case temperature of the semiconductor device.

2. A system according to claim 1, wherein the relationship comprises a mathematical relationship, lookup table, or graph correlating aged on-state resistance values with case temperature values and junction temperature values.

3. A system according to claim 1, wherein the relationship comprises a mathematical curve definition or a non-linear regression model.

4. A system according to claim 1, wherein the power electronics device is a power converter.

5. A system according to claim 1, wherein the semiconductor device is an insulated-gate bipolar transistor.

6. A system according to claim 1, wherein the processor outputs at least one of a control and an alert signal for the semiconductor device based upon the calculated junction temperature being greater than a threshold value.

7. A system according to claim 6, wherein, in response to the calculated junction temperature being greater than the threshold value, the processor outputs a signal to at least one of: shut down the power electronics device, limit further operation of the power electronics device, and at least one of schedule maintenance, repair, and replacement of the power electronics device.

8. A system according to claim 1, wherein the at least one sensor comprises at least one of a current sensor and a voltage sensor.

9. A system according to claim 8, wherein at least one of a phase current and a phase voltage is sensed by the sensor.

10. A system according to claim 9, wherein the processor extracts from at least one of the sensed phase current and the sensed phase voltage at least one of a semiconductor device current and a semiconductor device voltage.

11. A system according to claim 1, wherein the processor determines the on-state resistance based on an output of the at least one sensor and an age of the semiconductor device by calculating a modified on-state resistance of the semiconductor device dependent on the age of the semiconductor device.

12. A system according to claim 11, wherein the processor applies an ageing coefficient (α) to the on-state resistance.

13. A system according to claim 12, wherein the processor determines at least one of a change in the junction temperature and a number of junction temperature calculations, and the ageing coefficient is updated in response to at least one of the change in the junction temperature being more than a first predetermined threshold and the number of junction temperature calculations effected being more than a second predetermined threshold.

14. A method of determining a junction temperature in a semiconductor device, the method comprising: determining an on-state resistance of the semiconductor device; calculating the junction temperature of the semiconductor device; and defining a first relationship between the on-state resistance of the semiconductor device and the junction temperature of the semiconductor device, wherein the junction temperature of the semiconductor device is calculated according to a second relationship between the on-state resistance of the semiconductor device, based on aged samples lookup table data, and a case temperature of the semiconductor device.

15. A method according to claim 14, further comprising outputting at least one of a control signal and an alert for the semiconductor device based upon the calculated junction temperature.

16. A method according to claim 14, wherein the first relationship is attained by offline thermal characterisation of the semiconductor device.

17. A method according to claim 16, further comprising applying the offline thermal characterisation of the semiconductor device to the determined on-state resistance of the semiconductor device.

18. A data carrier comprising machine readable instructions for operating at least one processor in a system for monitoring a power electronics device to monitor a junction temperature of a semiconductor device by: receiving at least one sensor signal and determining from the at least one sensor signal an on-state resistance value of the semiconductor device; calculating the junction temperature of the semiconductor device; and accessing a stored first relationship between the on-state resistance of the semiconductor device and the junction temperature of the semiconductor device, and wherein the junction temperature of the semiconductor device is calculated according to a second relationship between the on-state resistance of the semiconductor device, based on the stored first relationship, and a case temperature of the semiconductor device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments will now be described by way of example only, with reference to the Figures, in which:

(2) FIG. 1 is an example of a first conventional method for determining the junction temperature of a semiconductor device;

(3) FIG. 2 is an example of a conventional method for determining the junction temperature of a semiconductor device;

(4) FIG. 3 is a graph illustrating threshold voltage temperature dependence for different samples of the same IGBT type;

(5) FIG. 4 is a block diagram of an example implementation of the junction temperature prediction model in a power converter system;

(6) FIG. 5 is a graph illustrating the typical output characteristics of an insulated-gate bipolar transistor (IGBT) for a constant gate voltage and a constant junction temperature;

(7) FIG. 6 is a graph illustrating measured collector-emitter threshold voltage data with respect to junction temperature;

(8) FIG. 7 is a circuit diagram illustrating the equivalent electrical circuit of FIG. 4 when switches s.sub.1, s.sub.4 and s.sub.6 are in the on-state;

(9) FIG. 8 is a comparison of the proposed computation method for on-state resistance with measured on-state resistance with respect to change in junction temperature;

(10) FIG. 9 is a graph illustrating how on-state resistance varies with power cycling;

(11) FIG. 10 is a flowchart illustrating the method by which the processor monitors the junction temperature of the semiconductor device.

(12) FIG. 11 is a diagram of a three-phase inverter rig developed for testing of the method by which the processor monitors the junction temperature of the semiconductor device.

(13) FIG. 12 is a graph illustrating estimated device current, device voltage and on-state resistance according to the method by which the processor monitors the junction temperature of the semiconductor device.

(14) FIG. 13 is a graph illustrating an unfiltered comparison of the measured junction temperature and the estimated junction temperature according to the method by which the processor monitors the junction temperature of the semiconductor device.

(15) FIG. 14 is a graph illustrating a comparison of the measured junction temperature and the estimated junction temperature according to the method by which the processor monitors the junction temperature of the semiconductor device, over a 10 second period.

(16) FIG. 15 is a graph illustrating a comparison of the measured junction temperature and the estimated junction temperature according to the method by which the processor monitors the junction temperature of the semiconductor device, over a 100 second period.

DETAILED DESCRIPTION

(17) The present disclosure proposes the use of IGBT on-state resistance as a temperature sensitive electrical parameter to extract the IGBT junction temperature.

(18) In this proposed method, the junction temperature is calculated using the characteristic of the IGBT that the on-state resistance is a function of the junction temperature. This approach consists of two processes: off-line thermal characterization of the IGBT with respect to the on-state resistance, and on-line estimation of the on-state resistance and subsequent extraction of junction temperature based on the characterized data.

(19) FIG. 4 illustrates an example system for monitoring a power electronics device. Here, the power electronics device is an inverter, however it will be appreciated that the power electronics device could be any power electronics device to which the present disclosure is applicable.

(20) The example system comprises a number of voltage and current sensors configured to measure the phase current and phase voltage of the inverter. The voltage sensors may be standard voltmeters. The current sensors may be standard ammeters.

(21) The example system further comprises a condition monitoring system. The condition monitoring system comprises at least one processor configured to monitor the junction temperature of the IGBT in the inverter.

(22) FIG. 5 illustrates typical output characteristics of an insulated-gate bipolar transistor (IGBT) for a constant gate voltage and a constant junction temperature. From the output characteristics, at a given current, the voltage drop between collector and emitter can be calculated as:
V.sub.CEon(t)=V.sub.CEO+i.sub.c(t)*r.sub.CE  (1)
where V.sub.CEO represents the collector-emitter threshold voltage, r.sub.CE represents the initial on-state resistance, i.sub.c represents the device current, and V.sub.CEon(t) represents the collector-emitter on-state voltage.

(23) By rearranging equation (1), the device on-state resistance can be expressed as:

(24) $\begin{array}{cc}{r}_{\mathrm{CE}}=\frac{\left[V_{\mathrm{CEon}}\left(t\right)-V_{\mathrm{CEO}}\right]}{i_c\left(t\right)}& \left(2\right)\end{array}$
where the initial value of the collector-emitter threshold voltage (V.sub.CEO) can be taken from the semiconductor device manufacturer specification sheet.

(25) FIG. 6 illustrates measured collector-emitter threshold voltage data with respect to junction temperature. The collector-emitter threshold voltage has a strong dependency on the junction temperature (T.sub.j(t)), which itself is considered as a time varying quantity. Hence, the equation given in (2) can be written as:

(26) $\begin{array}{cc}{r}_{\mathrm{CE}\_\mathrm{est}}=\frac{\left[V_{\mathrm{CEon}}\left(t\right)-\left(V_{\mathrm{CEO}}\left(T_j\left(t\right)\right)\right)\right]}{i_c\left(t\right)}& \left(3\right)\end{array}$

(27) The temperature dependency of collector-emitter threshold voltage can therefore be expressed as a function of junction temperature, as:
V.sub.CEO(T.sub.j(t))=V.sub.CEO*(a.sub.1*T.sub.j(t)+a.sub.2)  (4)
where coefficients a.sub.1 and a.sub.2 can be obtained using device specification sheer, or by off-line thermal characterization of the collector-emitter threshold voltage (V.sub.CEO) as a function of junction temperature.

(28) FIG. 7 illustrates the equivalent electrical circuit of FIG. 4 when switches s.sub.1, s.sub.4 and s.sub.6 are in the on-state. The device voltage can be obtained from the switching states of the inverter and the inverter output voltage. For example, assuming the load is balanced, the voltage drops across switch 4 and switch 6 are almost equal for the case shown in FIG. 7, and the approximate device voltage can be extracted from the output line and dc link voltage, as:
V.sub.CEon1=[(V.sub.dc−V.sub.ab)−((I.sub.B*r.sub.CE4)+V.sub.CE04)]  (5)
where (5) is valid only when s.sub.1, s.sub.4, and s.sub.6 are ON and I.sub.R>0.

(29) Similarly, for another switching state:
V.sub.CEon2=[(V.sub.dc+V.sub.ab)−((I.sub.B*r.sub.CE3)+V.sub.CE03)]  (6)
where (6) is valid only when s.sub.2, s.sub.3, and s.sub.6 are ON and I.sub.R<0

(30) The default values of r.sub.CE_1 r.sub.CE_2, r.sub.cE3, r.sub.cE4 are obtained using eqn (2) and V.sub.cE03, V.sub.cE04 are taken from the device manufacture specification sheet.

(31) The total device current can be calculated from a combination of the device currents in the inverter system of FIG. 7. Each device current in the inverter system can be extracted from the load phase currents using the reconstruction technique. The device currents are mathematically reconstructed as:

(32) $\begin{array}{cc}\left[\begin{array}{c}{i}_{c1}\\ i_{c2}\\ i_{c3}\\ i_{c4}\\ i_{c5}\\ i_{c6}\end{array}\right]=\frac{1}{2}\left[\begin{array}{ccc}\left(1+\mathrm{sign}\right)s_1& 0& 0\\ 0& \left(1+\mathrm{sign}\right)s_2& 0\\ 0& 0& \left(1+\mathrm{sign}\right)s_3\\ \left(1-\mathrm{sign}\right)s_4& 0& 0\\ 0& \left(1-\mathrm{sign}\right)s_5& 0\\ 0& 0& \left(1-\mathrm{sign}\right)s_6\end{array}\right]*\left[\begin{array}{c}{I}_A\\ I_B\\ I_C\end{array}\right]& \left(7\right)\end{array}$
where the ‘sign’ can be either +1 or −1, depending on the direction of load currents I.sub.A, I.sub.B, I.sub.C.

(33) FIG. 8 illustrates a comparison of the proposed computation method for on-state resistance with measured on-state resistance with respect to change in junction temperature for a Semikron SKM150 GB 12T4G module. The on-state resistance measurement is taken using Tektronix curve tracer equipment. From the results plotted in FIG. 8, it can be observed that the proposed estimation method follows the same pattern as the measured results, and the maximum error between measurement and estimation is approximately (±5%).

(34) This variation in on-state resistance is assigned to device degradation. FIG. 9 shows the value of on-state resistance with respect to accelerated ageing cycles. As can be seen, ageing leads to an increase in the on-state resistance in all of the tested modules. The on-state resistance increases almost 80% from the original values specified in the device data sheet. From the experimental investigation results, it can be seen that the increase in on-state resistance is directly related to the magnitude of change in junction temperature (ΔT.sub.j). In other words, the device degradation is much quicker when the magnitude of change in junction temperature is higher. Hence, when estimating on-state resistance, the device degradation must be taken into consideration to improve the accuracy of the estimation method.

(35) The junction temperature of power device is important in estimating health of the power device using device on-state resistance. Since, device degradation easily affects the device on-state resistance and junction temperature. Therefore, it is important to take account of device degradation in estimating junction temperature. Hence, the junction temperature of the power device equal to device case temperature (T.sub.C), when the temperature cycle is less than 1. And junction temperature extracted using modified on-state resistance value.

(36) $\begin{array}{cc}{T}_j\left(t\right)=\left\{\begin{array}{cc}{T}_c\left(t\right)& \mathrm{when}\mathrm{temperature}\mathrm{cycle}<1\\ \left(b_1{r}_{\mathrm{CE}\_\mathrm{act}\left(t\right)}^2+b_2{r}_{\mathrm{CE}\_\mathrm{act}\left(t\right)}+b_3\right)& \mathrm{when}\mathrm{temperature}\mathrm{cycle}>1\end{array}\right\}& \left(8\right)\end{array}$
Where b1, b2, b3 are the temperature co-efficient of aged power devices performed offline using look-up table approach.
where r.sub.ce_act is the modified on-state resistance, which can be given as:
r.sub.CE.sub.act(t)=r.sub.CE.sub.est(t)+r.sub.ce.sup.α  (9)
where r.sub.CE.sub.est(t) is the estimated on-state resistance using equation (3), and r.sub.ce.sup.α is the increase in on-state resistance due to ageing or degradation. The coefficient “α” can be extracted from degraded device samples by applying a curve fitting approach.

(37) FIG. 10 illustrates the method by which the processor monitors the junction temperature of the semiconductor device. At step 100, the processor initiates the monitoring process. This may occur periodically, or in response to the processor receiving a start signal, or in response to the processor receiving a signal indicating that an electrical parameter of the device reaching a predetermined threshold.

(38) At step 110, the processor obtains any required electrical parameters which are stored from the manufacture datasheet of the power electronics device. The electrical parameters may be the collector-emitter threshold voltage (referred to as V.sub.CEO in formulae throughout this patent specification).

(39) These electrical parameters are specific to each power electronics device. These electrical parameters may represent parameters which are correct at the time of manufacture of the power electronics device. These electrical parameters may be affected over time, and thus depend on the age of the power electronics device.

(40) At step 120, the processor instructs the at least one sensor to measure the instantaneous phase current and the instantaneous phase voltage. The processor then determines the device current and the device voltage from these measured values, using equations (5), (6) and (7).

(41) At step 130, the processor calculates the initial on-state resistance of the semiconductor device, e.g. using equation (3). A default on-state resistance (r.sub.CE_1, r.sub.CE_2, r.sub.CE3, r.sub.CE4) may be obtained from equation (2) without considering temperature effect. It can be updated once the processor estimates the r.sub.CE.sub.act using equation (3) at step 130.

(42) At step 140, the processor calculates the modified on-state resistance of the semiconductor device using equation (9). The modified on-state resistance takes into consideration the age of the semiconductor device and therefore accounts for any age degradation of the semiconductor device.

(43) At step 150, the processor calculates the junction temperature of the semiconductor device using the modified on-state resistance of the semiconductor device according to equation (8), determined from offline thermal characterisation of the semiconductor device.

(44) At step 160, the determined junction temperature is displayed to a user. The power electronics device may comprise a display for displaying the determined junction temperature. Alternatively, the determined junction temperature may be displayed via an external device to which the power electronics device is connected. The connection may be a wired connection or a wireless connection.

(45) As the on-state resistance of the semiconductor device varies with the age of the semiconductor device, the degradation variation of the power electronics device is considered when estimating the junction temperature of the semiconductor device. Hence, an ageing algorithm is applied to the monitoring process, illustrated by steps 170-190 of FIG. 10.

(46) At step 170, the processor calculates the number of performed junction temperature measurements, and the magnitude of change in junction temperature. The calculated magnitude of change in junction temperature may be the magnitude of the change in junction temperature since the first junction temperature measurement was taken. The calculated magnitude of change in junction temperature may be the magnitude of the change in junction temperature since the previous measurement was taken.

(47) At step 180, the process decides whether the on-state resistance ageing coefficient (referred to as a in formulae throughout this specification) is to be updated. If the magnitude of change in junction temperature is calculated to be more than a first predetermined threshold and the number of junction temperature measurements taken is calculated to be more than a second predetermined threshold, then the method proceeds to step 190. If the magnitude of change in junction temperature is not calculated to be more than the first predetermined threshold and/or the number of junction temperature measurements taken is not calculated to be more than the second predetermined threshold, then the monitoring process returns to step 110, and the monitoring process is automatically repeated.

(48) In this specific example the first predetermined threshold is 20° C. and the second predetermined threshold is 1000. It is envisaged that the first predetermined threshold may be a temperature in the range of 5-40° C., or 10-30° C. or 15-25° C.

(49) It is envisaged that the second predetermined threshold may be a number in the range of 100-10,000 measurements, or 300-5000 measurements, or 500-3000 measurements. It is also envisaged that algorithm could operate in a mode in which only one of the first and second predetermined thresholds needs to be met in order to update the on-state resistance ageing coefficient.

(50) At step 190, the processor updates the on-state resistance ageing coefficient. The processor stores the updated on-state resistance ageing coefficient for future calculation of the on-state resistance of the semiconductor device, and hence the future determination of the junction temperature of the semiconductor device.

(51) If, at step 180, it is decided that the on-state resistance ageing coefficient is to be updated, then after the on-state resistance ageing coefficient is updated, at step 200, the processor ends the monitoring process. The monitoring process may be re-initiated, using the updated on-state resistance ageing coefficient, after a predetermined time period has elapsed, or in response to the processor receiving a start signal, or in response to the processor receiving a signal indicating that an electrical parameter of the device reaching a predetermined threshold.

(52) In response to the estimated junction temperature being greater than a third predetermined threshold, the power electronics device may provide a signal to shut down the power electronics device, and/or to schedule maintenance and/or repairs and/or replacement of the power electronics device.

(53) The signal may be a visual signal. The visual signal may be displayed on a display of the power electronics device. Alternatively, the visual signal may be displayed on an external device connected to the power electronics device.

(54) Alternatively, or additionally, the signal may be an audio signal. The audio signal may be emitted from the power electronics device. Alternatively, the audio signal may be emitted from an external device connected to the power electronics device.

(55) In order to validate the developed junction temperature estimation method, a three-phase inverter rig was developed, as shown in FIG. 11. The junction temperature is measured by employing a calibrated thermocouple closure to a die of the device (this is achieved by removing the casing of the device and placing the thermocouple in the device).

(56) FIG. 12 shows the experimental results of the estimated device current, the estimated voltage and the calculated on-state resistance of an IGBT module. The devices were tested with a load current of 25 A and a switching frequency of 5 Khz. It can be seen from FIG. 12 that the estimated on-state voltage, and the estimated on-state resistance follow the device current pattern. The error between the estimated on-state voltage and the specified on-state voltage in the device data sheet is less than 2%. The error between the calculated on-state resistance and the stated on-state voltage in the device data sheet is less than 1%.

(57) FIG. 14 shows the experimental results of the estimated junction temperature. The devices were tested with a maximum load current of 30 A and a switching frequency of 5 Khz. It can be seen from FIG. 13 that the estimated junction temperature for a constant current profile follows the measured junction temperature, and the error between the estimated junction temperature and the measured junction temperature is less than 5%.

(58) To verify the accuracy of the developed method in transient conditions, the three-phase converter circuit was energized by a dynamic load current profile. The corresponding results were filtered, and are plotted in FIGS. 15 and 16. It can be seen that the model shows good accuracy in transient conditions. The initial temperature error at the start of the experiment is within ±7.2% and decreases to ±3%.

(59) The system and methods described herein may be advantageous in that accurately estimating the junction temperature of the semiconductor device enables an accurate failure prognosis of the entire power electronics device. That is, the system and methods described herein may allow accurate determination of when the system is likely to fail. In aerospace and marine applications, for example, this allows forward planning of any maintenance, repair or replacement required for the system. The system and methods described herein may therefore be advantageous in preventing the system from reaching failure, reducing unplanned maintenance, enhancing the system availability and/or providing significant cost savings for the system owner.

(60) The system and methods described herein may also be advantageous in that the proposed method uses existing current and voltage information to calculate the junction temperature of the semiconductor device. Unlike conventional temperature sensitive electrical parameter methods, the system therefore doesn't require any additional/bespoke sensing elements, any complex filtering circuits, or any external measurement circuitry. This may allow the proposed method to be applied to conventional “off the shelf” power electronics equipment.

(61) The proposed solutions described herein may be applicable to low power and high power systems that employ power switches. Health monitoring of devices as described herein may be used to improve the reliability and maintainability of power electronics converters. Knowledge of junction temperature can be used to protect the device, e.g. as a control parameter or threshold. Examples of functionality that could be enabled by the solutions proposed herein include: to implement safe shutdown when the temperature goes excessively high (e.g. during an instance of use); to output an alert (e.g. to a user or monitoring facility) when the IGBT device is operated above a predetermined junction temperature to control a converter such that a risk of premature failure is reduced or prevented (e.g. due to repeated excessive thermal stress reducing device life time and increasing the likelihood of premature failure) to allow controlled operation of the device outside/above a rated condition confidently (e.g. the temperature can be predicted for the entire operating range and so operation above the rated condition can be implemented to achieve a particular mission profile); developing/implementing prognostic and/or remaining useful-/operational time estimation capability by using thermal cycle calculation; ability to develop advanced control algorithms to prolong the device life through active thermal control and through advanced temperature control techniques; prediction of the junction temperature of the semiconductor switch at any instant during transient and intransient conditions. use of junction knowledge to improve system reliability, performance and/or weight design of the power system.

(62) The solutions proposed herein may be applied across number of applications that use power semiconductor devices such as IGBT, MOSFET, etc and devices manufactured from different material such as Si, SiC, GaN etc. The application could comprise grid connected inverters and power converters used solar, fuel cell, and wind. Industrial drives may be accommodated, such as variable speed drives used for controlling pumps, rolling mills etc. DC-DC converters may also be accommodated as used in various switch mode power supplies, solid state power controllers, etc.

(63) It will be understood that the invention is not limited to the embodiments above-described and various modifications and improvements can be made without departing from the concepts described herein. Except where mutually exclusive, any of the features may be employed separately or in combination with any other features and the disclosure extends to and includes all combinations and sub-combinations of one or more features described herein.