SUB-SAMPLING PHASE-LOCKED LOOP

Abstract

A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal (S.sub.DLY1) at a first point (t.sub.1) in time and a second delay signal (S.sub.DLY2) at a second point in time (t.sub.2). The sampler module is configured to provide a first sample (S.sub.1) of the oscillator output signal (S.sub.OUT) at the first point in time (t.sub.1) and a second sample (S.sub.2) of the oscillator output signal (S.sub.OUT) at the second point in time (t.sub.2). The interpolator is configured to provide a sampler signal (S.sub.SAMPL) by interpolating the first sample (S.sub.1) and the second sample (S.sub.2). The voltage controlled oscillator is configured to control the oscillator output signal (S.sub.OUT) based on the sampler signal (S.sub.SAMPL).

Claims

1. A sub-sampling phase-locked loop comprising a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator; wherein the digital-to-time converter is configured to provide a first delay signal (S.sub.DLY1) at a first point (t.sub.1) in time and a second delay signal (S.sub.DLY2) at a second point in time (t.sub.2), wherein the first point in time (t.sub.1) is before a first ideal sampling instant for an oscillator output signal (S.sub.OUT) and the second point in time (t.sub.2) is after a second ideal sampling instant for the oscillator output signal (S.sub.OUT), wherein the sampler module is configured to provide a first sample (S.sub.1) of the oscillator output signal (S.sub.OUT) at the first point in time (t.sub.1) based on the first delay signal (S.sub.DLY1) and a second sample (S.sub.2) of the oscillator output signal (S.sub.OUT) at the second point in time (t.sub.2) based on the second delay signal (S.sub.DLY2), wherein the interpolator is configured to provide a sampler signal (S.sub.SAMPL) by interpolating the first sample (S.sub.1) and the second sample (S.sub.2), wherein the voltage controlled oscillator is configured to control the oscillator output signal (S.sub.OUT) based on the sampler signal (S.sub.SAMPL).

2. The sub-sampling phase-locked loop according to claim 1, wherein the digital-to-time converter further is configured to receive a reference signal (S.sub.REF) and a control signal, the control signal defining a factor between a desired frequency of the oscillator output signal (S.sub.OUT) and a frequency of the reference signal (S.sub.REF); produce a converter signal (S.sub.C) defining possible points in time for sampling; and provide the first delay signal (S.sub.DLY1) and the second delay signal (S.sub.DLY2) based on the converter signal (S.sub.C), the reference signal (S.sub.REF) and the control signal.

3. The sub-sampling phase locked loop according to claim 2, wherein the digital-to-time converter further is configured to determine the first ideal sampling instant and the second ideal sampling instant based on the control signal and the reference signal (S.sub.REF).

4. The sub-sampling phase-locked loop according to claim 1, further comprising a forward transfer function module, configured to filter the sampler signal S.sub.SAMPL to provide a filtered sampler signal (S.sub.FILT), wherein the voltage controlled oscillator further is configured to control the oscillator output S.sub.OUT signal using the filtered sampler signal (S.sub.FILT).

5. The sub-sampling phase-locked loop according to claim 1, wherein the sampler module comprises a first sampler, and a second sampler, wherein the first sampler is configured to provide the first sample (S.sub.1) based on the first delay signal (S.sub.DLY1), and wherein the second sampler is configured to provide the second sample (S.sub.2) based on the second delay signal (S.sub.DLY2).

6. The sub-sampling phase-locked loop according to claim 1, wherein the interpolator further is configured to interpolate the first sample (S.sub.1) and the second sample (S.sub.2) using the formula:
S.sub.SAMPL=(1−f)×S.sub.1+f×S.sub.2 wherein f is an interpolation factor having a value in the interval 0-1.

7. The sub-sampling phase-locked loop according to claim 6, wherein the interpolator comprises a first adjustable capacitor device, and a second adjustable capacitor device, wherein the interpolator further is configured to set a capacitance value of the first adjustable capacitor device to (1−f)×C and to store the first sample S.sub.1 in the first adjustable capacitor device, wherein the interpolator further is configured to set a capacitance value of the second adjustable capacitor device to f×C and to store the second sample S.sub.2 in the second adjustable capacitor device, wherein C is both a maximum capacitance value of the first adjustable capacitor device and a maximum capacitance value of the second adjustable capacitor device, and wherein the interpolator further is configured to provide the sampler signal S.sub.SAMPL by connecting the first adjustable capacitor device in parallel with the second adjustable capacitor device.

8. The sub-sampling phase-locked loop according to claim 7, wherein the first adjustable capacitor device comprises M number of engagable unit-sized capacitors, and wherein the second adjustable capacitor device comprises M number of engagable unit-sized capacitors, wherein M≧1, wherein the interpolator further is configured to engage M−m engagable unit-sized capacitors in the first adjustable capacitor device, wherein M≧m, and wherein the interpolator further is configured to engage m engagable unit-sized capacitors in the second adjustable capacitor device, so that the capacitance of the first adjustable capacitor device is (M−m)×C.sub.CAP and the capacitance of the second adjustable capacitor device is m×C.sub.CAP, wherein C.sub.CAP is the capacitance of each unit-sized capacitor.

9. The sub-sampling phase-locked loop according to claim 6, wherein the interpolator comprises a first input configured to receive the first sample (S.sub.1); a second input configured to receive the second sample (S.sub.2); M number of resistors connected in series between the first input and the second input, wherein M≧2, and wherein the M resistors are connected with conductors; an interpolator output, wherein the interpolator further is configured to connect the interpolator output to any one of the conductors, the first input, or the second input, so as to provide the sampler signal (S.sub.SAMPL) on the interpolator output.

10. The sub-sampling phase-locked loop according to claim 1, further comprising an analogue-to-digital converter module configured to provide a digital signal (S.sub.D) by converting a difference between the first sample (S.sub.1) and the second sample (S.sub.2), and wherein the interpolator further is configured to interpolate the digital signal (S.sub.D) to provide the sampler signal (S.sub.SAMPL).

11. The sub-sampling phase-locked loop according to claim 1, wherein the first ideal sampling instant is different from the second ideal sampling instant.

12. The sub-sampling phase-locked loop according to claim 11, wherein the first ideal sampling instant and the second ideal sampling instant are in consecutive periods of the reference signal (S.sub.REF).

13. A method for controlling an oscillator output signal, the method comprising the steps of providing a first delay signal (S.sub.DLY1) at a first point (t.sub.1) in time and a second delay signal (S.sub.DLY2) at a second point in time (t.sub.2), wherein the first point in time (t.sub.1) is before a first ideal sampling instant for the oscillator output signal (S.sub.OUT) and the second point in time (t.sub.2) is after a second ideal sampling instant for the oscillator output signal (S.sub.OUT), providing at least a first sample (S.sub.1) of the oscillator output signal (S.sub.OUT) at the first point in time (t.sub.1) based on the first delay signal (S.sub.DLY1) and a second sample (S.sub.2) of the oscillator output signal (S.sub.OUT) at the second point in time (t.sub.2) based on the second delay signal (S.sub.DLY2), providing a sampler signal (S.sub.SAMPL) by interpolating the first sample (S.sub.1) and the second sample (S.sub.2), and controlling the oscillator output signal (S.sub.OUT) based on the sampler signal (S.sub.SAMPL).

14. A non-transitory storage medium comprising a computer program that runs on a computer with a program code for performing a method comprising the steps of: providing a first delay signal (S.sub.DLY1) at a first point (t.sub.1) in time and a second delay signal (S.sub.DLY2) at a second point in time (t.sub.2), wherein the first point in time (t.sub.1) is before a first ideal sampling instant for the oscillator output signal (S.sub.OUT) and the second point in time (t.sub.2) is after a second ideal sampling instant for the oscillator output signal (S.sub.OUT), providing at least a first sample (S.sub.1) of the oscillator output signal (S.sub.OUT) at the first point in time (t.sub.1) based on the first delay signal (S.sub.DLY1) and a second sample (S.sub.2) of the oscillator output signal (S.sub.OUT) at the second point in time (t.sub.2) based on the second delay signal (S.sub.DLY2), providing a sampler signal (S.sub.SAMPL) by interpolating the first sample (S.sub.1) and the second sample (S.sub.2), and controlling the oscillator output signal (S.sub.OUT) based on the sampler signal (S.sub.SAMPL).

Description

SHORT DESCRIPTION OF THE DRAWINGS

[0044] FIG. 1 shows schematically a sub-sampling phase-locked loop according to an embodiment of the present invention.

[0045] FIG. 2 shows a sub-sampling phase-locked loop according to a further embodiment of the present invention comprising two separate DTCs.

[0046] FIG. 3 is a timing diagram showing the relationship between the reference signal S.sub.REF, the oscillator output signal S.sub.OUT, and the converter signal S.sub.C from the DTC.

[0047] FIG. 4 shows schematically an interpolator and a sampler according to an embodiment of the invention.

[0048] FIG. 5 shows an interpolator and a sampler according to an embodiment of the present invention, which interpolator comprises discrete capacitances.

[0049] FIG. 6 shows an interpolator and a sampler according to a further embodiment of the present invention, which interpolator comprises a resistive ladder.

[0050] FIG. 7 shows an interpolator and a sampler according to a further embodiment of the present invention, which interpolator is configured to work in the digital domain.

[0051] FIG. 8 shows a sub-sampling phase-locked loop according to a further embodiment of the present invention, which sub-sampling phase-locked loop is configured to interpolate two consecutive samples.

[0052] FIG. 9 is a timing diagram showing the relationship between the reference signal S.sub.REF, the oscillator output signal S.sub.OUT, and the converter signal S.sub.C from the DTC.

[0053] FIG. 10 shows a charge-pump which may be used in sub-sampling phase-locked loops according to embodiments of the invention.

[0054] FIG. 11 shows a sub-sampling phase-locked loop connected with a coarse locking phased locked loop.

[0055] FIG. 12 shows a charge-pump based DTC which may be used in a sub-sampling phase-locked loop according to an embodiment of the invention.

[0056] FIG. 13 illustrates a method according to an embodiment of the invention.

DETAILED DESCRIPTION

[0057] In the following detailed description the same reference numeral will be used for the corresponding feature in the different drawings.

[0058] FIG. 1 shows schematically a sub-sampling phase-locked loop 100 according to an embodiment of the present invention. The sub-sampling phase-locked loop 100 comprises a digital-to-time converter 102, a sampler module 104, an interpolator 106, and a voltage controlled oscillator 108. The digital-to-time converter 102 is configured to provide a first delay signal S.sub.DLY1 at a first point t.sub.1 in time and a second delay signal S.sub.DLY2 at a second point in time t.sub.2. The first point in time t.sub.1 is before a first ideal sampling instant for an oscillator output signal S.sub.OUT and the second point in time t.sub.2 is after a second ideal sampling instant for the oscillator output signal S.sub.OUT. The first ideal sampling instant may according to an embodiment be the same sampling instant as the second ideal sampling instant. The sampler module 104 is configured to provide a first sample S.sub.1 of the oscillator output signal S.sub.OUT at the first point in time t.sub.1 based on the first delay signal S.sub.DLY1 and a second sample S.sub.2 of the oscillator output signal S.sub.OUT at the second point in time t.sub.2 based on the second delay signal S.sub.DLY2. The interpolator 106 is configured to provide a sampler signal S.sub.SAMPL by interpolating the first sample S.sub.1 and the second sample S.sub.2. Thus, the sampler signal is an interpolation taking into account a first time difference between the first point in time t.sub.1 and the first ideal sampling instant and a second time difference between the second point in time t.sub.2 and the second ideal sampling instant. The first and second ideal sampling instants are at zero crossings for an ideal signal/desired signal.

[0059] According to an embodiment the interpolation is linear. Thus, the sample taken closest to the ideal sampling instant is given most weight in the interpolation. In this way a sampler signal is provided which corresponds to a sampler signal based on a sample taken at the ideal sampling instant. The voltage controlled oscillator 108 is configured to control the oscillator output signal S.sub.OUT based on the sampler signal S.sub.SAMPL. In this way the frequency of the voltage controlled oscillator is controlled to the desired frequency.

[0060] FIG. 2 shows a sub-sampling phase-locked loop 100 according to a further embodiment of the present invention wherein the digital-to-time converter comprises two separate digital-to-time converter modules (DTC) 162, 162′. The sub-sampling phase-locked loop 100 according to the shown embodiment also comprises a modulator 154 comprising an input 156 and an output 158. The modulator 154 is configured to receive a control signal N.sub.f on the input and to provide control signals for the DTCs 162, 162′, on the output 158. The control signal N.sub.f defines a factor between a desired frequency of the oscillator output signal S.sub.OUT and a frequency of the reference signal S.sub.REF. The modulator 154 is configured to provide modulator signals on its output 158 for controlling the digital-to-time converter modules. Each digital-to-time converter 162, 162′, comprises a first input 150, 150′, and a second input 152, 152′. Each digital-to-time converter module 162, 162′ is configured to receive a reference signal S.sub.REF on said first input 150, 150′, and a modulator signal from the output 158 of the modulator 154 on the second input 152, 152′.

[0061] Each delay signal produced by the DTCs 162, 162′ defines the point in time when a sample of the oscillator output signal S.sub.OUT is to be taken by a downstream sampler. The DTCs 162, 162′, are configured to produce a converter signal S.sub.C defining possible points in time for sampling and to provide the first delay signal S.sub.DLY1 and the second delay signal S.sub.DLY2 based on the converter signal S.sub.C, the reference signal S.sub.REF and the control signal N.sub.f.

[0062] The sub-sampling phase-locked loop 100 in FIG. 2 further comprises a first sampler 116 with an input 170 for the oscillator output signal S.sub.OUT, a delay signal input 172 for the first delay signal S.sub.DLY1 and an output 174 for the first sample S.sub.1. The sub-sampling phase-locked loop 100 in FIG. 2 further comprises a second sampler 130 with an input 176 for the oscillator output signal S.sub.OUT, a delay signal input 178 for the second delay signal S.sub.DLY2 and an output 180 for the second sample S.sub.2. The first sampler 116 is configured to sample the oscillator output signal S.sub.OUT at the first point in time t.sub.1 based on the first delay signal S.sub.DLY1 to derive the first sample S.sub.1. The second sample 130 is configured to sample the oscillator output signal S.sub.OUT at the second point in time t.sub.2 based on the second delay signal S.sub.DLY2 to derive the second sample S.sub.2. The first sampler 116 and second sampler 130 form together a possible implementation for the sampler module 104 shown in FIG. 1. The first sampler 116 and the second sampler 130 each comprise means, such as a capacitor, for measuring and storing a voltage. Possible implementations of samplers are shown in FIG. 4 and FIG. 5.

[0063] The sub-sampling phase-locked loop 100 further comprises an interpolator 106 with a first input 182 for the first sample from the first sampler 116, a second input 184 for the second sample from the second sampler and an output 186. The interpolator 106 is configured to interpolate between the samples to produce the sampler signal S.sub.SAMPL which is provided on the output 186 of the interpolator 106. The sub-sampling phase-locked loop further comprises a filter 188 comprising an input 190 connected to the output of the interpolator 106 and an output 192. The filter 188 is configured to low-pass filter the sampler signal S.sub.SAMPL. Furthermore, the sub-sampling phase-locked loop comprises a voltage controlled oscillator 108 which comprises an input 194 coupled to the output of the filter and an output 266 for the oscillator output signal S.sub.OUT. The voltage controlled oscillator is configured to control the oscillator output signal S.sub.OUT based on the filtered sampler signal. An intermediate circuit called a charge-pump 224 may be arranged between the interpolator 106 and the filter 188 as is indicated by the dashed line. The charge-pump 224 functions as a matching circuit between the interpolator 106 and the filter 188.

[0064] FIG. 3 is a timing diagram showing the relationship between the reference signal S.sub.REF, the oscillator output signal S.sub.OUT, and the converter signal S.sub.C from the DTC. FIG. 3 also shows a small part of the oscillator output signal S.sub.OUT and the points in time for sampling t.sub.1, t.sub.2. A zero crossing 164 from negative voltage to positive voltage for the oscillator output signal S.sub.OUT is shown together with a zero crossings 166 from negative voltage to positive voltage for the reference signal S.sub.REF. Both zero crossings could be used as ideal sampling instants. In this example it should be understood that the zero crossings 164 correspond to the mentioned ideal sampling instants. S.sub.1 and S.sub.2 are the first and second samples taken at the times t.sub.1 and t.sub.2. As is shown in FIG. 3 the first point in time t.sub.1 is before the zero crossing 164 of the oscillator output signal S.sub.OUT and the second point in time t.sub.2 is after the zero crossing 164 of the oscillator output signal S.sub.OUT. The digital-to-time converter or converters provide(s) a first delay signal S.sub.DLY1 (e.g. a rising or falling edge) at the first point in time t.sub.1 and a second delay signal S.sub.DLY2 (e.g. a rising or falling edge) at the second point in time t.sub.2.

[0065] Assuming that the oscillator output signal S.sub.OUT and the reference signal S.sub.REF are aligned at t=0, then, for a fractional ratio N=N.sub.i+N.sub.f, 0≦N.sub.f<1, the N.sub.i'th oscillator output signal zero-crossing happens slightly before the reference edge. The (N.sub.i+1)'th zero-crossing comes slightly after the reference edge. The time difference T.sub.E is given by:

T.sub.E=(1−N.sub.f)×t.sub.VCO

where t.sub.VCO is the period of the oscillator output signal.

[0066] It is also convenient to express this delay in number of oscillator output signal cycles, or:

N.sub.E=1−N.sub.f

[0067] Note that these delays are constants for any given output frequency. The delay at the k'th reference cycle is given by:

n.sub.E[k]=k×N.sub.E=k×(1−N.sub.f)

t.sub.E[k]=n.sub.E[k]×t.sub.VCO=k×(1−N.sub.f)×t.sub.VCO

[0068] The principle behind the sub-sampling phase-locked loop is to delay the positive reference edge such that it coincides with the ideal zero-crossings of the oscillator output signal S.sub.OUT. When the delay is more than one period of the oscillator output signal S.sub.OUT (n.sub.E[k]≧1), the previous S.sub.OUT zero-crossing is sampled instead. This leads to a saw-tooth shaped delay of the reference signal S.sub.REF.

[0069] A modified expression for the delay n.sub.E[k] is given by

n.sub.E[k]=(k×(1−N.sub.f))mod 1

where mod is the modulus operator.

[0070] The digital-to-time converter can be implemented in several ways, which are known to persons skilled in the art and will not be discussed in detail here. FIG. 4 shows schematically an interpolator-sampler module 400 comprising a combination of an interpolator 106 and a sampler according to an embodiment of the invention. The oscillator output signal S.sub.OUT is sampled twice using a delay

[00001]$t_1=\Delta .Math..Math.t.Math.\frac{t_E}{\Delta .Math..Math.t}.Math..Math..Math.\mathrm{and}.Math..Math.t_2=\Delta .Math..Math.t.Math.\frac{t_E}{\Delta .Math..Math.t}.Math.,i.e.,$

one sample before and one sample after the ideal sampling instant. Δt is the resolution of the converter signal S.sub.C and is thus the smallest possible time between two consecutive samples of the oscillator output signal.

[0071] The interpolator-sampler module 400 comprises a first adjustable capacitor device 132 and a second adjustable capacitor device 134. The interpolator-sampler module 400 further comprises a first switch 196 arranged between the first input and the first adjustable capacitor device 132 and a second switch 198 arranged between the second input and the second adjustable capacitor device 134. The interpolator-sampler module 400 further comprises a third switch 200 arranged between the first adjustable capacitor device and the output of the interpolator-sampler module 400 and a fourth switch 202 arranged between the second adjustable capacitor device and the output 186. The interpolator-sampler module 400 further comprises a controller 168 which is configured to adjust the capacitance of the adjustable capacitor devices 132, 134, and the switches 196, 198, 200 and 202. The first switch 196 and the first adjustable capacitor device 132 constitute a first sampler 116. The second switch 198 and the second adjustable capacitor device 134 constitute a second sampler 130. The switches 200 and 202 together with the node at the outputs of the switches 200, 202, constitute an interpolator 106. During a track phase, the first switch 196 and the second switch 198 are closed and the third switch 200 and the fourth switch 202 are open. The voltage over each one of the first adjustable capacitor device 132 and the second adjustable capacitor device 134 tracks the input voltage (the voltage of the oscillator output signal S.sub.OUT). The first adjustable capacitor device 132 holds a charge of Q.sub.1(t)=S.sub.OUT(t)×(1−f)×C, 0≦f<1, wherein (1−f)×C is the capacitance of the first adjustable capacitor device 132. Similarly, the second adjustable capacitor device holds a charge of Q.sub.2(t)=S.sub.OUT(t)×f×C, wherein f×C is the capacitance of the second adjustable capacitor device 134.

[0072] During the hold phase, the first switch 196 and the second switch 198 are opened. The first switch 196 is opened at t=t.sub.1, (the first point in time indicated by the first delay signal S.sub.DLY1) and the second switch 198 is opened at t=t.sub.2 (the second point in time indicated by the second delay signal S.sub.DLY2). At t=t.sub.3>t.sub.2>t.sub.1, the third switch and the fourth switch are closed simultaneously. The total charge is now distributed over the two capacitors, whose total capacitance is C. The voltage therefore becomes:

[00002]$S_{\mathrm{SAMPL}}=\frac{Q_{\mathrm{tot}}}{C_{\mathrm{tot}}}=\frac{S_{\mathrm{OUT}}\left(t_2\right)fC+S_{\mathrm{OUT}}\left(t_1\right)\left(1-f\right)C}{C}=\left(1-f\right)S_1+fS_2.$

Using this technique, the voltages are interpolated by the factor f.

[0073] FIG. 5 shows schematically a further possible interpolator-sampler module 500 comprising a first adjustable capacitor device 132 and a second adjustable capacitor device 134. The first adjustable capacitor device 132 comprises M number of engagable unit-sized capacitors 146, and the second adjustable capacitor device 134 comprises M number of engagable unit-sized capacitors 146, wherein M≧1. The interpolator-sampler module 500 is further configured to engage M−m engagable unit-sized capacitors 146 in the first adjustable capacitor device 132, wherein M≧m, and to engage m engagable unit-sized capacitors 146 in the second adjustable capacitor device 134, so that the capacitance of the first adjustable capacitor device 132 is (M−m)×C.sub.CAP and the capacitance of the second adjustable capacitor device 134 is m×C.sub.CAP, wherein C.sub.CAP is the capacitance of each unit-sized capacitor 146.

[0074] The interpolator-sampler module 500 further comprises a first switch 196 arranged between the first input and the first adjustable capacitor device 132 and a second switch 198 arranged between the second input and the second adjustable capacitor device 134. The interpolator-sampler module 500 further comprises a third switch 200 arranged between the first adjustable capacitor device and the output of the interpolator 106 and a fourth switch 202 arranged between the second adjustable capacitor device and the output 186. The first switch 196 and the first adjustable capacitor device 132 constitute a first sampler 116. The second switch 198 and the second adjustable capacitor device 134 constitute a second sampler 130. The switches 200 and 202 together with the node at the outputs of the switches 200, 202, constitute an interpolator 106. The interpolator-sampler module 500 further comprises a controller 168 which is configured to adjust the capacitance of the adjustable capacitor devices 132, 134, and the switches 196, 198, 200 and 202. The adjustable capacitor according to this embodiment is relatively uncomplicated to implement. The function of the interpolator 106 and sampler according to this embodiment is the same as has been described in relation to the embodiment of FIG. 4. The controller 168 may be integrated into the interpolator-sampler module 500, may be a separate unit or may be a computer program executed on a central control unit.

[0075] FIG. 6 shows schematically a further possible interpolator-sampler module 600 comprising an interpolator 106 and a sampler module 104 according to a further embodiment of the present invention, which interpolator 106 comprises a resistive ladder. The interpolator-sampler module 600 comprises a first sampler 116 with an input 170 for the oscillator output signal S.sub.OUT, a delay signal input 172 for the first delay signal S.sub.DLY1 and an output 174 for the first sample S.sub.1. The interpolator-sampler module 600 further comprises a second sampler 130 with an input 176 for the oscillator output signal S.sub.OUT, a delay signal input 178 for the second delay signal S.sub.DLY2 and an output 180 for the second sample S.sub.2. A first buffer amplifier 212 is connected to the output 174 of the first sampler 116 and a second buffer amplifier 214 is connected to the output 180 of the second sampler 130 to provide a high-ohmic load for each sampler.

[0076] The interpolator 106 comprises a first input 136 configured to receive the first sample S.sub.1 and a second input 138 configured to receive the second sample S.sub.2. The interpolator 106 further comprises M number of resistors 148 connected in series between the first input 136 and the second input 138, wherein M≧2, and wherein the M resistors 148 are connected with conductors 144, and an interpolator output 142. The interpolator 106 is further configured to connect the interpolator output 142 to any one of the conductors 144, the first input 136 or the second input 138, so as to provide the sampler signal S.sub.SAMPL on the interpolator output 142. The interpolator-sampler module 600 further comprises a controller which is configured to control to which conductor 144 the output is to be connected. The controller may alternatively be part of a central control unit or processor. The output voltage is taken over the m'th resistor, giving an output voltage of:

[00003]$S_{\mathrm{SAMPL}}=S_1+\frac{mR}{MR}\left(S_2-S_1\right)=\left(1-\frac{m}{M}\right)S_1+\frac{m}{M}S_2$

[0077] FIG. 7 shows an interpolator-sampler module 700 according to a further embodiment of the present invention. The interpolator-sampler module 700 comprises a first sampler 116 with an input 170 for the oscillator output signal S.sub.OUT, a delay signal input 172 for the first delay signal S.sub.DLY1 and an output 174 for the first sample S.sub.1. The interpolator-sampler module 700 further comprises a second sampler 130 with an input 176 for the oscillator output signal S.sub.OUT, a delay signal input 178 for the second delay signal S.sub.DLY2 and an output 180 for the second sample S.sub.2. The interpolator-sampler module 700 in FIG. 7 also comprises a variable gain amplifier 216 which is connected to the output 174 of the first sampler 116 and the output 180 of the second sampler 130. The interpolator-sampler module 700 comprises a variable gain amplifier 216 an analogue-to-digital converter 217, a gain adjustment block 218 and a digital interpolator 106 configured to work in the digital domain. The difference between the output of the first sampler 116 and the output of the second sampler 130, i.e., the difference between the first sample S.sub.1 and the second sample S.sub.2, is amplified by the variable gain amplifier VGA. The amplified signal is then converted to a digital signal using the analogue-to-digital converter ADC. The gain adjustment block 218 forms a feedback loop that adjusts the gain of the VGA such that the full range of the analogue-to-digital converter ADC is used. The output of the digital interpolator 220 is a digital word, and may be used as is or converted back to analogue again. In case a digital word is to be used to control the voltage controlled oscillator 108 the voltage controlled oscillator has to be adapted to be controlled by a digital word.

[0078] FIG. 8 shows a sub-sampling phase-locked loop 100 according to a further embodiment of the present invention, wherein the sub-sampling phase-locked loop 100 is configured to interpolate two consecutive samples. Thus, the first ideal sampling instant is different from the second ideal sampling instant. The sub-sampling phase-locked loop 100 comprises a digital-to-time converter module DTC 162. The sub-sampling phase-locked loop 100 according to the shown embodiment also comprises a modulator 154 comprising an input 156 and an output 158. The modulator 154 is configured to receive a control signal N.sub.f on the input and to provide control signals for the DTC on the output 158. The control signal N.sub.f defines a factor between a desired frequency of the oscillator output signal S.sub.OUT and a frequency of the reference signal S.sub.REF. The modulator 154 is configured to provide modulator signals on its output 158 for controlling the digital-to-time converter module 162. The digital-to-time converter 162, comprises a first input 150, and a second input 152. The digital-to-time converter module 162 is configured to receive a reference signal S.sub.REF on said first input 150, and a modulator signal from the output 158 of the modulator 154 on the second input 152, the delay signal defining the point in time when a sample of the oscillator output signal is to be taken. The DTCs are configured to produce a converter signal S.sub.C defining possible points in time for sampling and to provide the first delay signal S.sub.DLY1 and the second delay signal S.sub.DLY2 based on the converter signal S.sub.C, the reference signal S.sub.REF and the control signal. The sub-sampling phase-locked loop 100 further comprises a sampler 116 with an input 170 for the oscillator output signal S.sub.OUT, a delay signal input 172 for the first delay signal S.sub.DLY1 and an output 174 for the first sample S.sub.1 and the second sample S.sub.2. The sub-sampling phase-locked loop 100 further comprises an analogue shift register 222 having a first cell C1 and a second cell C2. Each sample S.sub.1, S.sub.2, is injected into the cells C1, C2, of the analogue shift register 222, and the interpolation is performed between sample S.sub.1=S[k] and S.sub.2=S[k−1]. The delay at reference cycle k is d(k). The ideal delay at reference cycle k, expressed as number of DTC delays, is given by

[00004]$d_i\left[k\right]=\frac{t_E\left[k\right]}{\Delta .Math..Math.t}$

Since the DTC delays the input by an integer number of cycles, this number must be rounded to an integer. If the delay is rounded down on even cycles (k=0, 2, . . . ) and up on odd cycles (k=1, 3, . . . ), the samples S.sub.1, S.sub.2, will be alternating between being too low and too high. The voltage at each cycle can be expressed as:

[00005]$S_{\mathrm{OUT}}\left[k\right]=S_q\left[k\right]+S_e\left[k\right]=\left[\left(\frac{2.Math.\pi }{t_{\mathrm{VCO}}}\right)\left(d\left[k\right]-d_i\left[k\right]\right)\Delta .Math..Math.t\right]+S_e\left[k\right]$

[0079] The term S.sub.q[k] is the voltage due to DTC quantization. The term S.sub.e[k] is the voltage due to VCO phase fluctuations. The later is the quantity we wish to sample. In the above equation, it is assumed that the sampler is operating in a small region around the zero-crossing of the VCO signal, such that it can be approximated as a linear function. The sub-sampling phase-locked loop 100 further comprises an interpolator 106 with a first input 182 for the first sample from the first cell C1, a second input 184 for the second sample from the second cell C2 and an output 186. The interpolator 106 is configured to interpolate between the samples to produce the sampler signal S.sub.SAMPL which is provided on the output 186 of the interpolator 106. The sub-sampling phase-locked loop further comprises a filter 188 comprising an input 190 connected to the output of the interpolator 106 and an output 192. The filter 188 is configured to low-pass filter the sampler signal S.sub.SAMPL. Furthermore, the sub-sampling phase-locked loop comprises a voltage controlled oscillator 108 which comprises an input 194 coupled to the output of the filter and an output 266 for the oscillator output signal S.sub.OUT. The voltage controlled oscillator 108 is configured to control the oscillator output signal S.sub.OUT based on the filtered sampler signal.

[0080] FIG. 9 is a timing diagram showing the relationship between the reference signal S.sub.REF, the oscillator output signal S.sub.OUT, and the converter signal S.sub.C from the DTC. FIG. 9 shows two consecutive samples, one at t=(k−1)×T and one at t=k×T.

[0081] If we assume that S.sub.e[k] does not change much from cycle to cycle, i.e., |S.sub.e[k]−S.sub.e[k−1]|<<|S.sub.q[k]−S.sub.q[k−1]|, sample S.sub.s[k] and S.sub.s[k−1] can be interpolated such that S.sub.q[k] is removed and only S.sub.e[k] remains. This assumption holds for a PLL, since the high frequency noise on S.sub.e[k] is usually small. The interpolation factor is given by

[00006]$f\left[k\right]=-\frac{S_{\mathrm{OUT}}\left[k-1\right]}{S_{\mathrm{OUT}}\left[k\right]-S_{\mathrm{OUT}}\left[k-1\right]}=\frac{d_i\left[k-1\right]-d\left[k-1\right]}{d\left[k\right]-d_i\left[k\right]-d\left[k-1\right]+d_i\left[k-1\right]}$

The actual interpolation can be performed as described in previous sections, using a capacitive interpolator, a resistive interpolator or a digital interpolator.

[0082] FIG. 10 shows a charge-pump 224 which may be used in sub-sampling phase-locked loops according to embodiments of the invention as is shown, e.g., in FIG. 2. The charge-pump 224 comprises a first current source 226 with a fixed current (I.sub.U), and a second current source 228 with a current that can be modulated (I.sub.D+g.sub.m×ν.sub.CTRL). The charge pump also comprises an output 268. The current sources are simultaneously connected to the output 268 during a short pulse, and the net output current becomes I.sub.U−I.sub.D−g.sub.m×ν.sub.CTRL. The duty-cycle of the output pulse sets the overall gain of the charge-pump 224. The charge-pump also comprises a first switch 270 between the first current source 226 and the output 268 and a second switch 272 between the second current source 228. The charge-pump 224 also comprises a pulser 274 which is configured to control the first switch 270 and the second switch 272.

[0083] FIG. 11 shows a circuit comprising a sub-sampling phase-locked loop connected with a coarse locking phased locked loop. The circuit comprises a sampler 232 with an input 234 for a reference signal S.sub.REF and an input 262 for an oscillator output signal S.sub.OUT, and an output 258 for a sample S.sub.1. The circuit further comprises a first charge pump 236 with an input 238 for the sample S.sub.1 and an output 240 for a control current i.sub.CP. The circuit further comprises a loop filter 238 with an input 260 for the control current i.sub.CP, and an output 242 for a filtered control signal S.sub.CONTROL. The circuit further comprises a voltage controlled oscillator VCO with an input 264 for the filtered control signal S.sub.CONTROL, and an output 244 for the oscillator output signal S.sub.OUT. Since the sampler 232 can capture any VCO edge, not just the N'th edge, a sub-sampling PLL has a small lock range. To circumvent this, a typical SS-PLL has an additional coarse locking loop, as shown in FIG. 11. The circuit thus further comprises a divide-by-N-member 246, a phase-frequency detector PFD and an additional charge-pump 248. The output current of the second charge-pump 248 is added to that of the first charge-pump 236. This traditional PLL loop has a large locking range. To disable the coarse PLL loop once it has locked, a dead-zone is added to the PFD output such that for small phase differences, its output is zero. In possible further embodiments of the invention the described coarse locking phased locked loop may be used together with the above described embodiments of the sub-sampling phase-locked loop 100.

[0084] FIG. 12 shows a charge-pump based digital-to-time converter DTC 162 which may be used in a sub-sampling phase-locked loop according to an embodiment of the invention. The DTC 162 comprises a first input 150 for the reference signal S.sub.REF. The DTC 162 further comprises a current source 250, a number of capacitors C and switches 256 in a capacitor bank 252 and a logic buffer 254. When the reference clock S.sub.REF goes high, the current source 250 charges the capacitor bank. When the threshold voltage of the logic buffer 254 is reached, the output signal of the DTC S.sub.DLY transitions from low to high. The time it takes to charge the capacitor bank depends on the number of switches 256 that are closed. It is thereby possible, using a digital control, to set the delay in multiples of t.sub.D. Note that for successful operation of the SSF-PLL, t.sub.D should be known.

[0085] FIG. 13 illustrates a method according to an embodiment of the invention. In a first step 202 a first delay signal S.sub.DLY1 is provided at a first point t.sub.1 in time and a second delay signal S.sub.DLY2 is provided at a second point in time t.sub.2. The first point in time t.sub.1 is before a first ideal sampling instant for the oscillator output signal S.sub.OUT and the second point in time t.sub.2 is after a second ideal sampling instant for the oscillator output signal S.sub.OUT. In a second step 204, succeeding the first step providing 202, at least a first sample S.sub.1 of the oscillator output signal S.sub.OUT is provided at the first point in time t.sub.1 based on the first delay signal S.sub.DLY1 and a second sample S.sub.2 of the oscillator output signal S.sub.OUT is provided at the second point in time t.sub.2 based on the second delay signal S.sub.DLY2. In a third step 206 a sampler signal S.sub.SAMPL is provided by interpolating the first sample S.sub.1 and the second sample S.sub.2. Finally, in a fourth step 208 the oscillator output signal S.sub.OUT is controlled based on the sampler signal S.sub.SAMPL.

[0086] It is not necessary, as shown in FIG. 2, to use two DTCs. If a single DTC can output two consecutive reference edges, the two samplers may be clocked by these.

[0087] It is possible to interpolate more than two samples. This might have the added benefit of averaging differences in the step size of the DTC(s). This will increase the complexity of the interpolator.

[0088] Furthermore, any method according to the embodiments of the present invention may be implemented in a computer program, having code means, which when run by processing means causes the processing means to execute the steps of the method. The computer program is included in a computer readable medium of a computer program product. The computer readable medium may comprises of essentially any memory, such as a ROM (Read-Only Memory), a PROM (Programmable Read-Only Memory), an EPROM (Erasable PROM), a Flash memory, an EEPROM (Electrically Erasable PROM), or a hard disk drive.

[0089] Finally, it should be understood that the present invention is not limited to the embodiments described above, but also relates to and incorporates all embodiments within the scope of the appended independent claims.