TIME REGISTER

Abstract

A time register includes: a pair of inputs coupled to a pair of input clocks; a pair of tri-state inverters for producing a pair of level signals; and a pair of outputs coupled to the level signals for producing a pair of output clocks, wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.

Claims

1. A time register comprising: a pair of inputs coupled to a pair of input clocks; a pair of tri-state inverters for producing a pair of level signals; and a pair of outputs coupled to the level signals for producing a pair of output clocks, wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.

2. The time register of claim 1, wherein the tri-state inverters are responsive to the state signals and the input clocks for propagating a time difference of a pair of time differences between the respective input clock and the respective state signal to a voltage difference between the level signals.

3. The time register of claim 2, wherein the voltage difference between the level signals is proportional to the time difference of the pair of time differences.

4. The time register of claim 1, comprising a pair of capacitances for capacitive loading the tri-state inverters.

5. The time register of claim 1, comprising inverters or buffers connected to the tri-state inverters.

6. The time register of claim 1, comprising a charging source for precharging the level signal if the input is low.

7. The time register of claim 1, comprising a logic circuitry for holding the level signal if the input is high and the state signal is low.

8. The time register of claim 7, wherein the logic circuitry is configured to discharge the level signal if the input is high and the state signal is high.

9. The time register of claim 7, wherein the logic circuitry is configured to drive the state signal responsive to a hold signal and an awake signal.

10. The time register) of claim 9, wherein the logic circuitry is further configured to drive the state signal responsive to a preset signal such that the state signal is high if the preset signal is high.

11. The time register of claim 10, wherein the logic circuitry is configured to drive the state signal such that the state signal toggles upon a rising edge of either the hold signal or the awake signal.

12. The time register of claim 9, wherein the awake signal is a sampling clock and wherein the hold signal is a quantization error signal.

13. The time register of claim 12, wherein each of the pair of outputs is produced on the sampling clock, the output clock is a function of a time difference between a corresponding input clock and the quantization error signal.

14. A time register comprising a first circuit and a second circuit), each of the circuits comprising: a tri-state inverter coupled between a capacitive loaded first node and an output node, the tri-state inverter comprising: a PMOS transistor coupled between a battery voltage and the first node); and a first NMOS transistor and a second NMOS transistor coupled in series between the first node and a reference voltage, wherein a control terminal of the PMOS transistor and a control terminal of the first NMOS transistor are driven by an input signal and a control terminal of the second NMOS transistor is driven by a state signal, and wherein the tri-state inverter is configured to propagate a time difference between the input signal and the state signal to a voltage level at the first node.

15. The time register of claim 14, wherein the tri-state inverters of the first circuit and the second circuit are responsive to the state signals and the input signals for propagating a difference of the time difference of the first circuit and the time difference of the second circuit to a difference of the voltage levels at the first node of the first circuit and the second circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Further embodiments of the invention will be described with respect to the following figures, in which:

[0076] FIG. 1 shows a block diagram illustrating the general error-feedback structure 100 in the z-domain according to an implementation form;

[0077] FIG. 2 shows a block diagram illustrating an error-feedback structure 200 in the time-domain according to an implementation form;

[0078] FIG. 3 shows a schematic diagram illustrating a time register 300 according to an implementation form;

[0079] FIG. 4 shows a simplified schematic diagram illustrating the waveforms of signals used in the time register 300 depicted in FIG. 3; and

[0080] FIG. 5 shows a schematic diagram illustrating a method 500 for time buffering according to an implementation form.

DETAILED DESCRIPTION OF EMBODIMENTS

[0081] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

[0082] It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

[0083] FIG. 1 shows a block diagram illustrating the general error-feedback structure 100 in the z-domain according to an implementation form.

[0084] The error-feedback structure 100 includes a first adder 101, a delay unit 103, a quantizer 105, a digital-to-analog converter 109 and a second adder 107. The first adder 101 receives an input signal (U) at a first input 102 and a quantization error (E) at a first node 108 and is configured to subtract the error signal E from the input signal U to provide a first adder output signal 104 that is passed to the delay unit 103. The delay unit 103 delays the first adder output signal 104 by a unit delay to provide a delay unit output signal 106 that is passed to the quantizer 105 and the second adder 107. The quantizer 105 is configured to quantize the delay unit output signal 106 in steps determined by a control signal 114 to provide a digital output signal V at an output 110 of the error-feedback structure 100. The digital output signal V is passed to the digital-to-analog converter 109 to provide an analog output signal 112 that is passed to the second adder 107. The second adder 107 subtracts the delay unit output signal 106 from the analog output signal 112 to provide the quantization error (E) at the first node 118.

[0085] The error-feedback structure 100 can achieve the noise-shaping characteristics without using the integrator, which is the inevitable component in ΔΣ modulator. The z-domain model of the structure is shown in FIG. 1. Here, the quantization error E is obtained in analog form by subtracting the internal quantizer's 105 input 106 from the DAC 109 output 112. E is then fed back to the input (at first node 108) and the error between input signal U and E goes through the unit delay 103, z.sup.−1, whose output 106 is connected to the quantizer 105. The output signal 110 in the z-domain is: V=z.sup.−1U+(1−z.sup.−1) E, where, V is the digital output and U is the analog input.

[0086] The input signal U is not only limited to be an electrical signal, but also can be a manner of temperature, mass and even time. Therefore, the time-domain error-feedback structure 100 can be implemented if the analog form of the z-domain is presented by time-interval as described below with respect to FIG. 2.

[0087] FIG. 2 shows a block diagram illustrating an error-feedback structure 200 with time-interleaved register in the z-domain according to an implementation form. The time-to-digital converter 200 includes an input 202 for receiving a time-domain input signal Tin; an output 206 for providing a digital output signal Dout; a time register 205 coupled to the input 202 and to a first node 208; a time quantizer 207 coupled to the time register 205 for providing the digital output signal Dout at the output 206; and a digital-to-time converter 209 coupled to the output 206 for providing a feed-back signal E at the first node 208. The time register 205 may be implemented as described below with respect to FIG. 3.

[0088] The digital output signal Dout is an oversampled representation of the time-domain input signal Tin. The feedback signal E is a quantization error signal Q.sub.err. The digital-to-time converter 209 is coupled to the time register 205 for delaying an output signal 204 of the time register 205 in response to the digital output signal Dout. The time register 205 combines 203 the time-domain input signal Tin with the feedback signal E to produce a modified time-domain input signal. In FIG. 2, the combination 203 is a subtraction. The time register 205 delays the modified time-domain input signal by at least one cycle of a sampling clock. The time-domain input signal Tin may include a pair of two input signals that may include a first digital clock and a second digital clock. A value of the time-domain input signal Tin may correspond to a time difference between a transition of the first digital clock and a transition of the second digital clock.

[0089] The error-feedback structure 200 corresponds to the error-feedback structure 100 described above with respect to FIG. 1. However, the unit delay z.sup.−1 103 and the first adder 101 that performs a subtraction operation are replaced by a time-domain register 205 combined with subtractor 203. The voltage quantizer 105 or internal ADC of the error-feedback structure 100 described above with respect to FIG. 1 is replaced by a sub-TDC 207, whose input is the time-difference 204 or time interval instead of the voltage. Similarly, digital-to-time converter (DTC) 209 is used here to convert the digital code to time-interval, which is fed back to the input or first node 208 respectively.

[0090] The time-domain register 205 combined with subtractor 203 may be implemented as a plurality of subtractor-register devices 201 that may operate in parallel, e.g. by performing a pipeline processing. Such a parallel processing reduces the processing burden on the time-domain register 205. Instead of a single processing task multiple processing tasks can be performed by the multiple subtractor-register devices 201 in the same time instant.

[0091] The quantization noise is pushed to the high frequency due to the noise-shaping characteristic thus making the TDC's 200 resolution depend on the device noise, such as flicker/thermal noise instead of quantization noise. Therefore, the resolution of the TDC 200 is highly improved and independent from the process of technology. For example, in 40 nm CMOS process the minimal delay of inverter is about 10 ps.

[0092] FIG. 3 shows a schematic diagram illustrating a time register 300 according to an implementation form. The time register 300 includes a pair of inputs 345, 346 coupled to a pair of input clocks IN.sub.1, IN.sub.2; a pair of tri-state inverters 301, 302 for producing a pair of level signals V.sub.C1, V.sub.C2; and a pair of outputs 347, 348 coupled to the level signals V.sub.C1, V.sub.C2 for producing a pair of output clocks OUT.sub.1, OUT.sub.2. The tri-state inverters 301, 302 are responsive to a pair of state signals S.sub.1, S.sub.2 and the pair of input clocks IN.sub.1, IN.sub.2 for holding or discharging the level signals V.sub.C1, V.sub.C2. A first circuit 300a and a second circuit 300b that is a replica of the first circuit 300a are used to provide the respective signal rails of the signal pairs. Instead of the tri-state inverters 301, 302 any other tri-state logic circuit that performs a tri-state or three-state logic may be used.

[0093] The tri-state inverters 301, 302 are responsive to the state signals S.sub.1, S.sub.2 and the input clocks IN.sub.1, IN.sub.2 for propagating a time difference of a pair of time differences T.sub.1, T.sub.2 between the respective input clock IN.sub.1, IN.sub.2 and the respective state signal S.sub.1, S.sub.2 to a voltage difference between the level signals V.sub.C1, V.sub.C2 as described below with respect to FIG. 4.

[0094] The voltage difference between the level signals V.sub.C1, V.sub.C2 may be proportional to the time difference of the pair of time differences T1, T2. The time register 300 further includes a pair of capacitances C.sub.1, C.sub.2 for capacitive loading the tri-state inverters 301, 302. The capacitances C.sub.1, C.sub.2 may include parasitic capacitances coupled between the first node 303, 304 and ground GND. The time register 300 may include inverters 311, 312 or buffers connected to the tri-state inverters 301, 302. The time register 300 may include a charging source VDD for precharging the level signal V.sub.C1, V.sub.C2 if the input 345, 346 is low. The time register 300 may include a logic circuitry 321, 331 for holding the level signal V.sub.C1, V.sub.C2 if the input 345, 346 is high and the state signal S.sub.1, S.sub.2 is low.

[0095] The logic circuitry of FIG. 3 includes a flip-flop 321, e.g. a D flip-flop, and a multiplexer 331 driving the clock input of the flip-flop 321 (depicted in FIG. 3 for the first circuit 300a, however the same logic circuitry exists for the second circuit 300b). The multiplexer 331 switches the Hold signal at port 343 or the Awake signal at port 344 to the clock input of the flip-flop 321. The multiplexer 331 is controlled by the D input of the flip-flop 321 that is equal to the inverting Q output of the flip-flop 321. The non-inverting Q output of the flip-flop 321 produces the first state signal S.sub.1. The second state signal S.sub.2 is produced by a logic circuitry of the second circuit 300b that is not depicted in FIG. 3.

[0096] The logic circuitry 321, 331 operates to discharge the level signal V.sub.C1, V.sub.C2 if the input 345, 346 is high and the state signal S.sub.1, S.sub.2 is high. The logic circuitry 321, 331 operates to drive the state signal S.sub.1, S.sub.2 responsive to a hold signal Hold.sub.1, Hold.sub.2 and an awake signal (Awake). The logic circuitry 321, 331 operates to drive the state signal S.sub.1, S.sub.2 responsive to a preset signal (preset) such that the state signal S.sub.1, S.sub.2 is high if the preset signal (preset) is high. The logic circuitry 321, 331 operates to drive the state signal S.sub.1, S.sub.2 such that the state signal S.sub.1, S.sub.2 toggles upon a rising edge of either the hold signal (Hold.sub.1, Hold.sub.2) or the awake signal (Awake). The awake signal (Awake) may be a sampling clock and the hold signal Hold.sub.1, Hold.sub.2 may be a quantization error signal.

[0097] Each of the pair of outputs 347, 348 is produced on the sampling clock. The output clock OUT.sub.1, OUT.sub.2 is a function of a time difference between a corresponding input clock IN.sub.1, IN.sub.2 and the quantization error signal.

[0098] In the exemplary implementation of FIG. 3, the tri-state inverters 301, 302 are realized by PMOS and NMOS transistors as described in the following. Such an implementation provides a time register 300 including a first circuit 300a and a second circuit 300b, each of the circuits 300a, 300b including a tri-state inverter 301, 302 coupled between a capacitive loaded first node 303, 304 and an output node 347, 348. The tri-state inverter 301, 302 includes a PMOS transistor M.sub.p1 coupled between a battery voltage VDD and the first node 303, 304; a first NMOS transistor M.sub.n1 and a second NMOS transistor M.sub.n2 coupled in series between the first node 303, 304 and a reference voltage GND. A control terminal of the PMOS transistor M.sub.p1 and a control terminal of the first NMOS transistor M.sub.n1 are driven by an input signal IN.sub.1, IN.sub.2 and a control terminal of the second NMOS transistor M.sub.n2 is driven by a state signal S.sub.1, S.sub.2. The tri-state inverter 301, 302 propagates a time difference T.sub.1, T.sub.2 between the input signal IN.sub.1, IN.sub.2 and the state signal S.sub.1, S.sub.2 to a voltage level V.sub.C1, V.sub.C2 at the first node 303, 304 as described below with respect to FIG. 4.

[0099] The tri-state inverters 301, 302 of the first circuit 300a and the second circuit 300b are responsive to the state signals S.sub.1, S.sub.2 and the input signals IN.sub.1, IN.sub.2 for propagating a difference of the time difference T.sub.1 of the first circuit 300a and the time difference T.sub.2 of the second circuit 300b to a difference of the voltage levels V.sub.C1, V.sub.C2 at the first node 303, 304 of the first circuit 300a and the second circuit 300b as described below with respect to FIG. 4.

[0100] The time register 300 may be used as one of the time-domain registers 205 in a time-to-digital converter 200 as described above with respect to FIG. 2.

[0101] FIG. 4 shows a simplified schematic diagram illustrating the waveforms of signals used in the time register 300 depicted in FIG. 3.

[0102] The operation of the time registers with the implicit adder/subtractor is explained with waveforms in FIG. 4. There are four major phases: pre-charge, discharge, hold mode and residual discharge. When the inputs IN.sub.1 and IN.sub.2 are initially low, the load capacitors C.sub.1 and C.sub.2 are pre-charged to VDD by the PMOS transistors M.sub.P1. Due to the initial assertion of the preset signal, the Q output of the flip-flop 321 (corresponding to the state signal S.sub.1, S.sub.2) is initialized to high. After the rising edges are applied to IN.sub.1 and IN.sub.2, C.sub.1 and C.sub.2 start to discharge through Mn.sub.1 and Mn.sub.2 until the rising edges are later applied to Hold.sub.1 and Hold.sub.2, which set the flip-flop 321 Q output to low.

[0103] The voltages V.sub.C1 and V.sub.C2 are held steady until a trigger edge Awake resumes their discharges. Then, the rising edges of IN.sub.1 and IN.sub.2 are eventually propagated to the outputs OUT.sub.1 and OUT.sub.2. In other words, the time difference of T.sub.1 and T.sub.2 is proportional to the voltage difference of V.sub.C1 and V.sub.C2, thus the time-domain subtraction (or addition if inputs are swapped) can be realized during the process of residual discharge, which converts the voltage-difference back to the corresponding time interval. The propagation delay of input-output depends on the duration time of hold mode whose period is equal to 1/Fs and thus, presents a unit delay z.sup.−1 in the z-domain model. A short discharge time is preferred for the immunity of time perturbations associated with the in-band noise of the TDC. Besides, the usage of the single-phase gated inverter (driving C.sub.1/C.sub.2) eliminates the switching mismatches caused by PMOS and NMOS. As a result, the linearity is greatly improved.

[0104] FIG. 5 shows a schematic diagram illustrating a method 500 for time buffering according to an implementation form. The method 500 includes receiving 501 a pair of input clocks; producing 502 a pair of level signals by a pair of tri-state inverters; producing 503 a pair of output clocks based on the pair of level signals; and holding or discharging 504 the level signals responsive to a pair of state signals and the pair of input clocks.

[0105] The pair of level signals may be produced responsive to the state signals and the inputs clocks for propagating a time difference of a pair of time differences between the respective input clock and the respective state signal to a voltage difference between the level signals. The voltage difference between the level signals may be proportional to the time difference of the pair of time differences. The time buffering may include capacitive loading a pair of tri-state inverters. The time buffering may include inverting or buffering an output of the tri-state inverters. The time buffering may include precharging the level signal if the input is low. The time buffering may include holding the level signal if the input is high and the state signal is low. The method 500 may include discharging the level signal if the input signal is high and the state signal is high. The method 500 may include driving the state signal responsive to a hold signal and an awake signal. The method 500 may include driving the state signal responsive to a preset signal such that the state signal is high if the preset signal is high. The method 500 may include driving the state signal such that the state signal toggles upon a rising edge of either the hold signal or the awake signal. The awake signal may be a sampling clock and the hold signal may be a quantization error signal. Each of the pair of outputs clocks may be produced on the sampling clock, the output clock may be a function of a time difference between a corresponding input clock and the quantization error signal.

[0106] The method 500 may implement the same functionality as the time register 300 described above with respect to FIG. 3.

[0107] Time registers as presented above can be used in TDCs which may be implemented in PLLs. When such a time register based TDC is used in a PLL, the noise shaping in spectrum may effect a widening of the bandwidth of the PLL.

[0108] The present disclosure also supports a computer program product including computer executable code or computer executable instructions that, when executed, causes at least one computer to execute the performing and computing steps described herein, in particular the method 500 as described above with respect to FIG. 5 and the techniques described above with respect to FIGS. 1 to 4. Such a computer program product may include a readable storage medium storing program code thereon for use by a computer. The program code may perform the method 500 as described above with respect to FIG. 5.

[0109] While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “include”, “have”, “with”, or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprise”. Also, the terms “exemplary”, “for example” and “e.g.” are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

[0110] Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

[0111] Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

[0112] Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the invention beyond those described herein. While the present invention has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the present invention. It is therefore to be understood that within the scope of the appended claims and their equivalents, the invention may be practiced otherwise than as specifically described herein.