DC offset cancellation method and device

Abstract

Disclosed is a DC offset cancellation (DCOC) method, comprising: after a receiver is electrified, acquiring a digital signal of an offset voltage at a circuit output port in the receiver, obtaining a digital control signal for controlling a DCOC output stage from the digital signal, and outputting, by the DCOC output stage, a current to a corresponding circuit of the receiver according to the digital control signal. Also disclosed is a DC offset cancellation device.

Claims

1. A direct current offset cancellation (DCOC) method, comprising: after a receiver is powered on, obtaining a digital signal of an offset voltage at a circuit output port of the receiver; obtaining a digital control signal for controlling a DCOC output stage from the digital signal; and outputting, by the DCOC output stage, a current to a corresponding circuit of the receiver according to the digital control signal.

2. The method according to claim 1, wherein obtaining the digital signal of the offset voltage at the circuit output port of the receiver comprises: measuring the offset voltage at the circuit output port of the receiver by a DCOC Analog-to-Digital Converter (ADC), wherein the offset voltage measured by the DCOC ADC is AV.sub.os, AV.sub.os=(n1+x)*(I.sub.amp*R.sub.2), where n1 is an integer, x is a decimal smaller than 1 and greater than −1, I.sub.amp is a unit step current of the DCOC output stage, and R.sub.2 is a resistance at a circuit output port of the receiver; and converting the measured offset voltage AV.sub.os into the digital signal DV.sub.os, ${\mathrm{DV}}_{\mathrm{os}}=\left(2^{11}-1\right)+\frac{{\mathrm{AV}}_{\mathrm{os}}}{V_{\mathrm{LSB}}}=2047+\left(n.Math..Math.1+1\right)*\frac{I_{\mathrm{amp}}*R_2}{V_{\mathrm{LSB}}},$ where V.sub.LSB is a Least Significant Bit (LSB) of the DCOC ADC.

3. The method according to claim 2, wherein obtaining the digital control signal for controlling the DCOC output stage from the digital signal comprises: performing, by a digital signal processor, a reverse operation on the digital signal DV.sub.os transmitted from the DCOC ADC and on a constant value (I.sub.amp* R.sub.2/V.sub.LSB) to obtain a binary value $X.Math..Math.1=n.Math..Math.1+1=\frac{{\mathrm{DV}}_{\mathrm{os}}-2047}{I_{\mathrm{amp}}*R_2/V_{\mathrm{LSB}}};$ and when control ports of the DCOC output stage are of 5-bit, adding, by the digital signal processor, the binary value and 011111 to obtain the digital control signal for controlling the DCOC output stage.

4. The method according to claim 1, wherein the receiver comprises a filter, a Programmable Gain Amplifier (PGA) and a main ADC; the DCOC output stage comprises a first DCOC output stage and a second DCOC output stage; the first DCOC output stage is used for current compensation of the filter; and the second DCOC output stage is used for current compensation of the PGA.

5. The method according to claim 4, wherein obtaining the digital signal of the offset voltage at the circuit output port of the receiver comprises: measuring, by the DCOC ADC, the offset voltage at an output port of the filter and performing the current compensation on the filter at the first DCOC output stage, and then measuring the offset voltage at an output port of the PGA and performing the current compensation on the PGA by the second DCOC output stage.

6. A direct current offset cancellation (DCOC) device, comprising: a DCOC Analog-to-Digital Converter (ADC), a digital signal processor and a DCOC output stage, wherein the DCOC ADC is configured, after a receiver is powered on, to obtain a digital signal of an offset voltage at a circuit output port of the receiver and to transmit the digital signal to the digital signal processor; the digital signal processor is configured to obtain a digital control signal for controlling the DCOC output stage from the digital signal, and to transmit the digital control signal to the DCOC output stage; and the DCOC output stage is configured to output a current to a corresponding circuit of the receiver according to the digital control signal.

7. The device according to claim 6, wherein the DCOC ADC is configured to measure that the offset voltage AVos at the circuit output port of the receiver, AV.sub.os=(n1+x)*(I.sub.amp*R.sub.2),where n1 is an integer, x is a decimal smaller than 1 and greater than -1, is a unit step current of the DCOC output stage, and R.sub.2 is a resistance at the circuit output port of the receiver; and to convert the measured offset voltage into the digital signal DVos, ${\mathrm{DV}}_{\mathrm{os}}=\left(2^{11}-1\right)+\frac{{\mathrm{AV}}_{\mathrm{os}}}{V_{\mathrm{LSB}}}=2047+\left(n.Math..Math.1+1\right)*\frac{I_{\mathrm{amp}}*R_2}{V_{\mathrm{LSB}}},$ where V.sub.LSB is a Least Significant Bit (LSB) of the DCOC ADC:

8. The device according to claim 7, wherein the digital signal processor is configured to perform a reverse operation on the digital signal DV.sub.os transmitted from the DCOC ADC and on a constant value (I.sub.amp*R.sub.2/V.sub.LSB) to obtain a binary value $X.Math..Math.1=n.Math..Math.1+1=\frac{{\mathrm{DV}}_{\mathrm{os}}-2047}{I_{\mathrm{amp}}*R_2/V_{\mathrm{LSB}}};$ and when control ports of the DCOC output stage are of 5-bit, to add the binary value and 011111 to obtain the digital control signal for controlling the DCOC output stage.

9. The device according to claim 6, wherein the receiver comprises a filter, a Programmable Gain Amplifier (PGA) and a main ADC; the DCOC output stage comprises a first DCOC output stage and a second DCOC output stage; the first DCOC output stage is used for current compensation of the filter; and the second DCOC output stage is used for current compensation of the PGA.

10. The device according to claim 9, wherein the DCOC ADC is configured to measure the offset voltage at an output port of the filter and perform the current compensation on the filter at the first DCOC output stage, and then to measure the offset voltage at an output port of the PGA and perform the current compensation on the PGA at the second DCOC output stage.

11. The device according to claim 10, wherein the first DCOC output stage comprises: the control port, a reference signal port and output ports; the control port receives a 5-bit digital control signal; the reference signal port receives a bandwidth control signal of a 3-bit filter so as to control an own unit step current; the bandwidth control signal of the filter is transmitted by the digital signal processor; the output ports output the current, which is obtained by performing digital-to-analog conversion on the digital control signal according to the unit step current, to an input terminal of the filter, thereby performing the current compensation on the filter.

12. The device according to claim 10, wherein the second DCOC output stage comprises: the control port, a reference signal port and output ports; the control port receives a 5-bit digital control signal; the reference signal port receives a gain control signal of a 4-bit PGA so as to control an own unit step current; the gain control signal of the PGA is transmitted by the digital signal processor; the output ports output the current, which is obtained by performing digital-to-analog conversion on the digital control signal according to the unit step current, to an input terminal of the PGA, thereby performing the current compensation on the PGA.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 is a flowchart of a DCOC method provided by an embodiment of the disclosure.

[0014] FIG. 2 is a schematic diagram showing a circuit connection of a DCOC method provided by an embodiment of the disclosure.

[0015] FIG. 3 is a schematic diagram showing a current compensation, performed by a first DCOC output stage, on a filter provided by an embodiment of the disclosure;

[0016] FIG. 4 is a structural diagram of a DCOC device provided by an embodiment of the disclosure.

DETAILED DESCRIPTION

[0017] The common DCOC methods may include an input offset storing method, an output offset storing method, a pre-amplification method, a negative feedback loop circuit and so on, and all have their own defects when being directly applied to a direct frequency conversion receiver. For example, the input offset storing method, the pre-amplification method and the output offset storing method need a support from a clock signal and requires the circuit, when the offset voltage is measured, to disconnect an input signal, which is not suitable for an application occasion of the receiver. In case of the negative feedback loop method, the circuit structure is very simple and has great advantages in power consumption and area. However, the working speed is relatively slow and the compensated output offset voltage range is limited. Particularly, for the offset of the circuit for receiving a calibration signal and the offset prior to the circuit, the negative feedback loop method may become helpless. The implementation schemes described above are based on a dynamic calibration structure and the convergence speed is relatively slow. Thus, in the direct frequency conversion receiver having a high gain, the disclosure adopts a static calibration DCOC circuit having a high speed and a simple current output.

[0018] In an embodiment of the disclosure, after a receiver is powered on, a digital signal of an offset voltage at a circuit output port of the receiver is obtained, a digital control signal for controlling a DCOC output stage is obtained from the digital signal, and the DCOC output stage outputs a current to a corresponding circuit of the receiver according to the digital control signal.

[0019] The disclosure will be further described in detail below in conjunction with accompanying drawings and specific embodiments.

[0020] An embodiment of the disclosure provides a DCOC method. As shown in FIG. 1. The method includes the following steps.

[0021] In step 101, after a receiver is powered on, a digital signal of an offset voltage at a circuit output port of the receiver is obtained.

[0022] Specifically, after the receiver is powered on, a receiver input port does not receive an input signal. The offset voltage at the circuit output port of the receiver is measured by means of a DCOC ADC. And the measured offset voltage is converted into the digital signal.

[0023] Here, it is assumed that the offset voltage, measured by the DCOC ADC, at the circuit output port of the receiver is AV.sub.os, AV.sub.os=(n1+x)*(I.sub.amp*R.sub.2), where n1 is an integer, x is a decimal smaller than 1 and greater than −1, I.sub.amp is a unit step current of a DCOC output stage, and R.sub.2 is a resistance at a circuit output port of the receiver. The measured offset voltage is converted into the digital signal DV.sub.os. And it is assumed that a Least Significant Bit (LSB) of the DCOC ADC is V.sub.LSB,

[00001]${\mathrm{DV}}_{\mathrm{os}}=\left(2^{11}-1\right)+\frac{{\mathrm{AV}}_{\mathrm{os}}}{V_{\mathrm{LSB}}}=2047+\left(n.Math..Math.1+1\right)*\frac{I_{\mathrm{amp}}*R_2}{V_{\mathrm{LSB}}}.$

[0024] In step 102, a digital control signal for controlling the DCOC output stage is obtained from the digital signal.

[0025] Specifically, the digital control signal for controlling the DCOC output stage is obtained by a digital signal processor performing a reverse operation on the digital signal. For example, for the offset voltage at the circuit output port of the receiver, as (I.sub.amp*R.sub.2A/.sub.LSB) in the DV.sub.os is a constant value, the digital signal processor only needs to perform the reverse operation on the digital signal DV.sub.OS transmitted from the DCOC ADC and on the constant value (I.sub.amp*R.sub.2/V.sub.LSB), such that a binary value

[00002]$X.Math..Math.1=n.Math..Math.1+1=\frac{{\mathrm{DV}}_{\mathrm{os}}-2047}{I_{\mathrm{amp}}*R_2/V_{\mathrm{LSB}}}$

can be obtained. When a control port of the DCOC output stage is of 5-bit, the digital signal processor adds the binary value and 011111 to obtain the digital control signal for controlling the DCOC output stage.

[0026] In step 103, the DCOC output stage outputs a current to a corresponding circuit of the receiver according to the digital control signal.

[0027] Specifically, the DCOC output stage performs digital-to-Analog conversion on the digital control signal according to an own unit step current to obtain the current, and outputs the current to the corresponding circuit of the receiver.

[0028] In the embodiment, as shown in FIG. 2, the receiver includes three stages, i.e. a filter, a Programmable Gain Amplifier (PGA) and a main ADC. The DCOC output stage includes a first DCOC output stage and a second DCOC output stage. The first DCOC output stage is used for current compensation of the filter, and the second DCOC output stage is used for current compensation of the PGA. The DCOC ADC measures the offset voltage at an output port of the filter and performs the current compensation on the filter at the first DCOC output stage, and then measures the offset voltage at an output port of the PGA and performs the current compensation on the PGA by the second DCOC output stage.

[0029] It is assumed that the offset voltage, measured by the DCOC ADC, at an output port of the filter in the receiver is AV.sub.os-filter, AV.sub.os-filter=(n1+x)*(I.sub.1-amp*R.sub.2-filer) , where n1 is an integer, x is a decimal smaller than 1 and greater than −1, I.sub.1-amp is a unit step current of the first DCOC output stage, and R.sub.2-filter is a resistance at an output terminal of the filter. The measured offset voltage is converted into the digital signal DV.sub.os-filter. It is assumed that the LSB of the ADC is V.sub.LSB, then

[00003]${\mathrm{DV}}_{\mathrm{os}.Math.\text{-}.Math.\mathrm{filter}}=\left(2^{11}-1\right)+\frac{{\mathrm{AV}}_{\mathrm{os}.Math.\text{-}.Math.\mathrm{filter}}}{V_{\mathrm{LSB}}}=2047+\left(n.Math..Math.1+1\right)*\frac{I_{1.Math.\text{-}.Math.\mathrm{amp}}*R_{2.Math.\text{-}.Math.\mathrm{filter}}}{V_{\mathrm{LSB}}}.$

[0030] As (I.sub.1-amp 2*R.sub.1-filter/V.sub.LSB) in the DV.sub.os-filter is a constant value, the digital signal processor only needs to perform the reverse operation on the digital signal DV.sub.os-filter transmitted from the DCOC ADC and on the constant value (I.sub.1-amp*R.sub.2-filter/V.sub.LSB), such that a binary value

[00004]$X.Math..Math.1=n.Math..Math.1+1=\frac{{\mathrm{DV}}_{\mathrm{os}.Math.\text{-}.Math.\mathrm{filter}}-2047}{I_{1.Math.\text{-}.Math.\mathrm{amp}}*R_{2.Math.\text{-}.Math.\mathrm{filter}}/V_{\mathrm{LSB}}}$

can be obtained. When a control port of the first DCOC output stage is of 5-bit, the digital signal processor adds the binary value and 011111 to obtain the digital control signal for controlling the first DCOC output stage.

[0031] The first DCOC output stage includes: the control port DCOC_CONTRL<5:0>, a reference signal port IREF_CNTRL<3:0> and output ports ip and in. The DCOC_CONTRL<5:0> receives a 5-bit digital control signal, and the IREF_CNTRL<3:022 receives a bandwidth control signal BW<3:0> of a 3-bit filter so as to control an own unit step current I.sub.1-amp. The bandwidth control signal BW<3:0> of the filter is transmitted by the digital signal processor. The output ports ip and in output the current, which is obtained by performing the digital-to-Analog conversion on the digital control signal according to the unit step current I.sub.1-amp, to an input terminal of the filter, thereby performing the current compensation on the filter and realizing the DCOC of the filter.

[0032] After the first DCOC output stage performs the current compensation on the filter, the DCOC ADC measures the offset voltage at the output port of the PGA.

[0033] It is assumed that the offset voltage, measured by the DCOC ADC, at an output port of the PGA in the receiver is AV.sub.os-PGA, AV.sub.os-PGA=(n1+x)* (I.sub.2-amp*R.sub.2-PGA), where n1 is an integer, x is a decimal smaller than 1 and greater than −1, I.sub.2-amp is a unit step current of the second DCOC output stage, and R.sub.2-PGA is a resistance at an output terminal of the PGA. The measured offset voltage is converted into the digital signal DV.sub.os-PGA. It is assumed that the LSB of the DCOC ADC is V.sub.LSG, then

[00005]${\mathrm{DV}}_{\mathrm{os}.Math.\text{-}.Math.\mathrm{PGA}}=\left(2^{11}-1\right)+\frac{{\mathrm{AV}}_{\mathrm{os}.Math.\text{-}.Math.\mathrm{PGA}}}{V_{\mathrm{LSB}}}=2047+\left(n.Math..Math.1+1\right)*\frac{I_{2.Math.\text{-}.Math.\mathrm{amp}}*R_{2.Math.\text{-}.Math.\mathrm{PGA}}}{V_{\mathrm{LSB}}}.$

[0034] As (I.sub.2-amp*R.sub.2-PGA/V.sub.LSB) in the DV.sub.os-PGA is a constant value, the digital signal processor only needs to perform the reverse operation on the digital signal DV.sub.os-PGA transmitted from the DCOC ADC and on the constant value (I.sub.2-amp*R.sub.2-PGA/V.sub.LSB), such that a binary value

[00006]$X.Math..Math.1=n.Math..Math.1+1=\frac{{\mathrm{DV}}_{\mathrm{os}.Math.\text{-}.Math.\mathrm{PGA}}-2047}{I_{2.Math.\text{-}.Math.\mathrm{amp}}*R_{2.Math.\text{-}.Math.\mathrm{PGA}}/V_{\mathrm{LSB}}}$

can be obtained. When a control port of the second DCOC output stage is of 5-bit, the digital signal processor adds the binary value and 011111 to obtain the digital control signal for controlling the second DCOC output stage.

[0035] The second DCOC output stage includes: the control port DCOC_CONTRL<5:0>, a reference signal port IREF_CNTRL<4:0> and output ports ip and in. The DCOC_CONTRL<5:0> receives a 5-bit digital control signal, and the IREF_CNTRL<4:0> receives a gain control signal <4:0> of a 4-bit PGA so as to control an own unit step current I.sub.2-amp. The gain control signal <4:0> of the PGA is transmitted by the digital signal processor. The output ports ip and in output the current, which is obtained by performing the digital-to-Analog conversion on the digital control signal according to the unit step current I.sub.2-amp, to an input terminal of the PGA, thereby performing the current compensation on the PGA and realizing the DCOC of the PGA.

[0036] With the current compensation of the first DCOC output stage on the filter as an example, a working principle of the compensation is described in detail. As shown in FIG. 3, the filter is simplified into two input terminal resistors R1, two output terminal resistors R2 and an operational amplifier OP1. When the DCOC_CNTRL<5:0> of the first DCOC output stage is equal to 011111, the currents output from the ip and in ports respectively are −0.5*I.sub.1-amp and +0.5*I.sub.1-amp, which are flowed to the output ports Von and Vop via the resistor R2. Because nodes net_p and net_n are located at an input port of the operational amplifier, the high-gain operational amplifier OP1 controls the two nodes at the same voltage. And meanwhile, common-mode voltages of the output ports Von and Vop are also confined at a set common-mode voltage Vcm. As a result, a differential output current will generate a differential voltage I.sub.1-amp*R2, which is a compensation voltage, at the output ports. Therefore, the differential voltage (Vop-Von) generated by the first DCOC output stage at the output ports is up to a maximum value +32*I.sub.1-amp*R2 when the DCOC_CNTRL<5:0> is equal to 111111, and up to a minimum value −32*I.sub.1-amp*R2 when the DCOC_CNTRE<5:0> is equal to 000000, and the step length is I.sub.1-amp*R2. At the first DCOC output stage, the amplitude of the I.sub.1-amp may be adjusted via the reference signal port IREF_CNTRL<3:0>. A resistance value of the R2 may vary according to a digital control word CHANGE<3:0> of the digital signal processor, so that the step length I.sub.1-amp*R2 varies. Thus, the I.sub.1-amp may be adjusted via the IREF_CNTRL<3:0>. When a change occurs in the resistor R2, the I.sub.1-amp changes reversely, thereby guaranteeing the step length I.sub.1-amp*R2 to be unchanged. Here, when the DCOC_CNTRL<5:0> is equal to n and the n is greater than 31, the voltage for compensating the filter is: (n−31)*I.sub.1-amp*R2. When the DCOC_CNTRL<5:0> is equal to the n and the n is smaller than 32, the voltage for compensating the filter is: (n−32)*I.sub.1-amp*R2.

[0037] Based upon the method above, the embodiment of the disclosure further provides a DCOC device. As shown in FIG. 4, the device includes: a DCOC ADC 41, a digital signal processor 42 and a DCOC output stage 43.

[0038] The DCOC ADC 41 is configured, after a receiver is powered on, to obtain a digital signal of an offset voltage at a circuit output port of the receiver and to transmit the digital signal to the digital signal processor 42.

[0039] The digital signal processor 42 is configured to obtain a digital control signal for controlling the DCOC output stage from the digital signal, and to transmit the digital control signal to the DCOC output stage 43.

[0040] The DCOC output stage 43 is configured to output a current to a corresponding circuit of the receiver according to the digital control signal.

[0041] The DCOC ADC 41 may be specifically configured to measure an offset voltage AV.sub.os at the circuit output port of the receiver, AV.sub.os=(n1+x)* (I.sub.amp*R.sub.2), where n1 is an integer, x is a decimal smaller than 1 and greater than −1, I.sub.amp is a unit step current of the DCOC output stage 43, and R.sub.2 is a resistance at a circuit output port of the receiver. And the DCOC ADC 41 may be specifically configured to convert the measured offset voltage into the digital signal DV.sub.os,

[00007]${\mathrm{DV}}_{\mathrm{os}}=\left(2^{11}-1\right)+\frac{{\mathrm{AV}}_{\mathrm{os}}}{V_{\mathrm{LSB}}}=2047+\left(n.Math..Math.1+1\right)*\frac{I_{\mathrm{amp}}*R_2}{V_{\mathrm{LSB}}},$

where V.sub.LSB is an LSB of the DCOC ADC 41.

[0042] The digital signal processor 42 is specifically configured to perform a reverse operation on the digital signal AV.sub.os transmitted from the DCOC ADC 41 and on a constant value (I.sub.amp*R.sub.2/V.sub.LSB) to obtain a binary value

[00008]$X.Math..Math.1=n.Math..Math.1+1=\frac{{\mathrm{DV}}_{\mathrm{os}}-2047}{I_{\mathrm{amp}}*R_2/V_{\mathrm{LSB}}}.$

When control ports of the DCOC output stage are of 5-bit, adds the binary value and 01111 to obtain the digital control signal for controlling the DCOC output stage.

[0043] The receiver includes three stages, i.e. a filter, a PGA and a main ADC. The DCOC output stage 43 includes a first DCOC output stage and a second DCOC output stage. The first DCOC output stage is used for current compensation of the filter, and the second DCOC output stage is used for current compensation of the PGA. The DCOC ADC 41 is specifically configured to measure the offset voltage at an output port of the filter and perform the current compensation on the filter at the first DCOC output stage, and then to measure the offset voltage at an output port of the PGA and perform the current compensation on the PGA by the second DCOC output stage.

[0044] The DCOC ADC 41 is specifically configured to measure an offset voltage AV.sub.os-filter at an output port of the filter, AV.sub.—os-filter=(n1+x)*(I.sub.1-amp*R.sub.2-filter), where n1 is an integer, x is a decimal smaller than 1 and greater than −1, I.sub.1-amp is a unit step current of the DCOC output stage, and R.sub.2-filter is a resistance at an output terminal of the filter. And the DCOC ADC 41 is specifically configured to convert the measured offset voltage into the digital signal DV.sub.os-filter,

[00009]${\mathrm{DV}}_{\mathrm{os}.Math.\text{-}.Math.\mathrm{filter}}=\left(2^{11}-1\right)+\frac{{\mathrm{AV}}_{\mathrm{os}.Math.\text{-}.Math.\mathrm{filter}}}{V_{\mathrm{LSB}}}=2047+\left(n.Math..Math.1+1\right)*\frac{I_{1.Math.\text{-}.Math.\mathrm{amp}}*R_{2.Math.\text{-}.Math.\mathrm{filter}}}{V_{\mathrm{LSB}}},$

where V.sub.LSB is an LSB of the DCOC ADC 41.

[0045] The digital signal processor 42 is specifically configured to perform a reverse operation on the digital signal DV.sub.os-filter transmitted from the DCOC ADC 41 and on a constant value (I.sub.1-amp*R.sub.2-filter/V.sub.LSB) to obtain a binary value

[00010]$X.Math..Math.1=n.Math..Math.1+1=\frac{{\mathrm{DV}}_{\mathrm{os}.Math.\text{-}.Math.\mathrm{filter}}-2047}{I_{1.Math.\text{-}.Math.\mathrm{amp}}*R_{2.Math.\text{-}.Math.\mathrm{filter}}/V_{\mathrm{LSB}}}.$

When control ports of the first DCOC output stage are of 5-bit, adds the binary value and 01111 to obtain the digital control signal for controlling the first DCOC output stage.

[0046] The first DCOC output stage includes: the control port DCOC_CONTRL<5:0>, a reference signal port IREF_CNTRL<3:0> and output ports ip and in. The DCOC_CONTRL<5:0> receives a 5-bit digital control signal, and the IREF_CNTRL<3:0> receives a bandwidth control signal BW<3:0> of a 3-bit filter so as to control an own unit step current I.sub.1-amp. The bandwidth control signal BW<3:0> of the filter is transmitted by the digital signal processor 42. The output ports ip and in output the current, which is obtained by performing the digital-to-Analog conversion on the digital control signal according to the unit step current I.sub.1-amp, to an input terminal of the filter, thereby performing the current compensation on the filter and realizing the DCOC of the filter.

[0047] The DCOC ADC 41 is specifically configured, after the first DCOC output stage performs the current compensation on the filter, to measure the offset voltage AV.sub.os-PGA at the output port of the PGA, AV.sub.os-PGA=(n1+x)*(I.sub.2-amp*R.sub.2-PGA), where n1 is an integer, x is a decimal smaller than 1 and greater than −1, I.sub.2-amp is a unit step current of the second DCOC output stage, and R.sub.2-PGA, is a resistance at an output terminal of the PGA. And the DCOC ADC 41 is specifically configured to convert the measured offset voltage into the digital signal DV.sub.os-PGA,

[00011]${\mathrm{DV}}_{\mathrm{os}.Math.\text{-}.Math.\mathrm{PGA}}=\left(2^{11}-1\right)+\frac{{\mathrm{AV}}_{\mathrm{os}.Math.\text{-}.Math.\mathrm{PGA}}}{V_{\mathrm{LSB}}}=2047+\left(n.Math..Math.1+1\right)*\frac{I_{2.Math.\text{-}.Math.\mathrm{amp}}*R_{2.Math.\text{-}.Math.\mathrm{PGA}}}{V_{\mathrm{LSB}}},$

where V.sub.LSB is an LSB of the DCOC ADC 41.

[0048] The digital signal processor 42 is further configured to perform a reverse operation on the digital signal DV.sub.os-PGA transmitted from the DCOC ADC 41 and on a constant value (I.sub.2-amp*R.sub.2-PGA/V.sub.LSB) to obtain a binary value

[00012]$X.Math..Math.1=n.Math..Math.1+1=\frac{{\mathrm{DV}}_{\mathrm{os}.Math.\text{-}.Math.\mathrm{PGA}}-2047}{I_{2.Math.\text{-}.Math.\mathrm{amp}}*R_{2.Math.\text{-}.Math.\mathrm{PGA}}/V_{\mathrm{LSB}}}.$

The digital signal processor 42 is further configured to, when control ports of the second DCOC output stage are of 5-bit, add the binary value and 01111 to obtain the digital control signal for controlling the second DCOC output stage.

[0049] The second DCOC output stage includes: the control port DCOC_CONTRL<5:0>, a reference signal port IREF_CNTRL<4:0> and output ports ip and in. The DCOC_CONTRL<5:0> receives a 5-bit digital control signal, and the IREF_CNTRL<4:0> receives a gain control signal <4:0> of a 4-bit PGA so as to control an own unit step current I.sub.2-amp. The gain control signal <4:0> of the PGA is transmitted by the digital signal processor 42. The output ports ip and in output the current, which is obtained by performing the digital-to-Analog conversion on the digital control signal according to the unit step current I.sub.2-amp, to an input terminal of the PGA, thereby performing the current compensation on the PGA and realizing the DCOC of the PGA.

[0050] The above descriptions are only preferred embodiments of the disclosure and are not intended to limit the scope of protection of the disclosure. Any modifications, substitutions, improvements and the like made without departing from the spirit and the principle of the disclosure should fall within the protection scope of the disclosure.

INDUSTRIAL APPLICABILITY

[0051] According to the embodiments of the disclosure, the digital control signal for controlling the DCOC output stage is obtained by the digital signal of the offset voltage at the circuit output port of the receiver, so that the DCOC output stage outputs the corresponding current to the corresponding circuit of the receiver. In such way, the direct current offset voltage of the receiver can be cancelled. Because of the static calibration mode of the disclosure, the circuit structure is simpler and more stable, and the convergence speed is faster, without taking the circuit stability into consideration.