LOAD ADAPTABLE BOOST DC-DC POWER CONVERTER

Abstract

A boost DC-DC power converter comprising a semiconductor switch arrangement comprising a plurality of series connected semiconductor switches. A first capacitor is connected between a first intermediate node of a first leg of the semiconductor switch arrangement and a second intermediate node of a second leg of the semiconductor switch arrangement. A control circuit is coupled to respective control terminals of the plurality of semiconductor switches. A load sensor is configured to detect a load current and/or a load voltage of a load circuit connectable to at least a first DC output voltage of the DC-DC power converter. The control circuit being further configured to adjusting one or more operational parameters of the boost DC-DC power converter based on the detected load current and/or load voltage.

Claims

1. A boost DC-DC power converter comprising a semiconductor switch arrangement comprising: a first leg comprising N series connected semiconductor switches, where N is an integer larger than 1, where a first end of the first leg is connected to a DC reference potential, a second end of the first leg is connected to a boost node, a second leg comprising N series connected semiconductor switches , a first end of the second leg being connected to the boost node and a second end of the second leg being connected to a first output node for supplying a first DC output voltage; an inductor having a first end connected to the boost node and a second end connectable to a DC input voltage supply, a first capacitor connected between a first intermediate node of the first leg and a second intermediate node of the second leg, a second capacitor connected between the DC reference potential and the first output node; a load sensor configured to detect at least one of a load current and a load voltage of a load circuit; said load circuit being connectable to at least the first DC output voltage; a control circuit connected to respective control terminals of the semiconductor switches of the semiconductor switch arrangement, the control circuit being further configured to: adjusting one or more operational parameters of the boost DC-DC power converter based on the at least one of the detected load current and load voltage.

2. A boost DC-DC power converter according to claim 1, wherein the one or more operational parameters comprises at least one of: a switching frequency of the semiconductor switches of the semiconductor switch arrangement, a duty cycle, D, of the control signals of the semiconductor switches of the semiconductor switch arrangement; a voltage level of the control signals of the semiconductor switches of the semiconductor switch arrangement; an operational regime of the semiconductor switch arrangement, wherein said operational regime comprises a predetermined set of converter states; and a parameter of a feedback regulating loop controlling a DC voltage level of at least the first DC output voltage.

3. A boost DC-DC power converter according to claim 2, wherein the control circuit is configured to: select an operational regime of the semiconductor switch arrangement wherein the N series connected semiconductor switches of the second leg are placed in respective conducting states and the residual switches of the semiconductor switch arrangement arranged in respective non-conducting states, thereby energizing the first DC output voltage from the DC input voltage supply through the second leg.

4. A boost DC-DC power converter according to claim 1, wherein the semiconductor switch arrangement further comprises: a first further semiconductor switch for selectively coupling or decoupling a second output node to a first end of the first capacitor, for supplying a second DC output voltage via a second output node, a second further semiconductor switch for selectively coupling or decoupling the second output node or, if present a third output node, to the second end of the first capacitor.

5. A boost DC-DC power converter according to claim 1, wherein the load current comprises a DC or AC current flowing through a power supply line of the load circuit and the load voltage comprises a DC or AC voltage of the power supply line of the load circuit.

6. A boost DC-DC power converter according to claim 1, wherein the load current comprises a DC or AC current flowing through at least the first DC output voltage; and the load voltage comprises a DC or AC voltage of at least the first DC output voltage.

7. A boost DC-DC power converter according to claim 2, wherein the predetermined set of converter states of at least one operational regime comprises: a first charge configuration for charging the inductor through a first current path extending from the boost node to the DC reference potential; and a first discharge configuration for discharging the inductor through a second current path extending from the boost node either directly through the second leg to the first output node or through the first capacitor and at least one semiconductor switch of the first leg and one semiconductor switch of the second leg.

8. A boost DC-DC power converter according to claim 7, wherein the control circuit is further configured to set the duty cycle of each of the control signals of the semiconductor switches of the semiconductor switch arrangement to 0.5.

9. A boost DC-DC power converter according to claim 7, wherein the control circuit is further configured to: detecting load power to the load circuit based at least on the detected load current; and adjusting the switching frequency of the semiconductor switch arrangement in accordance with the detected load power.

10. A boost DC-DC power converter according to claim 9, wherein the control circuit is further configured to: selecting a first switching frequency if the load power is smaller than a first power threshold; and selecting a second switching frequency if the load power exceeds the first power threshold, wherein the second switching frequency is higher than the first switching frequency.

11. A boost DC-DC power converter according to claim 2, wherein the control circuit is further configured to: detecting load power to the load circuit based at least on the detected load current; and adjusting a loop gain of the feedback regulation loop in accordance with the detected load power.

12. A boost DC-DC power converter according to claim 11, wherein the control circuit is configured to: selecting a first loop gain if the detected load power is below a first power threshold; selecting a second loop gain if the detected load power exceeds the first power threshold; wherein the first loop gain is smaller than the second loop gain.

13. An audio amplification system comprising a boost DC-DC power converter in accordance with claim 1 and an audio power amplifier; said audio power amplifier comprising at least a first DC supply voltage rail connected to the DC reference potential of the boost DC-DC power converter and a second DC supply voltage rail coupled the first DC output voltage of the boost DC-DC power converter.

14. An audio amplification system according to claim 13, wherein the audio power amplifier comprises a class D audio amplifier such as multilevel class D audio amplifier.

15. An audio amplification system according to claim 14, wherein the class D audio amplifier comprises: audio level detector configured to determine a level of an audio input signal, or an audio signal derived therefrom, of the class D audio amplifier; an audio level indicator configured to indicate the determined level of the audio input signal or audio signal derived therefrom.

16. A boost DC-DC power converter according to claim 3, wherein the predetermined set of converter states of at least one operational regime comprises: a first charge configuration for charging the inductor through a first current path extending from the boost node to the DC reference potential; and a first discharge configuration for discharging the inductor through a second current path extending from the boost node either directly through the second leg to the first output node or through the first capacitor and at least one semiconductor switch of the first leg and one semiconductor switch of the second leg.

17. A boost DC-DC power converter according to claim 4, wherein the predetermined set of converter states of at least one operational regime comprises: a first charge configuration for charging the inductor through a first current path extending from the boost node to the DC reference potential; and a first discharge configuration for discharging the inductor through a second current path extending from the boost node either directly through the second leg to the first output node or through the first capacitor and at least one semiconductor switch of the first leg and one semiconductor switch of the second leg.

18. A boost DC-DC power converter according to claim 5, wherein the predetermined set of converter states of at least one operational regime comprises: a first charge configuration for charging the inductor through a first current path extending from the boost node to the DC reference potential; and a first discharge configuration for discharging the inductor through a second current path extending from the boost node either directly through the second leg to the first output node or through the first capacitor and at least one semiconductor switch of the first leg and one semiconductor switch of the second leg.

19. A boost DC-DC power converter according to claim 6, wherein the predetermined set of converter states of at least one operational regime comprises: a first charge configuration for charging the inductor through a first current path extending from the boost node to the DC reference potential; and a first discharge configuration for discharging the inductor through a second current path extending from the boost node either directly through the second leg to the first output node or through the first capacitor and at least one semiconductor switch of the first leg and one semiconductor switch of the second leg.

20. A boost DC-DC power converter according to claim 8, wherein the control circuit is further configured to: detecting load power to the load circuit based at least on the detected load current; and adjusting the switching frequency of the semiconductor switch arrangement in accordance with the detected load power.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In the following embodiments of the invention are described with reference to the accompanying drawings, in which:

[0030] FIG. 1 illustrates a dual-output boost DC-DC power converter in accordance with a first embodiment of the invention;

[0031] FIG. 2 illustrates a transistor level block diagram of a semiconductor switch arrangement of the dual-output boost DC-DC power converter circuit depicted on FIG. 1;

[0032] FIG. 3 illustrates schematically a control circuit of the dual-output boost DC-DC power converter depicted on FIG. 1;

[0033] FIG. 4A illustrates exemplary gate control signals of the semiconductor switch arrangement provided by the control circuit of FIG. 3 for a first set of operational parameters of the dual-output boost DC-DC power converter;

[0034] FIG. 4B illustrates exemplary gate control signals of the semiconductor switch arrangement provided by the control circuit of FIG. 3 for a second set of operational parameters of the dual-output boost DC-DC power converter;

[0035] FIG. 4C illustrates exemplary gate control signals of the semiconductor switch arrangement provided by the control circuit of FIG. 3 for a third set of operational parameters of the dual-output boost DC-DC power converter;

[0036] FIG. 4D illustrates exemplary gate control signals of the semiconductor switch arrangement provided by the control circuit of FIG. 3 for a fourth set of operational parameters of the dual-output boost DC-DC power converter;

[0037] FIG. 5 is a simplified block diagram of an exemplary single-output boost DC-DC power converter in accordance with a second embodiment of the invention,

[0038] FIG. 6 is a block diagram of an audio amplification system comprising a dual-output boost DC-DC power converter in accordance with various embodiments of the invention connected to a load circuit comprising a Class D audio amplifier; and

[0039] FIG. 7 shows a graph depicting computed duty cycle D versus boost ratio of an exemplary dual-output boost DC-DC power converter.

DETAILED DESCRIPTION OF THE INVENTION

[0040] In the following various exemplary embodiments of the boost DC-DC power converters are described with reference to the appended drawings. The skilled person will understand that the accompanying drawings are schematic and simplified for clarity and therefore merely show details which are essential to the understanding of the invention while other details have been left out. Like reference numerals refer to like elements throughout. Like elements will, thus, not necessarily be described in detail with respect to each figure.

[0041] FIG. 1 shows a block diagram of a dual-output boost DC-DC power converter 100 in accordance with a first embodiment of the invention. The dual-output boost DC-DC power converter 100 or power converter 100 comprises a converter circuit 101 and a control circuit 102 for controlling the operation of the power converter 100, in particular for adjusting one or more operational parameters of the power converter 100 based on a detected load current and/or detected load voltage as described in additional detail below. The converter circuit 101 comprises a semiconductor switch arrangement coupled to a floating charge capacitor as discussed in further detail with reference to FIG. 2 below. The power converter 100 is connected to an input power or input voltage supply 105 (Vdd) which supplies energy for the power converter 100. The power converter 100 is configured to generate separate first and second DC output voltages of different DC voltage levels, Pvdd and ½ Pvdd, respectively, in the present embodiment. The skilled person will understand that other embodiments of the power converter may be configured to generate merely a single DC output voltage, e.g. Pvdd, or more than two different DC output voltages in accordance with application requirements. A first smoothing capacitor 114 is preferably connected to the first DC output voltage and a second smoothing capacitor 113 is preferably connected to the second DC output voltage. The voltage level of the second DC output voltage is approximately on-half of the voltage level of the first DC output voltage as indicated by the factor 0.5. This feature is a noteworthy characteristic of the power converter circuit 100 enabled by the hybrid converter topology mixing operational characteristics of charge pumps and switched mode boost DC-DC power converters leading to a versatile and efficient power converter topology as explained in further detail below. The present embodiment of power converter 100 comprises an optional and programmable feedback voltage regulation loop (not shown) via the control circuit 102. The programmable feedback voltage regulation loop may in some embodiments of the invention be switched off or deactivated when certain values of the operational parameters of the power converter 100 are complied with. However, in its active state the programmable feedback voltage regulation loop provides accurate setting and continuous tracking of the respective DC output voltage levels of the first and second DC output voltages Pvdd and ½ Pvdd despite variations of the DC input voltage, load, temperature and circuit component values.

[0042] The power converter circuit 100 additionally comprises an inductor 111 having a first end connected to a boost node 122 and a second end connectable to a DC input voltage supply 105 (Vdd). The latter is schematically illustrated as a battery stack or package, but may comprise numerous types of DC voltage supplies available in an apparatus comprising the power converter 100 circuit.

[0043] The power converter circuit 100 is connected to a load circuit 115 via two different supply paths such that load voltage and load current, Ivdd, is supplied to the load circuit 115 as needed. The first DC output voltage (Pvdd) is connected to a first DC supply line or terminal of the load circuit 115 and the second DC output voltage (½ Pvdd) is connected to a second DC supply line or terminal of the load circuit 115. The load circuit 115 may comprise a class D audio power amplifier (not shown)—for example a multilevel class D audio amplifier, as discussed in further detail below with reference to FIG. 6. A DC voltage of the input voltage supply 105 may lie between 1.5 V and 5.0 such as about 3.6 V.

[0044] The control circuit 102 is connected to respective gate or control terminals of the semiconductor switches of the semiconductor switch arrangement of the converter circuit 101 as discussed in detail below with reference to FIG. 2. The control circuit 102 is configured to adjusting one or more operational parameters of the power converter 100 based on a detected load current or detected load voltage or a combination of both, e.g. representing load power. In the present embodiment, the control circuit 102 senses the load current Ivdd by sensing the DC and AC current flowing through the power supply line or wire 117 of the first DC output voltage (Pvdd). The control circuit 102 furthermore senses the load voltage by sensing at least the first DC output voltage (Pvdd). The control circuit 102 may comprise a suitable sense circuit for sensing the load voltage and load current Pvdd, Ivdd. This sense circuit may comprise a current sensor, such as a small resistance, inserted in the power supply line or wire 117. The sensed or detected load voltage and load current Pvdd, Ivdd may be applied to suitable inputs of the control circuit 102. In some embodiments, the detected load voltage and load current Pvdd, Ivdd may be represented in digital format, or be converted to digital format, inside the control circuit 102 by an A/D converter and suitable conditioning circuitry (not shown). The control circuit 102 may furthermore be configured to sense the DC and AC current flowing through the power supply line or wire 119, applying the second DC output voltage (Pvdd) to the load circuit 115, and the second DC output voltage in a similar manner.

[0045] In one embodiment of the power converter circuit 100, the control circuit 102 is configured to adjusting several operational parameters of the power converter based on at least one of the detected load current, voltage or power. The operational parameters comprise at least a switching frequency of the semiconductor switch arrangement and a duty cycle D of the control signals Q0-Q5 of the semiconductor switch arrangement. The operational parameters may additionally comprise a parameter of the feedback voltage regulating loop such as a loop gain or state, e.g. activated/on or deactivated/off. The one or more operational parameters may additionally comprise an operational regime of the semiconductor switch arrangement wherein said operational regime comprises a predetermined set of converter states. Various operational regimes of the semiconductor switch arrangement are discussed in further detail below.

[0046] The control circuit 102 is capable of adapting or tailoring power loss, or conversion efficiency, of the power converter 100 to the power consumption of the load circuit 115 by adaptively adjusting values of the one or more operational parameters of the power converter 100 based on the detected load current, voltage or power. The control circuit 102 may for example be configured to select a relatively low switching frequency of the semiconductor switch arrangement under conditions where the load circuit 115 draws a relatively small amount of power from the first DC output voltage and thereby reduce power losses incurred by the switching activity of certain components of the converter circuit 101. These components may comprise the semiconductor switches, capacitors and the inductor 111. In the opposite situation, where the load circuit 115 draws a relatively large amount of power from the first DC output voltage, the control circuit 102 may in response select a relatively high switching frequency of the semiconductor switch arrangement. The relatively high switching frequency increases the output current, voltage and power delivery capability of the power converter circuit 100. Hence, enabling the power converter 100 to meet the power consumption demands of the load circuit 115. Even if the high switching frequency leads to an increase of power losses of the power converter 100 these power losses may still represent a small fraction of the total power delivered to the load circuit and therefore insignificant from a system's perspective.

[0047] FIG. 2 illustrates an exemplary transistor level schematic of the converter circuit 101 depicted in a simplified schematic format on FIG. 1. The exemplary converter circuit 101 comprises a semiconductor switch arrangement comprising six controllable semiconductor switches Q1-Q5. Each of the controllable semiconductor switches Q0-Q5 may for example comprise a NMOS FET and/or PMOS FET transistor as indicated in the figure. The switches Q0, Q1 and Q4 are preferably n-type switches, and switches Q2, Q3 and Q5 are preferably p-type switches, for instance PMOSFETs. The selection of switch type is a matter of design and is something that would advantageously be selected in such a way as to optimize the circuit for its intended application, for example in terms of DC voltage levels and voltage polarities. The semiconductor switch arrangement comprises a first leg comprising the first and second semiconductor switches Q0, Q1 connected in series or cascade between a DC reference potential, i.e. ground/GND in the present embodiment but may be a negative DC supply rail in other embodiments, and a boost node 222. The semiconductor switch arrangement further comprises a second leg comprising third and fourth semiconductor switches Q2, Q3 connected in series or cascade between the boost node 222 and the first DC output voltage Pvdd. The first leg comprises a first intermediate node 221 placed at the junction node of the first and second semiconductor switches Q0, Q1 and the second leg likewise comprises a second intermediate node 223 placed at the junction or coupling node of the third and fourth semiconductor switches Q2, Q3. The boost inductor (L1) 111 has a first end coupled to a DC input voltage supply Vdd and a second end coupled to the boost node 222. A flying or pump capacitor C2 is coupled between the first intermediate node 221 and second intermediate node 223 such that a first end of C2 is coupled to the first intermediate node 221 and a second end coupled to the second intermediate node 223. As discussed in further detail below, the semiconductor switch arrangement comprises a first further semiconductor switch Q4, i.e. fifth switch of the present embodiment, is configured to selectively connecting and disconnecting a second output node 225, supplying the second DC output voltage ½ Pvdd, to the first end of the first capacitor and hence to the first intermediate node 221. A second further semiconductor switch Q5, i.e. sixth switch of the present embodiment, is configured for selectively connecting and disconnecting the second output node 225 or, if present, a third output node 526 to the second end of the first capacitor 212 and hence to the second intermediate node 223.

[0048] FIG. 3 illustrates the previously-discussed control circuit 102 configured to adaptively adjusting the one or more operational parameters of the power converter 100 based on the detected load current, voltage or power. The control circuit 102 may be configured for switching the dual-output boost DC-DC power converter 100 between first, second and third converter states in one operational regime. The control circuit 102 comprises a pulse-width modulator 301 and a gate driver schematically shown as element 320. More details about the control circuit 102 are discussed later in the specification. The control circuit 102 is configured to generate respective gate control signals QC1-QC5 for the controllable semiconductor switches Q0-Q5 of the semiconductor switch arrangement. This feature may be utilized to control at least the switching frequency of the semiconductor switch arrangement and a duty cycle, D, of the control signals of the semiconductor switch arrangement. The feature may also be utilized for controlling state switching between different converter states etc.

[0049] The control circuit 102 is configured to selectively operate the dual-output boost DC-DC power converter 100 in at least two different operational regimes, regime 1 and regime 2, depending on the desired voltage level of the first DC output voltage. Each operational regime comprises a particular set of converter states and an associated state switching scheme. The converter state switching is controlled by the control circuit 102 such that the respective target voltage levels of the first and second DC output voltages Pvdd and ½ Pvdd are reached and maintained during operation of the power converter 100.

[0050] The operation regime 1 may selected by the control circuit 102 where the DC voltage level of the first DC output voltage, Pvdd, is smaller than 2 times the DC voltage level of the input voltage supply, Vdd. The operation regime 2 may selected by the control circuit 102 where the target or desired voltage of the first DC output voltage is larger than two times the DC input voltage, i.e. Pvdd>2*Vdd).

[0051] The detailed implementation and benefits of these different operation regimes of the power converter 100, their associated sets of converter states and state switching schemes are described in detail in the applicant's co-pending application PCT/EP2015/072124. Hence, these explanations will not be repeated in every detail here.

[0052] FIGS. 4A-4D illustrates respective gate control signals QC1-QC5 of the first to sixth controllable semiconductor switches Q0-Q5 of the converter circuit 101 for four different sets of operational parameters of the power converter 100 selected based on detected load currents and/or detected load voltages. FIG. 4A illustrates operation regime 1 of the power converter (the case Pvdd<2*Vdd). The respective gate control signals QC1-QC5 of switches Q0-Q5 in FIGS. 4A-4D are depicted as “on” and “off”, meaning that the associated switch is in a conducting state where the gate control signal is logic high or “1” and in a non-conducting state where the gate control signal is logic low or “0”. Different switch types require different polarities and levels of the gate control signals QC1-QC5 in order to be “on” or “off”, and thus the actual gate voltages are different for different switch types. In practical implementations of the control circuit, the illustrated logical gate control signals QC1-QC5 must accordingly be translated into gate control voltages or potentials that realize the desired on and off states. FIGS. 4A-4D are additionally illustrating the corresponding signal waveforms at the boost node Vsw (122) and at the first and second terminals Vcf_p and Vcf_n (221, 223) of the floating capacitor C2 (212). Finally, first, second and third converter states 401,402a, 403 of operation regime 1 are indicated above the signal waveforms of FIGS. 4A-4D. The control circuit 102 is responsible for selecting the four different sets of operational parameters and generating the corresponding control signal waveforms illustrated schematically on FIGS. 4A-4D in response to detected changes of the load current and/or load voltage.

[0053] The control circuit 102 comprises a voltage controller 302a configured for comparing a target DC voltage, Vref, and an instantaneous voltage of the first DC output voltage Pvdd. When the first DC output voltage drops below Vref, the control circuit 102 adjusts the modulation signal Vmod accordingly to ensure charging of the capacitors C2, C3 and C4 and the boost inductor L1. In the exemplary embodiment, the control circuit 102 provides, via a voltage controller 302, a modulation signal Vmod representing a difference between the first DC output voltage Pvdd of the power converter circuit and a DC target voltage Vref. The first DC output voltage Pvdd is applied to a first input 313 of the voltage controller 302 and the DC target voltage Vref to a second input 314 of the voltage controller 302. The generated modulation signal Vmod is applied to a pair of comparators 311 and 312. These comparators 311 and 312 are configured to compare the modulation signal Vmod with respective complementary ramp signals 304a and 304b to provide two pulse-width modulation signals to the gate driver 320. The gate driver 320 in turn generates the previously discussed gate control signals QC1-QC5 for the semiconductor switches Q0-Q5 which signals are used for switching the converter circuit between the first, second and third converter states via the semiconductor switches Q0-Q5. The present embodiment thus uses two PWM phases for providing the required gate control signals QC1-QC5. The control circuit 102 may comprise a triangular waveform circuit 317 configured for generating the complementary ramp signals 304a and 304b where the modulation frequency is set by a programmable square wave generator 315. The control circuit 102 comprises a controller 325 that inter alia is responsive to the previously discussed control inputs comprising the load current signal or indicator Ivdd and a current value of the duty cycle, D-PWM, of the control signals. The controller 325 may comprise an appropriately configured digital state machine or a programmable microprocessor executing a control program. The controller 325 is configured to adjust a modulation frequency of each of the ramp signals 304a, 304b such that the switching frequency f0 of each of the individual switches (Q0-Q5) of the semiconductor switch arrangement is adjusted in a corresponding manner via the previously discussed gate control signals QC1-QC5 of the semiconductor switches Q0-Q5. The controller 325 may adjust the switching frequency f0 by adjusting a frequency of the programmable square wave generator 315 of the control circuit 102 connected to an input of the triangular waveform circuit 317.

[0054] The skilled person will understand that the voltage controller 302 may comprise the previously discussed feedback voltage regulation loop configured for adjusting the duty cycle D of the gate control signals QC1-QC5 of the semiconductor switches Q0-Q5 up/down in an effort to maintain the voltage of Pvdd at the DC target voltage Vref. In addition, the switching frequency of the power converter 100 is independently adjustable through adjustment of the previously discussed gate control signals QC1-QC5 of the semiconductor switches Q0-Q5.

[0055] Hence, one or more of the switching frequency, the duty cycle of the switch control signals and the parameters of the feedback voltage regulation loop may be adjusted or adapted to optimize the operation of the power converter 100 to meet certain performance constraints—for example the power consumption demands of the load circuit 115. The power consumption demands of the load circuit 115 may be represented by the load current signal Ivdd or a combination of the load current signal Ivdd and the sensed voltage of Pvdd.

[0056] In one embodiment of the power converter 100, the control circuit 102 is configured to adjusting the switching frequency f0 between a lower frequency of 10 kHz or less and an upper frequency of at least 2 MHz—for example 5 or 10 MHz.

[0057] In one embodiment of the power converter 100, the control circuit 102 is configured to select a first switching frequency fl of the semiconductor switches Q0-Q5 of the converter circuit 101 if the load power is smaller than a first power threshold and selecting a second switching frequency f2 if the load power exceeds the first power threshold—wherein f2 is higher than f1 for example at least two times higher or at least 5 times higher. If the load circuit comprises a class D audio power amplifier, the first power threshold may be situated somewhere between 0.01 W and 0.25 W for example around 0.1 W which indicates a near-idle operation of the class D power amplifier. The control circuit 102 may for example set the first switching frequency f1 of each of the semiconductor switches Q0-Q5 to less than 25 kHz, for example 10 kHz as mentioned above, for load power levels situated below the first power threshold. The switching frequency is indicated at the Vcn_n signal waveform by a corresponding switching cycle period Tsw. The control circuit 102 may set the second switching frequency f2 to a frequency above 100 kHz or above 250 kHz. FIG. 4A illustrates schematically the respective gate control signal waveforms of the first to sixth controllable semiconductor switches Q0-Q5 of the converter circuit 101 for the first set of operational parameters of the power converter. The first set of operational parameters may be selected by the control circuit 102 if the power drawn by the load circuit 115 lies below the first power threshold. As illustrated on FIG. 4A, the duty cycle of the control signals applied to the gates of the semiconductor switches Q0-Q5 is close to zero for example below 0.1 or below 0.05. However, each time Q1 is turned on, the boost inductor 111 is charged to the second output voltage ½ Pvdd through Q4 in state 401. Thereafter, the first DC output voltage Pvdd is charged from the DC input voltage Vdd through a current path through the boost inductor 111 and Q2 and Q3 such that the first output voltage Pvdd is charged to a voltage level approximately equal to the level of the DC input voltage Vdd, i.e. a boost ratio of one.

[0058] FIG. 4B illustrates the respective gate control signals QC1-QC5 of the first to sixth controllable semiconductor switches Q0-Q5 of the converter circuit 101 for the second set of operational parameters of the power converter selected by control circuit 102 where the power drawn by the load circuit exceeds the first power threshold but remains relatively low. As illustrated on FIG. 4B, the switching frequency has been increased by the control circuit 102 to the second switching frequency f2 discussed above. The control circuit 102 has simultaneously increased the duty cycle D of each of the control signals from about zero to substantially 0.5. The latter setting of the duty cycle D forces the first DC output voltage Pvdd to approximately two times the DC input voltage Vdd. This feature is particularly advantageous for embodiments of the boost DC-DC power converter which possess an uneven number of separate DC output voltages because D=0.5 for these converter embodiments or topologies lead to a cancellation of ripple current in the boost inductor 111. The cancellation of the ripple current in the boost inductor 111 in turn leads to a very small power loss in the boost power converter 100 because the latter largely acts as a charge pump by the switching action of the floating capacitor 212. The floating capacitor 212 may be charged through the boost inductor 111 in one converter state and dump its accumulated charge to the smoothing capacitor 114, connected to the first DC output voltage, in another converter state. Hence, the boost operation of the power converter 100 is largely disabled for this 0.5 setting of the operational parameter duty cycle D. In some embodiments, the control circuit 102 may be configured to maintain D=0.5 setting throughout a relatively large range of load powers. The control circuit 102 may for example select and maintain the D=0.5 setting for low power and medium power consumption of the load circuit 115 and gradually, or stepwise, increase the switching frequency of the semiconductor switch arrangement from the first frequency, e.g. 10 kHz, or the second frequency f2 or even higher frequency to meet increasing load power demands. This is schematically illustrated by the gate control signals QC1-QC5 of the first to sixth controllable semiconductor switches Q0-Q5 of the converter circuit 101 depicted on FIG. 4C for the third set of operational parameters of the power converter selected by the control circuit 102. The control circuit 102 has increased the switching frequency of the semiconductor switch arrangement from second frequency f2 to a higher frequency for example at least two times higher. However, the duty cycle D=0.5 has been maintained to keep benefiting from the previously discussed advantages of this D setting. The skilled person will appreciate that the increase of switching frequency of the semiconductor switch arrangement from the second to the third set of operational parameters improves the power delivery capability of the power converter 100, because the output impedance of a charge pump circuit varies inversely with the switching frequency. Hence, the increasing switching frequency of the semiconductor switch arrangement for increasing load power demands improves the power delivery capability of the present power converter circuit in an advantageous manner.

[0059] FIG. 4D illustrates the respective gate control signals QC1-QC5 of the first to sixth controllable semiconductor switches Q0-Q5 of the converter circuit 101 for the fourth set of operational parameters of the power converter 100 selected by the control circuit 102. The fourth set of operational parameters is preferably selected to reach the maximum power deliver capability of the power converter 100 as per the requirement of the load circuit 115. The control circuit 102 may be configured to select the fourth set of operational parameters in response to the detected load power or current reaches more than 50% or 75% of the maximum power or current capability. As schematically illustrated by the signal waveforms of FIG. 4D, the switching frequency has been increased by the control circuit 102 relative to the switching frequency selected for the third set of operational parameters discussed above. The control circuit 102 has in addition increased the duty cycle D of each of the control signals from substantially 0.5 to about 0.8. The latter setting of the duty cycle D forces the first DC output voltage Pvdd to a higher level than two times the DC input voltage Vdd by virtue of the boost operation of the boost coil 111. The relationship between the duty cycle D and the level of the first DC output voltage Pvdd, expressed as a boost ratio relative to the DC input voltage Vdd, is depicted on curve 705 of FIG. 7A for the power converter 100. A duty cycle D=0.8 generates a level or voltage of the first DC output voltage Pvdd which approximately 5 times the level of the DC input voltage Vdd as evident from curve 705.

[0060] Hence, the control circuit 102 of the present embodiment of the power converter 100 is configured to independently adjust two different operational parameters, the duty cycle D and the switching frequency f0 in response to the switching from one set of operational parameters to another in response to changing load power demands. The skilled person will appreciate that the control circuit 102 of other embodiments of the present power converter may be configured to adjust merely a single operational parameter in response to changing load power demands while yet other embodiments may be configured to adjust three or more operational parameters in response to the changing load power demands.

[0061] The first operational parameter may be the switching frequency f0 and the second operational parameter may comprise the previously discussed parameter or state of the feedback voltage regulating loop. The first or second operational parameter may alternatively comprise the previously discussed operation regime of the power converter circuit. The control circuit 102 may be configured to switch the converter circuit 101 from operation regime 1 to operation regime 2 if the target voltage of the first DC output voltage is at least two times larger than the DC input voltage Vdd. The control circuit 102 may be configured to adjust the value of the first DC output voltage Pvdd by adjusting the DC target voltage Vref. This may for example be accomplished by using a switch matrix to switch between several different DC voltage sources. In a digital implementation of the control circuit 102, a digital-to-analog converter may be used to generate a desired voltage level of the DC target voltage Vref from a single preset DC reference voltage of the control circuit 102.

[0062] The skilled person will appreciate control circuit 102 may be configured to adjust the switching frequency f0 of the semiconductor switch arrangement between the lower and upper frequencies in a plurality of predetermined steps, for example two, three or four steps, in response to increasing levels of load power. According to one such embodiment, the control circuit 102 adjusts the switching frequency in steps from 10 kHz for near-idle operation as schematically indicated on FIG. 4A through 100 kHz, 500 kHz and finally 2 MHz as schematically indicated on FIGS. 4B, 4C and 4D, respectively, with increasing load power. Alternatively, the control circuit 102 may be configured to adjust the switching frequency f0 in a largely continuous manner in response to detected changes of the load power.

[0063] According to yet another embodiment of the power converter 100, the control circuit 102 is configured to adjust voltage levels of the control signals QC0-QC5 of the semiconductor switches of the converter circuit 101 in accordance with current load power demands. Hence, the respective voltage levels of the control signals QC0-QC5 is yet another operational parameters of the power converter 100 that may be controlled or adjusted by the control circuit 102. The control circuit 102 may be configured to select a higher voltage level of the controls signals at high load power than at small load power. The voltage of the control signals QC0-QC5 may be set to a first level for load power levels below the first power threshold which in turn may correspond to the idle and near-idle operation of the class D amplifier load circuit discussed above. When the load power level exceeds the first power threshold, the voltage of each of the control signals may be increased to second level which is markedly larger than the first level, e.g. 1, 3 or 5 volts higher. This operational parameter exploits that the equivalent on-resistance of a semiconductor switch, e.g. a MOSFET, scales inversely with the level of the applied gate control voltage, e.g. gate-to-source voltage for MOSFETs. In this manner, a higher gate to source voltage leads to decreasing on-resistance of the MOSFET switch in questions. However, the amount of energy supplied from control circuit 102 to turn-on the semiconductor switch or switches increases with increasing control voltage. The inventors have realized that in near-idle operation, where the energy required to turn on the semiconductor switches is significant and power loss due to semiconductor switch on-resistance on the contrary is insignificant, overall power conversion efficiency of the power converter can be increased when the control circuit 102 selects a small voltage level of the control signals. Conversely, when load power supplied by the power converter circuit is high, e.g. exceeds the first power threshold discussed above, the control circuit 102 may increase the overall power conversion efficiency by increasing the voltage levels of the control signals QC0-QC5 because of the smaller on-resistances of the semiconductor switches Q0-Q5 of the switch arrangement 101.

[0064] FIG. 5 illustrates a transistor level diagram of a converter circuit 501 comprising a second semiconductor switch arrangement suitable for single-output boost DC-DC power converter embodiments of the invention. The present DC-DC power converter 500 generates only a single DC output voltage Pvdd for energizing a suitable load circuit via its DC power supply rail. The load circuit may comprise a class D audio amplifier or class AB audio amplifier etc. The second semiconductor switch arrangement comprises a cascade of four controllable semiconductor switches Q0-Q3 which may be identical to the corresponding switches of the first semiconductor switch arrangement of the previously discussed converter circuit 101. In one embodiment of the power converter 500, a control circuit (not shown) is configured to select an operation regime of the semiconductor switch arrangement 501 wherein the semiconductor switches Q2 and Q3 of the second leg are placed in respective conducting states. The residual switches Q0 and Q1 are arranged in respective non-conducting states. Hence, opening a static electrically conducting path from the DC input voltage supply Vdd to the first DC output voltage Pvdd to energize the latter without providing any boost of the Vdd. This operation regime of the semiconductor switch arrangement may be selected by the control circuit when the load power is relatively small—for example corresponding to near-idle operation of a class D power amplifier load (not shown). The respective control signal waveforms QC1-QC3 applied to the gate terminals of the four controllable semiconductor switches Q0-Q3 are plotted below the circuit schematic for a single set of operational parameters the single-output boost DC-DC converter 500. This set of operational parameters may correspond to the first set of operational parameters discussed above in connection with the dual-output boost DC-DC converter 100 and FIG. 4A, i.e. applicable where the load power is relatively small. As discussed in detail in connection with the previous dual-output boost DC-DC converter 100, the control circuit of the present single-output boost DC-DC converter 500 may be configured to adjust one or more operational parameters of the power converter 500 in response to changing load current, voltage or power demands to adapt electrical properties, such as conversion efficiency, of the power converter 500 to the required load power in a corresponding manner to the one discussed above in detail in respect of the dual-output boost DC-DC converter 100.

[0065] FIG. 6 is a schematic block diagram of an audio amplification system comprising a dual-output boost DC-DC power converter 600 in accordance with one of the previously described embodiments thereof connected to a Class D audio amplifier 640. The skilled person will appreciate that the dual-output boost DC-DC power converter 600 may be identical to any of the above-discussed dual-output voltage power converters 100. The class D audio amplifier 640 has a first (GND) voltage supply rail coupled to the ground connection of the power converter 600. A second voltage supply rail Vcc of the class D audio amplifier 640 is coupled to the first or upper DC output voltage Pvdd of the power converter 600. The class D audio amplifier 640 additionally comprises a mid-supply voltage supply rail ½ Vcc which is connected to the second or lower DC output voltage ½ Pvdd of the power converter 600. The Class D audio amplifier 640 comprises a pair of speaker output terminals or pads connectable to a loudspeaker 550 which may comprise a miniature electrodynamic speaker of a portable communication terminal or device or a regular sized loudspeaker for domestic applications. The control circuit 602 is configured to monitor or detect the load current Ivdd, drawn by the class D audio amplifier 640 from the first DC output voltage Pvdd, and/or the upper DC output voltage Pvdd supplied to the class D audio amplifier. The control circuit 602 is configured to adjusting one or more operational parameters of the boost DC-DC power converter 600 as discussed above based on the detected load current, and optionally the load voltage represented by the upper DC output voltage Pvdd or the lower DC output voltage ½ Pvdd.

[0066] The class D audio amplifier 640 comprises an audio level detector (not shown) configured to determine a level of an audio input signal, or an audio signal derived therefrom, of the class D audio amplifier 640. The audio level detector may be configured to directly measure or detect a level of the audio signal at the input (Audio in), or at the output (outp-outn), of the audio amplifier 640. The audio level detector may be configured to determine the level of the audio input signal in an indirect manner by detecting a modulation index of a pulse width modulated signal generated inside the audio amplifier 640, e.g. generated by a pulse width modulator of the amplifier 640. The level of the audio signal may be expressed relative to a known maximum audio level input or a known maximum audio level output at the output terminals connected to the loudspeaker load 550. The class D audio amplifier 640 comprises a likewise optional audio level indicator (Level) configured to indicate the determined level of the audio input signal or audio signal derived therefrom for example on an externally accessible pad or terminal of the class D audio amplifier 640. The audio level indicator (Level) may be connected to an input of the control circuit 602 such that the latter is configured to adjusting the one or more operational parameters of the boost DC-DC power converter 600 as discussed above based on the detected audio signal level. This feature allows the boost DC-DC power converter 600 to adjust the upper and lower DC output voltages such that these are tracking the level of the audio signal. In this manner, the upper and lower DC output voltages may both be set to lower voltages at small levels of the audio signal than at large levels of the audio signal, i.e. an adjustment of the upper and lower DC output voltages. This has the advantage that various parasitic switching losses in the class D audio amplifier assoviaed with state switching of semiconductor devices, in particular semiconductor devices of an output stage, are reduced at small levels of the audio signal.

[0067] Curve 710 of FIG. 7 shows a computed relationship between the duty cycle D of the control signals of the semiconductor switch arrangement of the converter circuit and the ripple current magnitude running in the boost coil L1 of the previously discussed the dual-output DC power converter 100. It is evident from curve 710 that the duty cycle D=0.5 produces a distinct local minimum in the ripple current magnitude as previously discussed. This D setting minimizes the power loss associated with drawing current through the boost coil in a beneficial manner.