SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SAME

Abstract

A semiconductor element capable of adjusting a barrier height φ.sub.Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (E.sub.F) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).

Claims

1. A method of manufacturing a semiconductor element provided with a stacked diode structure obtained by stacking a first n-type semiconductor layer, a second semiconductor layer having electron affinity lower than that of the first semiconductor layer, and a third n-type semiconductor layer in this order from an anode side to a cathode side, the first and second semiconductor layers having a heterojunction, wherein a doping concentration of the first semiconductor layer is adjusted such that a detection output current detected by inputting a predetermined high-frequency signal between an anode and a cathode of the semiconductor element is maximized.

2. A method of manufacturing a semiconductor element provided with a stacked diode structure obtained by stacking a first n-type semiconductor layer, a second semiconductor layer having electron affinity lower than that of the first semiconductor layer, and a third n-type semiconductor layer in this order from an anode side to a cathode side, the first and second semiconductor layers having a heterojunction, the semiconductor element being used as a detection circuit for performing detection by inputting a predetermined high-frequency signal between an anode and a cathode of the semiconductor element, wherein a doping concentration of the first semiconductor layer is adjusted such that a detection output current is maximized, assuming that a line impedance of a high-frequency signal input side of the detection circuit or a pure resistance antenna impedance, and an input impedance of an amplifier connected to a detection output of the detection circuit are given in advance.

3. A method of manufacturing a semiconductor element provided with a stacked diode structure obtained by stacking a first n-type semiconductor layer, a second semiconductor layer, and a third n-type semiconductor layer in this order from an anode side to a cathode side, the first and second semiconductor layers having a heterojunction, wherein the first semiconductor layer is formed of InGaAs, the second semiconductor layer is formed of InP, and the first semiconductor layer has an electron concentration n.sub.e (cm.sup.−3) defined by Equation C1;
n.sub.e=1.2×10.sup.19−9.5×10.sup.18×log(√{square root over (Sj)}) (C1) where “S.sub.j (μm.sup.2)” denotes an area of the heterojunction.

4. A semiconductor element provided with a stacked diode structure obtained by stacking a first n-type semiconductor layer, a second semiconductor layer having electron affinity lower than that of the first semiconductor layer, and a third n-type semiconductor layer in this order from an anode side to a cathode side, the first and second semiconductor layers having a heterojunction, the semiconductor element being used as a detection circuit for performing detection by inputting a predetermined high-frequency signal between an anode and a cathode, wherein a doping concentration of the first semiconductor layer is adjusted such that a detection output current is maximized in a line impedance of a high-frequency signal input side of the detection circuit or a pure resistance antenna impedance, and an input impedance of an amplifier connected to a detection output of the detection circuit, which are given in advance.

5. A semiconductor element provided with a stacked diode structure obtained by stacking a first n-type semiconductor layer, a second semiconductor layer, and a third n-type semiconductor layer in this order from an anode side to a cathode side, the first and second semiconductor layers having a heterojunction, wherein the first semiconductor layer is formed of InGaAs, the second semiconductor layer is formed of InP, and the first semiconductor layer has an electron concentration n.sub.e (cm.sup.−3) defined by Equation C1, where “S.sub.j (μm.sup.2)” denotes an area of the heterojunction.

6. The semiconductor element according to claim 5, wherein the stacked diode structure further has: a fourth n-type semiconductor layer stacked in the anode side of the first semiconductor layer, and a fifth n-type semiconductor layer stacked in the cathode side of the third semiconductor layer, wherein the stacked diode structure is formed such that the fifth semiconductor layer adjoins a semi-insulating semiconductor substrate.

7. The semiconductor element according to claim 6, further comprising an anode electrode and a cathode electrode, wherein the anode electrode adjoins a side of the fourth semiconductor layer opposite to the second semiconductor layer, the fifth semiconductor layer has an area larger than that of the third semiconductor layer as seen in a stacking direction, and the cathode electrode is placed in the third semiconductor layer side of the fifth semiconductor layer such that the cathode electrode does not come into contact with the third semiconductor layer.

8. The semiconductor element according to claim 7, wherein the anode electrode has an area larger than that of the fourth semiconductor layer as seen in the stacking direction.

9. The semiconductor element according to claim 7, wherein the first semiconductor layer has an area larger than that of the second semiconductor layer as seen in the stacking direction.

10. A semiconductor device comprising: an electric connection line that connects an electric high-frequency input circuit and an electric output circuit; and a semiconductor element provided with a stacked diode structure obtained by stacking a first n-type semiconductor layer, a second semiconductor layer having electron affinity lower than that of the first semiconductor layer, and a third n-type semiconductor layer in this order from an anode side to a cathode side, the first and second semiconductor layers having a heterojunction, wherein the semiconductor element being used as a detection circuit for performing detection by inputting a predetermined high-frequency signal between an anode and a cathode, wherein a doping concentration of the first semiconductor layer is adjusted such that a detection output current is maximized in a line impedance of a high-frequency signal input side of the detection circuit or a pure resistance antenna impedance, and an input impedance of an amplifier connected to a detection output of the detection circuit, which are given in advance, wherein the cathode side is connected to the electric connection line, the anode side is connected to the ground, and a detection signal obtained by detecting an electric high-frequency wave from the electric high-frequency input circuit is output to the electric output circuit.

11. The semiconductor device according to claim 10, wherein the electric high-frequency input circuit is an antenna.

12. The semiconductor device according to claim 14, wherein the electric high-frequency input circuit is a planar antenna formed on the semi-insulating semiconductor substrate.

13. A semiconductor device comprising: an electric connection line that connects an electric high-frequency input circuit and an electric output circuit; and a semiconductor element provided with a stacked diode structure obtained by stacking a first n-type semiconductor layer, a second semiconductor layer, and a third n-type semiconductor layer in this order from an anode side to a cathode side, the first and second semiconductor layers having a heterojunction, wherein the first semiconductor layer is formed of InGaAs, the second semiconductor layer is formed of InP, and the first semiconductor layer has an electron concentration n.sub.e (cm.sup.−3) defined by Equation C1, where “S.sub.j (μm.sup.2)” denotes an area of the heterojunction, wherein the cathode side is connected to the electric connection line, the anode side is connected to the ground, and a detection signal obtained by detecting an electric high-frequency wave from the electric high-frequency input circuit is output to the electric output circuit.

14. The semiconductor device according to claim 13, wherein the stacked diode structure further has: a fourth n-type semiconductor layer stacked in the anode side of the first semiconductor layer, and a fifth n-type semiconductor layer stacked in the cathode side of the third semiconductor layer, wherein the stacked diode structure is formed such that the fifth semiconductor layer adjoins a semi-insulating semiconductor substrate.

15. The semiconductor device according to claim 14, further comprising an anode electrode and a cathode electrode, wherein the anode electrode adjoins a side of the fourth semiconductor layer opposite to the second semiconductor layer, the fifth semiconductor layer has an area larger than that of the third semiconductor layer as seen in a stacking direction, and the cathode electrode is placed in the third semiconductor layer side of the fifth semiconductor layer such that the cathode electrode does not come into contact with the third semiconductor layer.

16. The semiconductor device according to claim 15, wherein the anode electrode has an area larger than that of the fourth semiconductor layer as seen in the stacking direction.

17. The semiconductor device according to claim 15, wherein the first semiconductor layer has an area larger than that of the second semiconductor layer as seen in the stacking direction.

18. The semiconductor device according to claim 17, wherein the electric high-frequency input circuit is an antenna.

19. The semiconductor device according to claim 17, wherein the electric high-frequency input circuit is a planar antenna formed on the semi-insulating semiconductor substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0053] FIG. 1 is a diagram illustrating a structure of a semiconductor element according to the present disclosure;

[0054] FIG. 2 is a band diagram of a semiconductor element according to the present disclosure;

[0055] FIG. 3 is a diagram illustrating a structure of the semiconductor element according to the present disclosure;

[0056] FIG. 4 is a diagram illustrating a structure of the semiconductor element according to the present disclosure;

[0057] FIG. 5 is a diagram illustrating a semiconductor device (detection circuit) according to the present disclosure;

[0058] FIG. 6 is a diagram illustrating an equivalent circuit of the semiconductor device (detection circuit) according to the present disclosure;

[0059] FIG. 7 is a diagram illustrating a barrier height and a frequency characteristic of the semiconductor element according to the present disclosure;

[0060] FIG. 8A is a diagram illustrating a relationship between an electron concentration of a first semiconductor layer of the semiconductor element according to the present disclosure and a detection current output from the semiconductor device according to the present disclosure;

[0061] FIG. 8B is a diagram illustrating a relationship between an electron concentration of the first semiconductor layer of the semiconductor element according to the present disclosure and the detection current output from the semiconductor device according to the present disclosure;

[0062] FIG. 9 is a diagram illustrating a semiconductor device (detection circuit) according to the present disclosure;

[0063] FIG. 10 is a band diagram of a heterobarrier diode (HBD) structure using InGaAsP;

[0064] FIG. 11 is a diagram illustrating a diode equivalent circuit; and

[0065] FIG. 12 is a diagram schematically illustrating a current-voltage (I-V) characteristic of a diode and a detection I-V characteristic for a high frequency input.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0066] Embodiments of the present disclosure (?) is now described with reference to the accompanying drawings. The following embodiments are examples of the present disclosure, and the present disclosure is not limited to the embodiments described below. Such examples are just for illustrative purposes, and various changes or modifications may also be possible on the basis of knowledge of a person ordinarily skilled in the art. Note that like reference numerals denote like elements through the entire specification and drawings.

First Embodiment

[0067] FIG. 1 is a schematic diagram illustrating a basic configuration of a semiconductor element 301 according to this embodiment. Each semiconductor layer includes the following components. [0068] 1: high-concentration n-type InGaAs contact layer (fourth semiconductor layer) [0069] 2: n-type InGaAs layer having an electron concentration adjusted depending on a requirement (first semiconductor layer) [0070] 3: low-concentration InP depletion layer (second semiconductor layer) [0071] 4: high-concentration n-type InP layer (third semiconductor layer) [0072] 5: high-concentration n-type InGaAs contact layer (fifth semiconductor layer) [0073] 6: anode electrode [0074] 7: cathode electrode

[0075] FIG. 2 is a band diagram of the semiconductor element according to this embodiment. The Fermi level E.sub.F and an electron concentration distribution 10 are illustrated in association. Since InGaAs has electron affinity larger than that of InP, a conduction band discontinuity (ΔE.sub.C=240 meV) is generated on an “in-band line-up” between the n-type InGaAs layer 2 and the low-concentration InP depletion layer 3 as illustrated in FIG. 2. Accordingly, an electron energy barrier (qφ.sub.Bn=ΔE.sub.C−(E.sub.f−E.sub.C)) asymmetric in the InGaAs/InP junction in Equation 4 is generated. The barrier height looking from InP to the InGaAs side depends on a voltage. However, the barrier height looking from InGaAs to the InP side mostly unchanges with a voltage. Using this barrier, it is possible to provide a diode having a rectification characteristic (=nonlinearity).

[0076] The electron concentration of InGaAs on the InGaAs/InP interface (n-type InGaAs layer 2) is preferably set to be high in order to reduce a voltage change of the barrier height φ.sub.Bn by virtue of an electron accumulation effect of the heterojunction interface. This is because, if the concentration is low, the barrier height φ.sub.Bn (=ΔE.sub.C−E.sub.F) on the heterojunction interface is changed by the bias due to a change of the charge of the InGaAs side (n-type InGaAs layer 2) to intercept the electric field of the depleted InP (InP depletion layer 3).

[0077] A concept of the semiconductor element according to the present disclosure is to intentionally increase the electron concentration of the InGaAs (n-type InGaAs layer 2) up to a deep degeneration range over a range capable of preventing the “change of the barrier height by the bias” described above, such that the electron Fermi level (E.sub.F) increases from a band edge of InGaAs (n-type InGaAs layer 2) to a band edge of InP (InP depletion layer 3). In this case, in an ideal case, the I-V characteristic of the HBD can be expressed as follows.

[00002] $\begin{matrix} [Equation .Math. .Math. 5] \\ \begin{matrix} I_{SBD} (V) = .Math. I_{S} .Math. (\exp (V / V_{T}) - 1) \\ = .Math. S_{j} \times A^{*} .Math. T^{2} \times \exp (- φ_{Bn} / V_{T}) \times (\exp (V / V_{T}) - 1) \\ = .Math. S_{j} \times A^{*} .Math. T^{2} \times \exp (- (Δ .Math. .Math. E_{C} - (E_{F} - E_{C})) / kT) \times \\ .Math. (\exp (V / V_{T}) - 1) \end{matrix} & (5) \end{matrix}$

[0078] That is, the barrier height (φ.sub.Bn is adjusted by raising or lowering the Fermi level E.sub.F by changing the electron concentration n.sub.e of the n-type InGaAs layer 2, so that it is possible to change the I-V characteristic of the HBD (change the saturation current I.sub.S and the differential resistance value R.sub.D).

[0079] One of the methods of experimentally optimizing the electron concentration n.sub.e of the n-type InGaAs layer 2 of the HBD is described below. A first n-type semiconductor layer, a second semiconductor layer having electron affinity lower than that of the first semiconductor layer, and a third n-type semiconductor layer are stacked in this order from the anode side to the cathode side to form a plurality of diode structures having a heterojunction between the first and second semiconductor layers. The electron concentration of the first semiconductor layer in each diode structure is changed by controlling a doping concentration when the first semiconductor layer is stacked. In addition, the detection current obtained by inputting predetermined RF signals to such a diode structure is plotted individually, and the electron concentration capable of obtaining the maximum detection current is found from the result of the plotting.

[0080] More specifically, in order to optimize the aforementioned HBD element, assuming that a line impedance of the high frequency signal input side of the detection circuit or a pure resistance antenna impedance, and an input impedance of the amplifier connected to the detection output are given in advance, a doping concentration of the first semiconductor layer is adjusted such that the output current detected by inputting the high frequency signal is maximized. A Plurality of diode structures are prepared by changing the doping concentration as described above, and they are used as the detection circuit, and the line impedance in the high frequency signal input side or the antenna impedance of the pure resistance and the input impedance of the amplifier connected to the detection output are given by using the diode structures. The detection current obtained by inputting predetermined RF signals to the detection circuit is plotted. An electron concentration capable of maximizing the detection current is found from the result of the plotting.

[0081] If the detection circuits including the HBD have the same configuration, the optimum saturation current I.sub.S becomes a constant value. Therefore, the barrier height φ.sub.Bn is changed depending on the area S.sub.j of the heterojunction. For this reason, the electron concentration n.sub.e of the n-type InGaAs layer 2 is determined by using Equation C1 as an index assuming that the heterojunction area necessary in the frequency characteristic is denoted by S.sub.j (μm.sup.2).

[0082] It was found that an optimum receive characteristic can be obtained in a wide amplifier input line impedance range of 35 to 200Ω for a typical antenna impedance (75Ω) if the electron concentration n.sub.e of the n-type InGaAs layer 2 is determined in this manner. For example, if the junction area is set to “S.sub.j=0.5 μm.sup.2,” the concentration becomes “n.sub.e=1.3×10.sup.19 (/cm.sup.3).” In this condition, the Fermi level E.sub.F increases by approximately 160 meV from the conduction band edge. As a result, an effective electron energy barrier qφ.sub.Bn (=ΔE.sub.C−E.sub.F) becomes 80 meV which is remarkably low, and the saturation current I.sub.S becomes 0.17 mA which is remarkably high, compared to the HED of the prior art.

Second Embodiment

[0083] The semiconductor element according to this embodiment further has a semi-insulating semiconductor substrate in addition to the semiconductor element 301 of FIG. 1. Specifically, the stacked diode structure is formed such that the fifth semiconductor layer comes into contact with the semi-insulating semiconductor substrate. In addition, the anode electrode adjoins a side of the fourth semiconductor layer opposite to the second semiconductor layer, and the area of the fifth semiconductor layer is larger than the area of the third semiconductor layer as seen in a stacking direction. Furthermore, the cathode electrode is placed in the third semiconductor layer side of the fifth semiconductor layer such that the cathode electrode does not come into contact with the third semiconductor layer.

[0084] FIGS. 3 and 4 are schematic diagrams illustrating the semiconductor element 302 according to this embodiment, in which FIG. 3 is a plan view illustrating the semiconductor element, and FIG. 4 is a cross-sectional view (taken along the line A-A′). Each semiconductor layer is formed as follows. [0085] 11: high-concentration n-type InGaAs contact layer (fourth semiconductor layer) [0086] 12: n-type InGaAs layer (first semiconductor layer) having an electron concentration adjusted depending on a requirement [0087] 13: low-concentration InP depletion layer (second semiconductor layer) [0088] 14: high-concentration n-type InP (third semiconductor layer) [0089] 15: high-concentration n-type InGaAs contact layer (fifth semiconductor layer) [0090] 16: anode electrode [0091] 17: cathode electrode [0092] 18: semi-insulating semiconductor substrate [0093] 19: wire metal [0094] 20: HBD region

[0095] Reference numerals 11 to 17 correspond to reference numerals 1 to 7 of FIG. 1.

[0096] In order to manufacture the HBD, all of the semiconductor layers are epitaxially grown through metal organic vapor phase epitaxy (MO-VPE) or molecular beam epitaxy (MBE), and the resulting patterns are made on substrates. The anode electrode 16 is patterned, and the underlying semiconductor layer is chemically etched by using the patterned anode electrode 16 as a mask, so that an overhang profile shown in the cross-sectional view of FIG. 4 can be manufactured. Since a size of the anode electrode 16 can be formed to be larger than the junction size of the semiconductor layer, it is possible to facilitate patterning of the wire metal 19. Since the low-concentration InP depletion layer 13 and the high-concentration n-type InP 14 are chemically etched by using the n-type InGaAs layer 12 as a mask, the more minute size can be obtained. Therefore, it is possible to reduce the junction capacitance C.sub.1 of the HBD.

Third Embodiment

[0097] FIGS. 5 and 6 are diagrams illustrating a semiconductor device 401 according to this embodiment.

[0098] The semiconductor device 401 includes an electric connection line 9A that connects an electric high-frequency input circuit 8A and an electric output circuit 8B and the semiconductor element 301 having the cathode side connected to the electric connection line 9A and the anode side connected to the ground 9B to output a detection signal obtained by detecting an electric high frequency wave from the electric high-frequency input circuit 8A to the electric output circuit 8B. Note that, in FIG. 6, the semiconductor element 301 is illustrated as a diode (HBD) 20. Each circuit and the like are formed as follows (those already described in the first embodiment are not described). [0099] 8A: electric high-frequency (RF) input circuit [0100] 8B: electric output circuit [0101] 9A: electric connection line [0102] 9B: ground [0103] 9C: RF electric signal input port [0104] 9D: detection output port

[0105] The semiconductor device 401 has a pair of electrode terminals between the cathode electrode 7 and the anode electrode 6 of the semiconductor element 301. The electric RF input circuit 8A is connected to one of the electrode terminals, and the electric output circuit 8B is connected to the other electrode terminal, so that they serve as a detection circuit.

[0106] The electric RF input circuit 8A is, for example, a transmission line or an antenna. Detection voltage and current generated by an electric RF signal are dominated by the RF voltage applied to a true portion (parallel circuit of C.sub.j and R.sub.D) of the HBD (the diode 20 of FIG. 6) and the operation point. Therefore, it is possible to evaluate a detection output characteristic by estimating which kind of the RF voltages will reach both ends of the HBD true portion for an even RF input.

[0107] Consider a case where the electric RF input circuit 8A is the pure resistance antenna (impedance Zo=75Ω). If this pure resistance antenna is directly connected to the HBD 20, this can be regarded as an equivalent circuit of FIG. 6. Voltages generated by the differential resistance R.sub.D are obtained for an even RF input 31.

[0108] In the circuit of FIG. 6, it is assumed that the impedance of the input line is set to “Zo=75Ω,” the junction area is set to “S.sub.j=0.5 μm.sup.2,” the junction capacitance is set to “C.sub.j=1.85 fF,” the series resistance is set to “R.sub.S=10Ω,” and the input impedance is set to “R.sub.in=infinite (the output of the semiconductor device has an open state). The RF current I.sub.RF generated in the differential resistance R.sub.D of the HBD 20 depending on a frequency, when the saturation current I.sub.S is changed by inputting even RF power (that is, when the electron concentration of InGaAs is changed), was computed (FIG. 7). In FIG. 7, the abscissa refers to a frequency of the RF input 31, and the ordinate refers to the RF current I.sub.RF generated in the differential resistance R.sub.D.

[0109] If the electron energy barrier is set to “qφ.sub.Bn=63 meV,” there is a slight voltage drop of the series resistance R.sub.S. However, since impedance matching is almost achieved between the differential resistance R.sub.D and the line, the impedance becomes nearly 0 dB in a low frequency range. Meanwhile, as the electron energy barrier increases to “qφ.sub.Bn=80 meV” and to “qφ.sub.Bn=138 meV,” the impedance becomes mismatched to “Zo<R.sub.D.” Therefore, a current flowing through the differential resistance R.sub.D is reduced, so that the detection current is reduced accordingly. As described above in conjunction with the background art, the current sensitivity is not changed while impedance matching is achieved. That is, if the differential resistance R.sub.D increases and impedance mismatching becomes bigger, they bring to decrease the detection current. Note that the detection current is described below again with reference to FIG. 8.

[0110] Under the mismatching conditions, a state shifts from where the bandwidth (frequency characteristic) is determined by “C.sub.j.Math.Zo” to where the bandwidth is determined by “C.sub.j.Math.R.sub.D” as the differential resistance R.sub.D decreases. Therefore, the lower electron energy barrier qφ.sub.Bn is More advantageous. Focusing on a 3 dB-down frequency (f.sub.−3dB), it is recognized that the f.sub.−3dB of 1.1 THz for the electron energy barrier qφ.sub.Bn of 138 meV increases to 2.2 THz for the electron energy barrier qφ.sub.Bn of 63 meV (in FIG. 7, illustrated as white circles O on each frequency characteristic).

[0111] As described above, in many systems that handle high-speed signals in reality, the detection output is connected to a feedback amplifier, and the input impedance R.sub.in is typically set to 50Ω. Here, it is important to set a large detection current output in terms of improvement of the signal-to-noise (S/N) ratio.

[0112] A behavior of the detection output current can be computed when changing the electron concentration n.sub.e (=electron energy barrier qφ.sub.Bn) of the n-type InGaAs layer 2. In FIG. 8A, the impedance of the input line of the circuit of FIG. 6 is set to “Zo=75Ω” and “R.sub.in=50Ω.” In FIG. 8B, the impedance is set to “Zo=250Ω” and “R.sub.in=500Ω.” In FIGS. 8A and 8B, the abscissa refers to the electron concentration n.sub.e of the n-type InGaAs layer 2, and the ordinate refers to the current output to the impedance R.sub.in out of the detection current output from the HBD. Note that the RF input 31 is set to “−30 dBm.”

[0113] The detection current on the ordinate is the current output from the detection circuit having the differential resistance R.sub.D as a power-source impedance to the R.sub.in portion. As the electron concentration n.sub.e of the n-type InGaAs layer 2 decreases, and the electron energy barrier qφ.sub.Bn increases, the saturation current I.sub.S decreases. Therefore, the detection current also decreases. Meanwhile, if the electron concentration n.sub.e exceeds its optimum range, the differential resistance R.sub.D decreases relative to the impedance Zo. In this state, the input high-frequency is reflected (that is, the matching state is deteriorated, and the HBD terminal voltage decreases), so that the detection current decreases. For this reason, as illustrated in FIGS. 8A and 8B, the detection current of the R.sub.in portion has a peak at a certain electron energy barrier qφ.sub.Bn, that is, at a given electron concentration n.sub.e of InGaAs. The series resistance R.sub.S is set to zero (0Ω) or real values (10Ω and 20Ω). A change of an optimum point of the electron concentration n.sub.e caused by the series resistance R.sub.S is not really significant.

[0114] In the example of no-feeding (zero bias) operation of FIG. 8A, the optimum value (corresponding to an electron energy barrier qφ.sub.Bn of 80 meV) exists in the vicinity of an electron concentration n.sub.e of 1.3×10.sup.19 (/cm.sup.3). Since this electron concentration n.sub.e corresponds to the junction area S.sub.j of 0.5 μm.sup.2, the differential resistance R.sub.D becomes 150Ω, and the saturation current I.sub.S becomes 166 μA according to Equation C1. It is recognized that the detection current output has a maximum value if the differential resistance R.sub.D of the HBD is slightly higher than the exact matching impedance (Zo=75Ω) of the input line.

[0115] In the example of no-feeding (zero bias) operation of FIG. BB, the optimum value exists in the vicinity of an electron concentration n.sub.e of 1.0×10.sup.19 (/cm.sup.3). As in this example, it is important that a certain optimum electron concentration n.sub.e peak exists depending on a given circuit condition, and the electron concentration n.sub.e and the value “log [√S.sub.j]” have a linear relationship as estimated from Equation C1. Note that the numerical relationship between the junction area S.sub.j and the optimum electron concentration n.sub.e described above in conjunction with Equation C1 corresponds to a case where the impedance of the input line is set to “Zo=75Ω,” and the input impedance of the amplifier is set to “R.sub.in=50Ω” (a receiver detection circuit of a high-speed signal).

Fourth Embodiment

[0116] FIG. 9 is a diagram illustrating a semiconductor device 402 according to this embodiment. A planar bow tie antenna as the electric RF input circuit 8B is connected to the semiconductor device. Each circuit is provided as follows. [0117] 19: wire metal [0118] 20: HBD region [0119] 21: bow tie antenna metal [0120] 22: detection output line (one for the electric connection line, and the other for the ground) [0121] 23: connection end

[0122] The HBD region 20 according to this embodiment is the HBD region 20 of FIG. 3.

[0123] A pattern end of the bow tie antenna metal 21 is connected to the wire metal 19 extending from the HBD region 20 of FIG. 9. In addition, if a circuit is provided in a transmission line, typically, a high impedance filter circuit capable of removing a high frequency component is connected to the connection end 23. The high frequency signal input to the bow tie antenna may also contain a component emitted back from the corresponding antenna. However, the high frequency signal is less coupled to the detection output line 22 connected to the high impedance filter circuit. That is, as seen from the antenna side which is the electric RF input circuit 8A, the detection output line 22 connected to the electric output circuit 8B has a high-frequency cut-off state.

[0124] Meanwhile, if the antenna side is seen from the connection end 23, the frequency of the connection end 23 is deviated from the frequency band of the bow tie antenna. Therefore, it has a low-frequency cut-off state.

[0125] Therefore, the semiconductor device 402 basically has the same circuit configuration as that of the equivalent circuit of FIG. 6 (including the electric RF input circuit 8A and the HBD region 20).

[0126] <Effects>

[0127] As described above, the present disclosure provides a technology capable of improving the detection current output and the bandwidth (3 dB-down frequency) performance of the detection device in which a zero-bias operation is performed at a high frequency band, in particularly, at a THz frequency range. This technology is a design method for basically approximating the differential resistance value R.sub.D of the operating point to an impedance matching state of the RF input line by implementing the lower barrier height φ.sub.Bn and increasing the saturation current I.sub.S, compared to the HBD of the prior art, and setting the detection current output to an optimum value. The diode formed of only semiconductor materials has a problem of unstable characteristics caused by the barrier metal, which is serious in the SBD. The present disclosure is able to solve the problem and facilitates manufacturing of the array sensor that requires a uniform detection output.

APPENDIX

[0128] How to derive Equation C1 will be described.

[0129] A logarithm “log( )” is applied to both sides of Equation 3.

[00003] $\begin{matrix} .Math. [Equation .Math. .Math. A .Math. .Math. 1] \\ .Math. {\log (e)}^{- 1} \times \log (\frac{I_{S}}{A^{*} .Math. T^{2}}) = {\log (e)}^{- 1} \times \log (S_{j}) - \frac{φ_{Bn}}{V_{T}} .Math. .Math. {\log (e)}^{- 1} \times \log (\frac{I_{S}}{A^{*} .Math. T^{2}}) - {\log (e)}^{- 1} \times \log (S_{j}) = - \frac{φ_{Bn}}{V_{T}} \times \frac{Δ .Math. .Math. E_{C} - (E_{f} - E_{C})}{q} = - \frac{φ_{Bn}}{V_{T}} \times (\frac{Δ .Math. .Math. E_{C}}{q} - G \times n_{c}) & (A1) \end{matrix}$

[0130] Here, electron concentration dependence of the Fermi level is assumed as the following formula.

[Equation A2]

(E.sub.f−E.sub.C)/q=G×n.sub.e (A2)

[0131] where “G” denotes a coefficient.

[0132] In addition, Equation A2 can be expressed as the following formula by setting the junction area to “S.sub.j=S.sub.jum×10.sup.−8 (cm.sup.2)” and setting the unit to microns.

[00004] $\begin{matrix} .Math. [Equation .Math. .Math. A .Math. .Math. 3] \\ n_{e} = \frac{V_{T}}{G} [{\log (e)}^{- 1} \times \log (\frac{I_{S}}{A^{*} .Math. T^{2}})] + \frac{Δ .Math. .Math. E_{C}}{qG} + \frac{8 .Math. .Math. V_{T}}{G .Math. .Math. \log (e)} - \frac{2 .Math. .Math. V_{T}}{G .Math. .Math. \log (e)} \times \log (\sqrt{S_{jum}}) & (A3) \end{matrix}$

[0133] In the case of the InGaAs/InP heterojunction, the coefficient G is estimated to “G=1.21×10.sup.−20” on the basis of the non-patent document examples. In the case of a typical high-speed detection circuit of the present disclosure, an optimum value of the saturation current I.sub.S becomes “I.sub.S(optimum)=166 μA” under the following condition (as described above). [0134] input line impedance: Zo=75 Ω [0135] amplifier input impedance: R.sub.in=50 Ω

[0136] In addition, if “V.sub.T=0.025 and ΔE.sub.C=0.24/q” is substituted with Equation A3, the following formula can be obtained.

[00005] $\begin{matrix} .Math. [Equation .Math. .Math. A .Math. .Math. 4] \\ \begin{matrix} n_{e} = .Math. \frac{V_{T}}{G} [{\log (e)}^{- 1} \times \log (\frac{I_{S}}{A^{*} .Math. T^{2}})] + \frac{Δ .Math. .Math. E_{C}}{qG} + \frac{8 .Math. .Math. V_{T}}{G .Math. .Math. \log (e)} - \frac{2 .Math. .Math. V_{T}}{G .Math. .Math. \log (e)} \times \\ .Math. \log (\sqrt{S_{jum}}) \\ = .Math. 1.18 \times 10^{19} - 9.5 \times 10^{18} .Math. \log (\sqrt{S_{jun}}) \end{matrix} & (A4) \end{matrix}$

[0137] Equation A4 corresponds to Equation C1.

ADDITIONAL REMARKS

[0138] In the following description, a semiconductor detection device that receives RF electric signals at a frequency band of millimeter waves to several THz waves according to the present disclosure, more specifically, a high-speed semiconductor detection device operated in a zero-bias state with low noise will be described.

[0139] The present disclosure relates to a semiconductor detection device that receives RF electric signals at a high frequency band, and provides a means capable of appropriately setting the saturation current I.sub.S and the differential resistance value R.sub.D at the zero-bias operating point using a simple structure even in a small junction capacitance and improving a receive sensitivity of a detection receiver device.

[0140] <1>

[0141] A semiconductor element comprising: a stacked diode structure provided with a heterojunction including a first n-type semiconductor and a second semiconductor, and a third n-type semiconductor adjoining the second semiconductor to serve as a contact layer; an electrode terminal having an electric contact to the first n-type semiconductor; and an electrode terminal having an electric contact to the third n-type semiconductor, wherein, assuming that a desired value is given for an area (S.sub.j μm.sup.2) of the heterojunction including the first re-type semiconductor and the second semiconductor, the structure is determined by adjusting an electron concentration of the first n-type semiconductor in order to maximize the detection current input to the amplifier connected to subsequent stages for a given RF input.

[0142] <2>

[0143] In the semiconductor element according to Part <1>,

[0144] the first n-type semiconductor is formed of InGaAs,

[0145] the second semiconductor is formed of InP having a low concentration, and

[0146] an electron concentration n.sub.e of the first n-type semiconductor is determined by “n.sub.e=1.16×10.sup.19-9. 5×10×log [√S.sub.j]/cm.sup.3” when an area of the heterojunction constituted of the first n-type semiconductor and the second semiconductor “S.sub.j μm.sup.2” is given.

[0147] <3>

[0148] In the semiconductor device according to Parts <1> and <2>, a third n-type contact layer is placed to adjoin an outer side of the first n-type semiconductor of the stacked diode structure, a fourth n-type contact layer is placed to adjoin an outer side of the third re-type semiconductor, and each layer is formed on a substrate.

[0149] <4>

[0150] In the semiconductor device according to Parts <1>, <2>, and <3>, an electric RF input circuit and a detection output circuit are connected to a pair of electrode terminals as described above.

[0151] <5>

[0152] In the semiconductor device according to Parts <1>, <2>, <3>, and <4>, the semiconductor device is a planar antenna or a stereoscopic antenna in which an electric RF input circuit is formed on a substrate.

REFERENCE SIGNS LIST

[0153] 301, 302: semiconductor element (HBD) [0154] 401, 402: semiconductor device

SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SAME

Inventors

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H01L29/861

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H01L29/66121

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H01L29/36

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H01L29/205

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H01Q23/00

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H01L29/6609

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H01L29/0657

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H01L29/861

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H01Q23/00

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H01L29/205

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H01L29/66

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Abstract

Claims

Description