PHASE MEASURING DEVICE AND APPARATUSES USING THE PHASE MEASURING DEVICE

Abstract

The inventive phase measuring device includes a first A/D converter 2 that digitizes a first periodical input signal X at each predetermined sampling timing and outputs the resultant signal as a digital signal Xd, a first zero-crossing identification means operable to detect a sign of Xd, a counting processing unit 4 that counts a difference in the number of times of zero-crossing detection by the first zero-crossing identification means and calculates the difference at each sampling timing, and a fraction processing unit 5 that computes a fraction of the number of times of zero-crossing detection on the basis of Xd at sampling timings immediately before and immediately after determination of zero-crossing by the first zero-crossing identification means. An averaging processing unit 6 performs averaging by adding up and totalizing the outputs from the counting processing unit 4 and the fraction processing unit 5, thereby computing a phase. The inventive device thus implements a digital phase measuring device and a digital phase difference measuring device that allow input of periodical signals in a wide frequency range and that are capable of accurate and real-time measurement.

Claims

1. A phase measuring device for measuring a phase of a periodical input signal that changes periodically or a phase difference between periodical input signals by using a digital circuit, the device comprising: an A/D converter that digitizes the periodical input signal respectively at each predetermined sampling timing and outputs each resultant signal as a digital signal; a zero-crossing identification means operable to detect a change in sign of the digital signal; a counting processing unit that counts the number of times of zero-crossing detection by the zero-crossing identification means and calculates the number at each said sampling timing; a fraction processing unit that computes a fraction F.sup.x of the number of times of zero-crossing detection, on the basis of the digital signal at sampling timings immediately before and immediately after determination of zero-crossing by the zero-crossing identification means; and an averaging processing unit that performs averaging on the basis of a sum of N output values calculated by the counting processing unit and a sum of the fractions F.sup.x computed by the fraction processing unit during a corresponding period, to compute a phase of the digital signal.

2. The phase measuring device according to claim 1, wherein the periodical input signal includes a first periodical input signal X and a second periodical input signal Y, the A/D converter includes first and second A/D converters that digitize the periodical input signals X and Y, respectively, at each predetermined sampling timing and output the resultant signals as digital signals Xd and Yd, respectively, the zero-crossing identification means includes first and second zero-crossing identification means operable to detect changes in sign of the digital signals Xd and Yd, respectively, the counting processing unit counts a difference between the number of times of zero-crossing detection by the first zero-crossing identification means and the number of times of zero-crossing detection by the second zero-crossing identification means, and calculates the difference at each said sampling timing, the fraction processing unit computes fractions F.sup.X and F.sup.Y of the respective numbers of times of zero-crossing detection by the first and second zero-crossing identification means, on the basis of the digital signals Xd and Yd at sampling timings immediately before and immediately after determination of zero-crossing by the corresponding ones of the first and second zero-crossing identification means, and the averaging processing unit performs averaging on the basis of a sum of N output values calculated by the counting processing unit and a difference between a sum of the fractions F.sup.X and a sum of the fractions F.sup.Y computed by the fraction processing unit during a corresponding period, to compute a phase difference between the digital signals Xd and Yd, thereby measuring a phase difference between the periodical input signals X and Y.

3. The phase measuring device according to claim 1, wherein when a sampling rate for driving the A/D converter is represented as f.sub.ADC and the number of averaging of the averaging processing unit is represented as N, a phase difference calculation rate of f.sub.ADC/N is attained in the averaging processing unit.

4. A displacement measuring device based on a laser heterodyne interferometer, the device causing reflected light, obtained by irradiating a measurement object with laser light, to interfere with reference light, obtained by applying a frequency shift to the laser light, and measuring a displacement of the measurement object from a phase difference between the lights, the device employing the phase measuring device according to claim 2, wherein the reflected light corresponds to the first periodical input signal X and the reference light corresponds to the second periodical input signal Y, and the phase measuring device includes a computing means that computes the displacement of the measurement object on the basis of an output from the averaging processing unit.

5. The displacement measuring device according to claim 4, wherein when resolution of the displacement measuring device is represented as d.sub.r and a maximum value of a measurable velocity range is represented as v.sub.max, the following relationships are satisfied:
d.sub.r=λ/(4N.Math.2.sup.n)
v.sub.max<λ(f.sub.ADC−4f.sub.h)/8 where λ is a laser wavelength, N is the number of averaging, n is the number of conversion bits of the A/D converter, f.sub.ADC is a sampling rate of the A/D converter, and fh is a frequency of the reference signal.

6. A phase noise measuring device which measures a time history of phase fluctuation of an input signal by comparing the input signal with a high-stability reference signal, the device employing the phase measuring device according to claim 2, wherein the input signal and the high-stability reference signal correspond respectively to one and the other of the first periodical input signal X and the second periodical input signal Y, and the phase fluctuation of the input signal is measured on the basis of an output from the averaging processing unit.

7. A PLL circuit which generates a phase-locked output signal with respect to a periodical input signal by using a phase comparator, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider, the PLL circuit employing the phase measuring device according to claim 2 as the phase comparator, wherein the input signal corresponds to the first periodical input signal X and an output from the frequency divider corresponds to the second periodical input signal Y.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0057] FIG. 1 is a diagram illustrating a general outline of signal processing in a phase measuring device of the present invention.

[0058] FIG. 2 is a block diagram of a counting processing unit according to the present invention.

[0059] FIG. 3 is a diagram illustrating an operation of the counting processing unit according to the present invention.

[0060] FIG. 4 is a block diagram of a fraction processing unit according to the present invention.

[0061] FIG. 5 is a diagram illustrating an operation of the fraction processing unit according to the present invention.

[0062] FIG. 6 is a diagram illustrating a relationship between an input signal and zero-crossing detection.

[0063] FIG. 7 is a diagram illustrating an operation until averaging processing is performed.

[0064] FIG. 8 is a diagram illustrating a general outline of signal processing in a phase difference measuring device of the present invention.

[0065] FIG. 9 is a block diagram of a counting processing unit in the phase difference measuring device of the present invention.

[0066] FIG. 10 is a diagram illustrating an operation of the counting processing unit in the phase difference measuring device of the present invention.

[0067] FIG. 11 is a block diagram of a fraction processing unit in the phase difference measuring device of the present invention.

[0068] FIG. 12 is a diagram illustrating an operation performed by the fraction processing unit in the phase difference measuring device of the present invention.

[0069] FIG. 13 is a diagram illustrating an operation until averaging processing is performed in the phase difference measuring device of the present invention.

[0070] FIG. 14 is a diagram illustrating a general outline of Example 1 as an application to a laser heterodyne interferometer.

[0071] FIG. 15 is a diagram listing advantages of Example 1 as compared to the conventional techniques.

[0072] FIG. 16 is a diagram illustrating a general outline of Example 2 as an application to a phase noise measuring device.

[0073] FIG. 17 is a block diagram of a general PLL circuit.

[0074] FIG. 18 is a block diagram of Example 3 as an application to a PLL circuit.

DESCRIPTION OF EMBODIMENTS

[0075] Firstly, the basic principles of the phase measuring device based on the present invention will be described with reference to the drawings.

[0076] A periodical input signal in the phase measuring device will be hereinafter referred to as an input signal X.

[0077] The general outline of signal processing performed by the phase measuring device 1 based on the present invention is shown in FIG. 1.

[0078] The input signal X is digitized by a first A/D converter 2, and output as Xd. A driving clock 3, which is for driving the A/D converter 2, is input into the A/D converter 2.

[0079] The converted, digital data Xd is transmitted to a subsequent digital signal processing section, where the data is processed. As shown in FIG. 1, the digital signal processing section is made up of three units of a counting processing unit 4, a fraction processing unit 5, and an averaging processing unit 6.

[0080] The functions of the three units of the counting processing unit 4, the fraction processing unit 5, and the averaging processing unit 6 will now be described in order.

[0081] (Counting Processing Unit)

[0082] FIG. 2 is a block diagram of the counting processing unit 4.

[0083] The operation will be described in detail with reference to FIG. 3. Here, the horizontal axis represents the data number i at each sampling timing. Specifically, from the left in order (starting at i=0), data are received successively at a driving sampling rate of the first A/D converter 2, and subjected to processing. That is, the data interval in FIG. 3 corresponds to the driving sampling rate of the first A/D converter 2 (or, period of the driving clock 3).

[0084] Firstly, data Xd, obtained by digitizing the input signal X by the first A/D converter 2, corresponds to (A) in FIG. 3.

[0085] Here, the counting processing unit 4 uses a first zero-crossing identification means 41 to detect zero-crossing when the data Xd is switched from positive to negative or vice versa. For example, when a timing at which the data has crossed zero is detected in (A) in FIG. 3, a signal in FIG. 3 (B) is made to rise to take a positive logic immediately after the zero-crossing, at the data number corresponding to the time point when the data has passed zero. In this manner, zero-crossing can be detected.

[0086] Next, the signal shown in FIG. 3 (B) is input into a counter 43, where counting processing is performed.

[0087] The counter 43 counts up each time a detection signal is received from the first zero-crossing identification means 41. The value held by the counter 43 is as shown in FIG. 3 (C).

[0088] It should be noted that in the case where the input signal X has a frequency much smaller than the driving sampling rate of the first A/D converter 2, noise included in the input signal or in the first A/D converter 2 itself may cause misdetection of zero-crossing. Even in such a case, there is no problem because the misdetection can be ignored using a well-known algorithm.

[0089] (Fraction Processing Unit)

[0090] Next, the general outline of the fraction processing unit 5 is shown in FIG. 4.

[0091] The operation of the fraction processing unit 5 will now be described in detail with reference to FIGS. 5 and 6.

[0092] Firstly, the digital data row Xd, obtained by converting the input signal X by the first A/D converter 2, corresponds to FIG. 5 (A), which is precisely the same as FIG. 3 (A).

[0093] Next, linear interpolation computation processing is carried out. Specifically, a value (value B in FIG. 6) at the timing when zero-crossing of a measurement signal has been detected and a value (value A in FIG. 6) immediately before it are latched.

[0094] From these two data pieces, a linear interpolation computation as expressed by the expression 1 is performed.

|B|/(|A|+|B|)  (Expression 1)

[0095] The calculated value is held, in association with the timing immediately before the zero-crossing detection timing (i.e. the same timing as the value A in FIG. 6), as a calculated fraction value. This is illustrated in FIG. 5 (B).

[0096] In FIG. 5 (B), as zero-crossing has been detected for example at the data number 2 (see FIG. 3 (B)), the value at the data number 1 and the value at the data number 2 are used to perform the calculation of the expression 1 to obtain a calculated value (of approximately 0.5), which value is then associated with the time point of the data number 1. Similarly, the calculated fraction values are obtained at the time points of the data numbers 4, 7, 10, 14, and 17.

[0097] In this operation of the fraction processing unit 5, zero-crossing of the input signal X itself should be detected. The zero-crossing detection operation may be performed in the fraction processing unit 5 as independent zero-crossing detection processing. Alternatively, the operation may be implemented by transmitting a detection signal from the outside of the fraction processing unit 5, for example from the counting processing unit 4.

[0098] While this processing includes a division, generally in an FPGA, high-speed floating-point arithmetic (division) places heavy load. To reduce such load, a division using a “look-up table” may be applied.

[0099] A division using a look-up table is a technique known in the arithmetic operations by the FPGA. Specifically, for S of every value that the data can take (256 values in the case of 8 bits, for example), “×T” approximately equivalent to “÷S” is held in advance as a table (dictionary) in an internal memory. When a certain division “÷S” is to be done in the FPGA, the corresponding “×T” is extracted to do a multiplication instead, which is simpler than the division.

[0100] When a division using a look-up table is applied, the calculated fraction value will include an error from the exact value obtained from the expression 1. The calculated fraction value, however, corresponds to the correction term of the final result, which barely affects the final result. Therefore, such a replacement will not lead to deteriorated measurement accuracy.

[0101] (Averaging Processing Unit)

[0102] The operation of the averaging processing unit 6 will now be described.

[0103] The averaging processing unit 6 uses two data rows obtained from the counting processing unit 4 and the fraction processing unit 5 to perform arithmetic processing on the basis of the following expression 2.

[00001]$\begin{array}{cc}U=\frac{1}{N}.Math.\left(\underset{i=0}{\overset{N-1}{.Math.}}.Math..Math.C_i+\underset{j=1}{\overset{i}{.Math.}}.Math..Math.F_j^X\right)& \left[\mathrm{Expression}.Math..Math.2\right]\end{array}$

[0104] Firstly, the number N of averaging is determined from a rate at which data is desired to be obtained ultimately. That is, 1/N of the sampling rate of the A/D converter operation becomes the sampling rate at which the output data is obtained ultimately.

[0105] By way of example, N=20 hereinbelow, as shown in FIG. 7. That is, the number of the output values from the counting processing unit 4 and the fraction processing unit 5 that the averaging processing unit 6 uses per averaging processing is 20, with the data numbers i from 0 to 19.

[0106] The symbols in the expression 2 are defined as follows.

[0107] C.sub.i: an output value from the counting processing unit 4 (i.e. a value of the counter 43; see FIG. 7 (A)).

[0108] F.sup.X.sub.j: a calculated fraction value, calculated for the input signal X by the fraction processing unit 5 (FIG. 7 (B)). Here, j is the number attached to indicate the order of each output value. In the example shown in FIG. 7 (B), six points are plotted over the data numbers from 0 to 19, so j=1-6. That is, I=6 in the expression 2.

[0109] As explained above, in the example in FIG. 7, the addition/subtraction and division by N indicated by the expression 2 are performed with 20 pieces of C.sub.i and 6 pieces of F.sup.X.sub.j, to obtain an output value U from the averaging processing unit 6.

[0110] In the case where the above-described averaging processing is actually implemented in an FPGA, in order to ensure real-time performance, the processing may be performed in the following manner.

[0111] (1) At the timing corresponding to each data number, data pieces of C.sub.i, F.sup.X.sub.j, F.sup.Y.sub.k output from the counting processing unit 4 and the fraction processing unit 5 are transmitted to the averaging processing unit 6.

[0112] (2) The averaging processing unit 6 holds a value in its memory (with the initial value being zero), and at each timing, it adds the received data to the value held in the memory, and holds the resultant value until the next data reception timing. That is, a value S.sub.i held in the memory is according to the recurrence formula in the expression 3.

S.sub.i=S.sub.i-1+C.sub.i+F.sup.X  (Expression 3)

[0113] It should be noted that F.sup.X is used in the computation only when the value has been transmitted. At this time, the history of S.sub.i is as shown in FIG. 7 (C).

[0114] (3) Here, in the fraction processing unit 5, the calculated fraction value is associated with the timing immediately before the zero-crossing detection timing, as explained above. The calculated fraction value can be obtained only after the zero-crossing detection timing, so the timing needs to be adjusted.

[0115] To this end, a delay for M timings may be inserted before the addition/subtraction is performed in the averaging processing unit 6. M is an appropriate integer not smaller than 1 and sufficiently smaller than N.

[0116] With the delay inserted, the processing in (2) above can be performed after the calculation of the calculated fraction value F.sup.X.sub.j, at the expense of the delay for M timings of the value held in the memory.

[0117] The time delay for M timings, however, poses no problem because it is sufficiently smaller than the above-described sampling rate at which the output data will be obtained ultimately.

[0118] The time delay of course takes a known fixed value constantly. It is thus possible to compensate for the delay when accuracy in measurement time is desired.

[0119] (4) The addition/subtraction is repeated as in (2) above.

[0120] (5) With the processing in (4) continued, once the last data has been received, the value held at the time point corresponding to i=19 (last) is divided by N to obtain the value in the expression 2. Therefore, this value may be used as the ultimate output. After completion of this series of operations, the value held is reset to zero before starting the next series of operations.

[0121] Further, in the case where it is necessary to reduce the load of the division part of dividing with N, a power of two may be selected as N.

[0122] The output U from the averaging processing unit 6 and a desired phase φ (in radian) have a relationship expressed by the following expression 4.

φ=πU  (Expression 4)

[0123] More precisely, a constant ε is added to the right side of the expression 4. Theoretically, ε is a value that takes a value of π or zero, which is uniformly determined in accordance with the phase relationship of the input signal at the start of measurement.

[0124] In the case where phase measurement is performed successively, as in the phase measuring device of the present invention or in an apparatus using the device, the change in phase becomes a major parameter to be measured, so ε is a term that is ignorable and poses no problem on the measurement. That is, when the value of U calculated firstly after the start of measurement is represented as U.sub.0 and the subsequent value of U is represented as Un (n=1, 2, . . . ), Un−U.sub.0 is used as a measurement result. Thus, the presence of ç, which is added to both, poses no problem.

[0125] Here, φ is a phase (in radian) of the input signal X. The phase is measured with respect to the time point when the processing was started. When the output U is processed inside the FPGA or on the PC on the basis of this relationship, the phase (in radian) can be calculated.

[0126] In consideration of the processing in subsequent stages, it is of course possible to use the data U, as it is, in the processing in the subsequent stages, without converting it into a phase (in radian) as in the expression 4.

[0127] A measurement instrument that computes and outputs a result in real time is required to have a function of setting a time as a basis for starting measurement. That is, it is desired to have a function of setting a phase φ to zero at the time when a certain reset signal has been received during the operation, and computing the subsequent output data on the basis of that reference time. This function can readily be implemented by an operation of resetting the value of the counter in the counting processing unit to zero and/or initializing the processing in the averaging processing unit at the timing of reception of a reset signal.

[0128] Calculating a phase according to the processing as described above makes it possible to input a periodical signal in a wide frequency range, and to perform measurement with accuracy and in real time.

[0129] While the example of implementing the digital signal processing by an FPGA has been illustrated above, not only the FPGA, but also an ASIC, a system LSI, or any other method capable of realizing digital signal processing can implement the processing in a similar manner.

[0130] Further, while the input signal X has been assumed to be a sine wave signal, a pulse signal (also called a square wave signal) used in digital circuits can be converted into a sine wave signal by applying a band-pass filter or low-pass filter.

[0131] It is therefore possible to compose a phase measuring device for a pulse signal by disposing a band-pass filter in a stage preceding the phase measuring device.

[0132] Further, the calculated phase can be differentiated by time in processing in a subsequent stage, to convert it into a frequency of the input signal X. As such, even in the case where the device is used as a frequency counter, it can measure the frequency of a signal having a wide frequency variation range, while ensuring high resolution and real-time property. Supporting a wide frequency variation range can be stated differently that even for an input signal having large frequency noise, high-speed and reliable measurement is possible.

[0133] Next, the basic principles in the case of measuring a phase difference on the basis of the present invention, i.e. in the case of using the device as a phase difference measuring device, will be described with reference to the drawings.

[0134] Two periodical input signals for use in phase difference measurement will be hereinafter referred to as input signals X, Y. It should be noted that the elements and components common to those in the phase measuring device described above will be denoted by the same reference characters.

[0135] The general outline of signal processing performed by the phase difference measuring device 10 based on the present invention is shown in FIG. 8.

[0136] An input signal X and an input signal Y are digitized separately by a first A/D converter 2 and a second A/D converter 30, and output as Xd and Yd, respectively. The converted, digital data Xd, Yd are transmitted to a subsequent digital signal processing section, where the data are processed. As shown in FIG. 8, the digital signal processing section is made up of three units of a counting processing unit 4, a fraction processing unit 5, and an averaging processing unit 6.

[0137] The functions of the three units of the counting processing unit 4, the fraction processing unit 5, and the averaging processing unit 6 will now be described in order.

[0138] (Counting Processing Unit)

[0139] FIG. 9 is a block diagram of the counting processing unit 4.

[0140] The operation will be described in detail with reference to FIG. 10.

[0141] Here, the horizontal axis represents the data number i at each sampling timing. Specifically, from the left in order (starting at i=0), data are received successively at a driving sampling rate of the first A/D converter 2 and of the second A/D converter 30, and subjected to processing. That is, the data interval in FIG. 10 corresponds to the driving sampling rate of each A/D converter 2, 30.

[0142] Firstly, data Xd and Yd, obtained by digitizing the input signal X and the input signal Y by the first A/D converter 2 and the second A/D converter 30, correspond respectively to (A) and (C) in FIG. 10.

[0143] Here, the counting processing unit 4 uses a first zero-crossing identification means 41 to detect zero-crossing when the data Xd is switched from positive to negative or vice versa. For example, when a timing at which the data has crossed zero is detected in (A) in FIG. 10, a signal in FIG. 10 (B) is made to rise to take a positive logic immediately after the zero-crossing, at the data number corresponding to the time point when the data has passed zero. In this manner, zero-crossing can be detected.

[0144] Similarly, a second zero-crossing identification means 42 is used to perform zero-crossing processing on the data Yd. The signal obtained as a result is as shown in FIG. 10 (D).

[0145] Next, the signal shown in FIG. 10 (B) and the signal shown in FIG. 10 (D) are input into an up-down counter 44, where counting processing is performed.

[0146] For the up-down counter 44, a well-known counter is adopted which has a function of counting “1” when a detection signal is received from the first zero-crossing identification means 41, counting “−1” when a detection signal is received from the second zero-crossing identification means 42, and otherwise maintaining the value unchanged. It should be noted that the counting directions (positive and negative) may be set arbitrarily, because even when the positive and negative are set oppositely, they may be reversed in subsequent processing to obtain the same results.

[0147] The value held by the up-down counter 44 is as shown in FIG. 10 (E). This data row in FIG. 10 (E) is transmitted to the averaging processing unit 6 as counted values. This data row corresponds to C.sub.i (where i is the data number) in the expression 6 described later.

[0148] It should be noted that in the case where the input signals each have a frequency much smaller than the driving sampling rate of the corresponding A/D converter 2, 30, noise included in the input signal or in the A/D converter 2, 30 itself may cause misdetection of zero-crossing. Even in such a case, there is no problem because the misdetection can be ignored using a well-known algorithm, as in the case where the phase itself is measured as described earlier.

[0149] (Fraction Processing Unit)

[0150] Next, the general outline of the fraction processing unit 5 is shown in FIG. 11.

[0151] The operation of the fraction processing unit 5 will now be described in detail with reference to FIGS. 6 and 12.

[0152] Firstly, the digital data row Xd, obtained by converting the input signal X by the first A/D converter 2, corresponds to FIG. 12 (A), which is precisely the same as FIG. 10 (A).

[0153] Next, linear interpolation computation processing is carried out. Specifically, a value (value B in FIG. 6) at the timing when zero-crossing of a measurement signal has been detected and a value (value A in FIG. 6) immediately before it are latched. From these two data pieces, a linear interpolation computation as expressed by the expression 5 is performed.

|B|/(|A|+|B|)  (Expression 5)

[0154] The calculated value is held, in association with the timing immediately before the zero-crossing detection timing (i.e. the same timing as the value A in FIG. 6), as a calculated fraction value. This is illustrated in FIG. 12 (B).

[0155] In FIG. 12 (B), as zero-crossing has been detected for example at the data number 2 (see FIG. 10 (B)), the value at the data number 1 and the value at the data number 2 are used to perform the calculation of the expression 5 to obtain a calculated value (of approximately 0.5), which value is then associated with the time point of the data number 1. Similarly, the calculated fraction values are obtained at the time points of the data numbers 4, 7, 10, 14, and 17.

[0156] In this operation of the fraction processing unit 5, zero-crossing of each of the input signal X and the input signal Y themselves should be detected. The zero-crossing detection operation may be performed in the fraction processing unit 5 as independent zero-crossing detection processing. Alternatively, the operation may be implemented by transmitting a detection signal from the outside of the fraction processing unit 5, for example from the counting processing unit 4.

[0157] While this processing includes a division, generally in an FPGA, high-speed floating-point arithmetic (division) places heavy load. To reduce such load, a division using a “look-up table” may be applied.

[0158] A division using a look-up table is a technique known in the arithmetic operations by the FPGA. Specifically, for S of every value that the data can take (256 values in the case of 8 bits, for example), “×T” approximately equivalent to “÷S” is held in advance as a table (dictionary) in an internal memory. When a certain division “÷S” is to be done in the FPGA, the corresponding “×T” is extracted to do a multiplication instead, which is simpler than the division.

[0159] When a division using a look-up table is applied, the calculated fraction value will include an error from the exact value obtained from the expression 5. The calculated fraction value, however, corresponds to the correction term of the final result, which barely affects the final result. Therefore, such a replacement will not lead to deteriorated measurement accuracy.

[0160] For the input signal Y as well, the calculated fraction value is obtained in exactly the same manner as in the input signal X. The input signal Y is shown in FIG. 12 (C), and the calculated fraction values obtained are shown in FIG. 12 (D).

[0161] (Averaging Processing Unit)

[0162] The operation of the averaging processing unit 6 will now be described.

[0163] The averaging processing unit 6 uses two data rows obtained from the counting processing unit 4 and the fraction processing unit 5 to perform arithmetic processing on the basis of the following expression 6.

[00002]$\begin{array}{cc}\left[\mathrm{Expression}.Math..Math.6\right]& \\ U=\frac{1}{N}.Math.\left(\underset{i=0}{\overset{N-1}{.Math.}}.Math..Math.C_i+\underset{j=1}{\overset{i}{.Math.}}.Math..Math.F_j^X-\underset{k=1}{\overset{m}{.Math.}}.Math..Math.F_k^Y\right)& \left[\mathrm{Expression}.Math..Math.6\right]\end{array}$

[0164] Firstly, the number N of averaging is determined from a rate at which data is desired to be obtained ultimately. That is, 1/N of the sampling rate of the A/D converter operation becomes the sampling rate at which the output data is obtained ultimately.

[0165] By way of example, N=20 hereinbelow. That is, the number of the data pieces that the averaging processing unit 6 uses per averaging processing is 20, with the data numbers i from 0 to 19.

[0166] The symbols in the expression 6 are defined as follows.

[0167] C.sub.i: an output value from the counting processing unit 4 (i.e. a value of the up-down counter; see FIG. 13 (A)).

[0168] F.sup.X.sub.j: a calculated fraction value, calculated for the input signal X by the fraction processing unit 5 (FIG. 13 (B)). Here, j is the number attached to indicate the order of each output value. In the example shown in FIG. 13 (B), six points are plotted over the data numbers from 0 to 19, so j=1-6. This means I=6 in the expression 6.

[0169] F.sup.Y.sub.k: a calculated fraction value, calculated for the input signal Y by the fraction processing unit 5 (FIG. 13 (C)). Here, k is the number attached to indicate the order of each output value. In the example shown in FIG. 13 (C), four points are plotted over the data numbers from 0 to 19, so k=1-4. This means m=4 in the expression 6.

[0170] As explained above, in the example in FIG. 13, the addition, subtraction, and division by N, indicated by the expression 6, are performed with 20 pieces of C.sub.i, 6 pieces of F.sup.X.sub.j, and 4 pieces of F.sup.Y.sub.k, to obtain an output value U from the averaging processing unit 6.

[0171] In the case where the above-described averaging processing is actually implemented in an FPGA, in order to ensure real-time performance, the processing may be performed in the following manner.

[0172] (1) At the timing corresponding to each data number, data pieces of C.sub.i, F.sup.X.sub.j, F.sup.Y.sub.k output from the counting processing unit 4 and the fraction processing unit 5 are transmitted to the averaging processing unit 6.

[0173] (2) The averaging processing unit 6 holds a value in its memory (with the initial value being zero), and at each timing, it adds/subtracts the received data to/from the value held in the memory, and holds the resultant value until the next data reception timing. That is, a value S.sub.i held in the memory is according to the following recurrence formula.

S.sub.i=S.sub.i-1+C.sub.i+F.sup.X−F.sup.Y  (Expression 7)

[0174] It should be noted that F.sup.X and F.sup.Y are used in the computation only when the values have been transmitted. At this time, the history of S.sub.i is as shown in FIG. 13 (D).

[0175] (3) Here, in the fraction processing unit 5, the calculated fraction value is associated with the timing immediately before the zero-crossing detection timing, as explained above. The calculated fraction value can be obtained only after the zero-crossing detection timing, so the timing needs to be adjusted.

[0176] To this end, a delay for M timings may be inserted before the addition/subtraction is performed in the averaging processing unit 6. M is an appropriate integer not smaller than 1 and sufficiently smaller than N.

[0177] With the delay inserted, the processing in (2) above can be performed after the calculation of the calculated fraction values F.sup.X.sub.j, F.sup.Y.sub.k, at the expense of the delay for M timings of the value held in the memory.

[0178] The time delay for M timings, however, poses no problem because it is sufficiently smaller than the above-described sampling rate at which the output data will be obtained ultimately.

[0179] The time delay of course takes a known fixed value constantly. It is thus possible to compensate for the delay when accuracy in measurement time is desired, as in the case of measuring the phase itself as explained earlier.

[0180] (4) The addition/subtraction is repeated as in (2) above.

[0181] (5) With the processing in (4) continued, once the last data has been received, the value held at the time point corresponding to i=19 (last) is divided by N to obtain the value in the expression 6. Therefore, this value may be used as the ultimate output. After completion of this series of operations, the value held is reset to zero before starting the next series of operations.

[0182] Further, in the case where it is necessary to reduce the load of the division part of dividing with N, a power of two may be selected as N.

[0183] The output U from the averaging processing unit and a desired phase difference have a relationship expressed by the following expression 8.

Δφ=πU  (Expression 8)

[0184] More precisely, a constant ε is added to the right side of the expression 8. Theoretically, ε is a value that takes a value of π, −π, or zero, which is uniformly determined in accordance with the phase relationship of the input signals at the start of measurement. In the case where phase difference measurement is performed successively, as in the present invention or in an apparatus using the same, the change in phase difference becomes a major parameter to be measured, so ε is a term that is ignorable and poses no problem on the measurement. That is, when the value of U calculated firstly after the start of measurement is represented as U.sub.0 and the subsequent value of U is represented as Un (n=1, 2, . . . ), Un−U.sub.0 is used as a measurement result. Thus, the presence of ç, which is added to both, poses no problem.

[0185] Here, Δφ is a phase difference (in radian) between the input signal X and the input signal Y. The phase difference is measured with respect to the time point when the processing was started. When the output U is processed inside the FPGA or on the PC on the basis of this relationship, the phase difference (in radian) can be calculated.

[0186] In consideration of the processing in subsequent stages, it is of course possible to use the data U, as it is, in the processing in the subsequent stages, without converting it into a phase difference (in radian) as in the expression 8.

[0187] A measurement instrument that computes and outputs a result in real time is required to have a function of setting a time as a basis for starting measurement. That is, it is desired to have a function of setting a phase difference Δφ to zero at the time when a certain reset signal has been received during the operation, and computing the subsequent output data on the basis of that reference time. This function can readily be implemented by an operation of resetting the value of the up-down counter in the counting processing unit to zero and initializing the processing in the averaging processing unit at the timing of reception of a reset signal.

[0188] Calculating a phase difference according to the processing as described above makes it possible to input two periodical signals in a wide frequency range, and to perform measurement with accuracy and in real time.

[0189] While the example of implementing the digital signal processing by an FPGA has been illustrated above, not only the FPGA, but also an ASIC, a system LSI, or any other method capable of realizing digital signal processing can implement the processing in a similar manner.

[0190] Further, while the input signals X and Y have both been assumed to be a sine wave signal, a pulse signal (also called a square wave signal) used in digital circuits can be converted into a sine wave signal by applying a band-pass filter or low-pass filter.

[0191] It is therefore possible to compose a phase difference measuring device for a pulse signal by disposing a band-pass filter in a stage preceding the phase difference measuring device.

[0192] It should be noted that the present phase difference measuring device can readily be implemented by preparing two phase measuring devices and causing them to operate in parallel. That is, when the processing result by a phase measuring device 1 on an input signal X is represented as Ux and the processing result by a phase measuring device 2 on an input signal Y is represented as Uy, the phase difference can be calculated by Δφ=π(Ux−Uy). Theoretically, the phase difference measurement result obtained in this manner is precisely the same as the result obtained by the present phase difference measuring device, so both yield the same advantageous effects.

EXAMPLES

[0193] Examples of applications to specific apparatuses will now be described.

[Example 1] (Application to Laser Heterodyne Displacement Measuring Device)

[0194] In this example, the phase difference measuring device 10 of the present invention based on the above-described basic principles is applied to a laser heterodyne displacement measuring device. The present example will be described below, with a reference signal as the input signal X and a measurement signal as the input signal Y.

[0195] A laser heterodyne interferometer has widely been known as a measuring device utilizing the phase difference of laser light. In the laser heterodyne interferometer, laser light subjected to frequency shifting is used, and a phase difference between reflected light of the laser light from a measurement object and reference light is used to measure, for example, a displacement, or a displacement that occurs when vibration or shock is applied.

[0196] FIG. 14 shows the basic principles of a laser heterodyne interferometer.

[0197] In a displacement measuring device based on the laser heterodyne interferometer, a reference signal having a frequency of 80 MHz, for example, is input into a device, such as an AOM, that applies a frequency shift to laser light, and the resultant laser light frequency-shifted by 80 MHz is interfered with the laser light reflected from a measurement object, whereby a measurement signal is generated which has a phase modulation by a displacement of the measurement object added to 80 MHz.

[0198] In order to calculate the displacement from the two signals of the measurement signal and the reference signal, the phase difference measuring device 10 according to the present invention is applied to compose the laser heterodyne displacement measuring device.

[0199] Specifically, two sine wave input signals of the measurement signal and the reference signal are input into the phase difference measuring device 10 according to the present invention, to obtain output data U.

[0200] Here, the data U obtained in the averaging processing unit 6 and the displacement (d [m]) of the measurement object have a relationship as expressed by the expression 9, where X is a laser wavelength ([m]).

d=λU/4  (Expression 9)

[0201] When the output U is processed inside the FPGA or on the PC on the basis of this relationship, the displacement can be calculated in real time.

[0202] Although in the present example the reference signal as the input signal X is assumed to be the AOM driving signal and the measurement signal as the input signal Y is assumed to be the optical interference signal as shown in FIG. 14, there may be laser heterodyne interferometers of various other configurations. In general, however, they are based on the same principle that the phase difference measuring device 10 according to the present invention is used inside the laser heterodyne interferometers.

[0203] Therefore, irrespective of the illustration in FIG. 14, the phase difference measuring device portion inside the laser heterodyne interferometer can be replaced with the phase difference measuring device 10 according to the present invention, to obtain similar advantageous effects as in the present embodiment.

[0204] The phase difference measuring device according to the present invention has two merits of being high in accuracy and being capable of measurement even when the phase difference varies considerably. These merits correspond respectively to “measurement resolution” and “velocity range of a measurement object” in displacement measurement. Thus, the specific example of the present example and the conventional techniques will be compared in these two respects.

[0205] Firstly, parameters necessary for analysis are defined as follows.

[0206] (1) f.sub.h: a heterodyne beat frequency, which corresponds to the frequency of the reference signal in FIG. 14. In this example, it is set to 80 MHz.

[0207] (2) f.sub.ADC: a sampling rate for driving the A/D converter. In this example, it is set to 500 MHz.

[0208] (3) f.sub.s: a measurement sampling rate of the displacement data desired to be obtained. In this example, with N=20, f.sub.s=500/N=25 MHz.

[0209] It should be noted that in a general laser heterodyne displacement meter, the measurement sampling rate is normally within the range of 1 kHz to 1 MHz.

[0210] (4) V.sub.max: a maximum measurable velocity [m/s] of a measurement object.

[0211] (5) d.sub.r: measurement resolution [m].

[0212] (6) λ: a laser wavelength. In this example, it is set to 633 nm, which is the wavelength of a helium-neon laser often used for a displacement measuring instrument. It is of course possible to apply various other lasers.

[0213] Firstly, a conventional counting method, having a merit that it is adaptable even when the velocity range of a measurement object is high, will be compared with the present example in terms of measurement resolution.

[0214] The conventional counting method can measure only an integer value of the number of times of zero-crossing of the input signal (measurement signal, reference signal). Thus, in order to improve the resolution, a technique of multiplying the input signal using a PLL circuit or the like, a technique of averaging the values calculated in a plurality of times, or other technique is often adopted. At this time, the measurement resolution can be expressed by the following expression 10.

d.sub.r=λ/4LQ  (Expression 10)

[0215] Here, L is the multiplication rate by the PLL circuit, and Q is the number of averaging. In the commercially available products, LQ of at most about 1024 has been realized to achieve d.sub.r=λ/4096=about 0.155 nm.

[0216] This technique, however, requires a high-speed PLL circuit or the like, and suffers increased technical difficulty, so it is difficult to increase L. Although it may be conceivable to increase the number Q of averaging, in principle, Q is limited to at most about 2fh/fs, with no further prospect of improvement.

[0217] By comparison, according to the present example, it is possible to obtain the measurement resolution that is much higher than d.sub.r=λ/4096, the highest level of commercially available products, without using any PLL circuit.

[0218] That is, typically, the resolution can be expressed by the following expression 11.

d.sub.r=λ/(4N.Math.2.sup.n)  (Expression 11)

[0219] Here, n is the number of conversion bits of the A/D converter. Assuming that n=8 bits, the present example achieves d.sub.r=0.03 nm, with the number N of averaging being 20.

[0220] Assuming that f.sub.s=1 MHz, which has widely been used, with N=500, the following holds:

d.sub.r=0.0012 nm

[0221] This shows that the resolution obtained in the present example is better in the order of a hundredfold as compared to the resolution of about 0.155 nm by the counting method based on the conventional technique.

[0222] Next, a conventional demodulation method, which is good in measurement resolution, will be compared with the present example in terms of the velocity range of a measurement object.

[0223] In the demodulation method, it is necessary to adopt a low-pass filter that sets a frequency not greater than a half of the measurement sampling rate as a cut-off frequency f.sub.c according to the “sampling theorem” in the information theory. That is, it is necessary to satisfy the following expression 12.

f.sub.c<f.sub.s/2  (Expression 12)

[0224] Here, the cut-off frequency f.sub.c restricts the maximum measurable velocity, by the following expression 13.

(2v.sub.max)/λ=f.sub.c  (Expression 13)

[0225] From the above, the following expression 14 is derived.

v.sub.max=(λf.sub.s)/4  (Expression 14)

[0226] While a relatively high value of f.sub.s=1 MHz is now being adopted as the measurement sampling rate, it still places a limit of v.sub.max=about 0.16 m/s.

[0227] On the other hand, as to the velocity range of a measurement object according to the present example, an input signal having a frequency not greater than a half of the A/D converter sampling rate is measurable according to the sampling theorem. That is, the relationship between f.sub.ADC and v.sub.max is expressed by the following expression 15.

f.sub.ADC=2(2f.sub.h+4v.sub.max/λ)  (Expression 15)

[0228] Transposition yields the following.

v.sub.max=λ(f.sub.ADC−4f.sub.h)/8  (Expression 16)

[0229] Substituting the values now being used by way of example in the expression yields v.sub.max=14.2 m/s.

[0230] Comparison of this value with the velocity range v.sub.max=about 0.16 m/s in the demodulation method shows that the value obtained in Example 1 is greater in the order of a hundredfold.

[0231] The comparison with the conventional techniques will now be made in various respects other than the resolution and velocity range.

[0232] Firstly, in the method according to the present invention, real-time processing is possible even on a high-speed input signal. On the other hand, in the zero-crossing analysis method, the zero-crossing time of a signal is calculated from digitized data. This requires complicated calculations to be applied to the data temporarily held in a memory. Accordingly, it is not possible to perform real-time processing on a high-speed signal of 80 MHz, for example, as in the present example.

[0233] Further, in terms of tolerance to amplitude variation, the present invention is as strong as the counting method. On the other hand, the demodulation method is poor in this respect. Specifically, the method is undesirable because the output is sensitive when the signal amplitude varies, when the signal has been biased, when the signal has suffered distortion, etc.

[0234] The advantages of Example 1 as compared to the conventional techniques (demodulation method, counting method, zero-crossing method) as described above, from the standpoints of measurement resolution, velocity range of measurement object, capability of real-time processing, required clock speed, processing complexity, and tolerance to amplitude variation of signal, are listed in FIG. 15.

[0235] As such, while the conventional techniques each have disadvantages in certain perspectives, according to the present example, the requirements can be fulfilled in every respect.

[0236] In the case where a velocity signal of a measurement object is desired to be obtained, as in a laser Doppler vibrometer, it can readily be calculated by subjecting the displacement signal measured by the laser heterodyne displacement measuring device to temporal differentiation.

[Example 2] (Application to Phase Noise Measuring Device)

[0237] A phase noise measuring device is a device that measures a time history of phase fluctuation (noise) of a certain signal. The phase fluctuation is also called phase jitter, which is an important index for evaluating the stability of a high-frequency signal source. The phase noise measuring device is therefore an instrument indispensable to research and development on faster communication equipment and others.

[0238] In order to implement a phase noise measuring device by applying the present invention thereto, a measured signal may be used as the input signal in FIG. 1. In this case, the measurement performance of phase noise (self-noise of the phase noise measuring device itself) is determined according to the phase noise level of the A/D converter driving clock. Thus, when measurement with lower noise is desired, a high-stability reference signal may be introduced to the driving clock.

[0239] Alternatively, a measured signal and a high-stability reference signal may be input as the input signal X and the input signal Y, respectively, to the phase difference measuring device in FIG. 8. In this case, the phase noise of the measured signal can be measured without being affected by the phase noise level of the A/D converter driving clock.

[0240] FIG. 16 illustrates the application. Here, the high-stability reference signal refers to a periodical signal having extremely small phase noise, which signal can become the basis of measurement. It can be obtained by an atomic clock, for example.

[0241] While the measured signal and the high-stability reference signal have been set as the input signals X and Y, respectively, they may be set conversely as the input signals Y and X.

[0242] Applying the present invention makes the measurement possible even in the case where the measured signal and the high-stability reference signal considerably differ in frequency. Specifically, when the frequency of a measured signal is represented as f.sub.A and the sampling rate for driving the A/D converter as f.sub.ADC, measurement becomes possible in the range of f.sub.A<f.sub.ADC/4, and at the same time, the resolution of the phase noise measurement can be increased.

[0243] That is, when the number of conversion bits of the A/D converter is represented as n (for example, n=8 bits), the number of averaging as N, and the resolution of the phase noise as d (in radian), the following relationship holds: d=2π/(N.Math.2.sup.n).

[0244] Further, according to the present invention, highly reliable measurement is possible even in the case where the phase noise level of the measured signal is very large, i.e. when the phase variation exceeds 2π to a large extent, for example.

[0245] Specifically, the phase noise measuring devices according to the existing techniques include:

[0246] (A) those of highly accurate type, using a spectrum analyzer and PLL; and

[0247] (B) those of wide range type, performing A/D conversion and analysis as in an oscilloscope.

[0248] With (A), any signal having too large phase noise will become out of range, so the measurement thereof is impossible. On the other hand, according to the present technique, there is no problem because of the wide frequency range of the measured signal. With (B), while measurement is possible even for a signal having large phase noise, the memory capacity is limited, so the measurement becomes impossible in an area with low offset frequency where long-time data acquisition is necessary. The present technique supports real-time processing, thereby enabling highly reliable measurement even in the area where the offset frequency is extremely low.

[Example 3] (Application to PLL Circuit)

[0249] A PLL circuit, as shown in FIG. 17, is a circuit that generates a phase-locked output signal with respect to an input, periodical signal. In the circuit, feedback control as shown in FIG. 17 is performed by a phase comparator, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider.

[0250] In the present example, the portion of the phase comparator in this PLL circuit is replaced with the phase difference measuring device according to the present invention and a band-pass filter or low-pass filter.

[0251] Specifically, the phase difference measuring device according to the present invention outputs a phase difference in the form of digital value, so the loop filter is replaced with a digital controller, as shown in FIG. 18.

[0252] In the case where an input signal is a pulse signal, a band-pass filter or a low-pass filter is inserted in front of the PLL circuit, although such a filter is unnecessary when the input signal is a sine wave or similar periodical signal.

[0253] Applying the present invention to the PLL circuit yields the following advantages.

[0254] Firstly, the circuit operates even when there is a large frequency difference between the input signal X and the input signal Y of the phase difference measuring device.

[0255] In a normal PLL circuit, when the variable frequency range of the VCO is represented as Δf and the frequency dividing number as K, the range of the input signal kept under control of the PLL circuit is limited to Δf/K. In order to solve this problem, a complicated technique called a fractional PLL may be used to dynamically and meticulously change the frequency dividing number K.

[0256] On the other hand, in the case of the PLL circuit to which the present invention has been applied, when the frequency of the input signal is represented as f.sub.A and the sampling rate driving the A/D converter as f.sub.ADC, measurement is possible in a much wider range of f.sub.A<f.sub.ADC/4.

[0257] Secondly, it is possible to introduce a digital technology for shortening the time (called a lock-up time) taken from when a desired frequency is set until when the phase control is completed.

[0258] In the conventional PLL, in order to shorten the lock-up time, the design of the loop filter would be modified to adjust the feedback control characteristics.

[0259] On the other hand, in the case of the PLL circuit to which the present invention has been applied, the digital controller is used in place of the loop filter, so it is possible, for example, to flexibly change the control characteristics, or to adopt a kind of feedforward technique called “gear shift”.

[0260] It should be noted that the PLL circuit in the present example can be used as an FM demodulator, as in the case of a normal PLL circuit.

[0261] This is advantageous in that, with the advantageous effects of the present invention, the circuit operates even in the case where the frequency difference between the FM signal and the reference signal is large. Specifically, when the frequency of the measured signal is represented as f.sub.A and the sampling rate driving the A/D converter as f.sub.ADC, measurement is possible in the range of f.sub.A<f.sub.ADC/4. It is thus possible to configure an FM demodulator capable of direct demodulation even if the transition amount of frequency hopping of the FM signal is considerably large, without the need to do phase lock again.

[0262] While the case of applying the present invention to a digital PLL circuit has been illustrated in the present example, there is another kind of PLL circuit called a full digital PLL. Such a full digital PLL also includes a phase comparator, so the present invention is applicable thereto in a similar manner as in the present example.

INDUSTRIAL APPLICABILITY

[0263] As described above, the present invention, with a simple circuit configuration, allows input of periodical signals of a wide frequency range, and also enables measurement of a phase or a phase difference with accuracy, at equal time intervals, and in real time. Accordingly, it can be expected to be applicable to a laser heterodyne displacement measuring device, a phase noise measuring device, a PLL circuit, and various other apparatuses.

REFERENCE SIGNS LIST

[0264] 1: phase measuring device [0265] 2: first A/D converter [0266] 3: driving clock [0267] 4: counting processing unit [0268] 5: fraction processing unit [0269] 6: averaging processing unit [0270] 10: phase difference measuring device [0271] 30: second A/D converter [0272] 41: first zero-crossing identification means [0273] 42: second zero-crossing identification means [0274] 43: counter [0275] 44: up-down counter