IC with first and second functional circuits coupling only first circuits to output bond pads

Abstract

A family of digital logic functions has the same specifications for input and output voltages and the same number of bond pads. A digital logic integrated circuit for the family includes a substrate of semiconductor material having a core area and a peripheral area; a certain number of bond pads formed in the peripheral area, the certain number of bond pads determining the total area of the substrate; programmable digital logic transistor circuitry formed in the core area for each of the digital logic functions in the family; programmable input and output circuitry formed in the peripheral area; programming circuitry for programming the programmable digital logic transistor circuitry into a selected digital logic function; and programmable input and output means for programming the input and output circuitry into input and output circuits for the selected digital logic function.

Claims

1. An integrated circuit comprising: (a) a substrate of semiconductor material having a core area and a peripheral area; (b) bond pads formed in the peripheral area, the bond pads including first and second input bond pads and an output bond pad; (c) a first set of one or more functional circuits formed in the core area, each functional circuit of the first set having a first function, each functional circuit of the first set having respective first and second inputs coupled to the first and second input bond pads, and having a respective output coupled to the output bond pad; (d) a second set of one or more functional circuits formed in the core area, each functional circuit of the second set having a second function different than the first function, each functional circuit of the second set having respective first and second inputs and having a respective output; and (e) conductive material coupling the first and second input bond pads to the respective first and second inputs of the one or more functional circuits of the first set and coupling the output bond pad only to the respective output of the one or more functional circuits of the first set.

2. The integrated circuit of claim 1 in which the conductive material includes a strap.

3. The integrated circuit of claim 1 in which the conductive material includes a fuse.

4. The integrated circuit of claim 1 in which the conductive material includes metal.

5. The integrated circuit of claim 1 in which the conductive material includes an upper level metal.

6. The integrated circuit of claim 1 in which the first set of functional circuits includes one or more AND gates.

7. The integrated circuit of claim 1 in which the first set of functional circuits includes one or more OR gates.

8. The integrated circuit of claim 1 in which the first set of functional circuits includes one or more NAND gates.

9. The integrated circuit of claim 1 in which the first set of functional circuits includes one or more NOR gates.

10. The integrated circuit of claim 1 in which the second set of functional circuits includes one or more AND gates.

11. The integrated circuit of claim 1 in which the second set of functional circuits includes one or more OR gates.

12. The integrated circuit of claim 1 in which the second set of functional circuits includes one or more NAND gates.

13. The integrated circuit of claim 1 in which the second set of functional circuits includes one or more NOR gates.

14. The integrated circuit of claim 1 in which the first function is a first digital logic function and the second function is a second digital logic function.

15. The integrated circuit of claim 1 in which the conductive material includes multiplexer circuits coupling the output bond pad to the respective output of the one or more functional circuits of the first set.

16. The integrated circuit of claim 1 in which the conductive material couples the first and second input bond pads to the respective first and second inputs of the one or more functional circuits of the second set.

17. The integrated circuit of claim 1 including a third set of one or more functional circuits formed in the core area, each functional circuit of the third set having a third function different from the first and second functions, each functional circuit of the third set having respective first and second inputs coupled to the first and second input bond pads, and having a respective outputs.

18. The integrated circuit of claim 1 including: a third set of functional circuits formed in the core area, each functional circuit of the third set having a third function different from the first and second functions, each functional circuit of the third set having respective first and second inputs coupled to the first and second input bond pads, and having a respective output; and a fourth set of functional circuits formed in the core area, each functional circuit of the fourth set having a fourth function different from the first, second, and third functions, each functional circuit of the fourth set having respective first and second inputs coupled to the first and second input bond pads, and having respective output.

Description

BRIEF DESCRIPTION OF THE VIEWS OF THE DRAWINGS

(1) FIGS. 1A, 1B, and 1C, respectively are a symbol for an inverter, a function table for the inverter, and a plan view representation of an encapsulated integrated circuit inverter.

(2) FIGS. 2A, 2B, and 2C, respectively are a symbol for an AND gate, a function table for the AND gate, and a plan view representation of an encapsulated integrated circuit AND gate.

(3) FIGS. 3A, 3B, and 3C, respectively are a symbol for a NAND gate, a function table for the NAND gate, and a plan view representation of an encapsulated integrated circuit NAND gate.

(4) FIGS. 4A, 4B, and 4C, respectively are a symbol for an OR gate, a function table for the OR gate, and a plan view representation of an encapsulated integrated circuit OR gate.

(5) FIGS. 5A, 5B, and 5C, respectively are a symbol for a NOR gate, a function table for the NOR gate, and a plan view representation of an encapsulated integrated circuit NOR gate.

(6) FIGS. 6A, 6B, and 6C, respectively are a symbol for an EXCLUSIVE OR gate, a function table for the EXCLUSIVE OR gate, and a plan view representation of an encapsulated integrated circuit EXCLUSIVE OR gate.

(7) FIGS. 7A, 7B, and 7C, respectively are a symbol for a D-type flip flop, a function table for the D-type flip flop, and a plan view representation of an encapsulated integrated circuit D-type flip flop.

(8) FIGS. 8A, 8B, and 8C, respectively are a symbol for an octal D-type flip flop arrangement, a function table for each D-type flip flop of the octal arrangement, and a plan view representation of an encapsulated integrated circuit octal D-type flip flop arrangement.

(9) FIG. 9 is a plan view of an integrated circuit with 6 bond pads.

(10) FIG. 10 is a plan view of an integrated circuit with 8 bond pads.

(11) FIG. 11 is a plan view of an integrated circuit with 14 bond pads.

(12) FIG. 12 is a plan view of an integrated circuit with 20 bond pads.

(13) FIGS. 13A, 13B, and 13C, respectively are a symbol for a dual AND gate arrangement, a function table for the dual AND gate arrangement, and a plan view representation of an encapsulated integrated circuit dual AND gate arrangement.

(14) FIG. 14 is partial schematic diagram of an integrated circuit with selectable dual AND, OR, NAND, and NOR gates of the disclosure, using a multiplexer.

(15) FIG. 15 is partial schematic diagram of an integrated circuit with selectable dual AND, OR, NAND, NOR gates, and D-type flip flops of the disclosure, using a multiplexer.

(16) FIG. 16 is partial schematic diagram of an integrated circuit with selectable AND, OR, NAND, and NOR gates of the disclosure using a metal mask.

(17) FIG. 17 is partial schematic diagram of an integrated circuit with selectable AND, OR, NAND, and NOR gates of the disclosure using fuses.

(18) FIG. 18 is a partial schematic diagram of an integrated circuit with two AND gates, an OR gate, and a propagation delay buffer.

(19) FIG. 19 is a schematic diagram of metal mask connections for multiplex control signals S10, S11, S20, and S21.

(20) FIG. 20 is a schematic diagram of fuse connections for multiplex control signals S10, S11, S20, and S21.

(21) FIG. 21 is a schematic diagram of non-volatile memory providing multiplex control signals S10, S11, S20, and S21.

(22) FIG. 22 is a schematic diagram of an I.sup.2C serial connection to non-volatile memory providing for multiplex control signals S10, S11, S20, and S21.

(23) FIG. 23 is a plan view of a semiconductor die depicting a peripheral area for peripheral circuitry and a core area for core circuitry.

(24) FIG. 24 is a plan view of a semiconductor die depicting input and output circuitry in a peripheral area and logic and programming circuitry in a core area.

(25) FIG. 25 is a block diagram of a low voltage core, level shifting, and I/O cells.

(26) FIG. 26 is a flow chart for one process of making integrated circuits.

(27) FIG. 27 is a flow chart for another process of making integrated circuits.

DETAILED DESCRIPTION OF THE DISCLOSURE

(28) The problem of inventory and customer delivery time can be addressed with more efficiency using master designs for groups of digital logic functions in early semiconductor processing steps and differentiated late processing steps for the individual parts. The late processing steps can be the use of upper metal level layer straps, fuses, or non-volatile memory to select a desired logic function from the available group of logic functions.

(29) The digital logic families can be divided in to bond pad or package pin groups. For example, in one low voltage CMOS family the over 300 unique parts can be divided into groups having 6 bond pads, 8 bond pads, 14 bond pads, 16 bond pads, and 20 bond pads or pins. A design can fix the layout of the bond pad locations for each pin group using minimum bond pad areas to pass packaging rules. With present semiconductor process technologies usage, the minimum semiconductor die area is limited by the peripheral area of a die required for the bond pads.

(30) Using state of the art, sub-180 nm semiconductor process technology, digital density of 20 k+ transistor gates per mm.sup.2 is achievable for transistors operating at 3 or 5 volts. This density provides for multiple logic functions to be designed into a very small area of semiconductor material. In some cases the functions on 40 or more old logic dies may be designed onto a new, single base die. These functions can be designed into a core area of a semiconductor die with the bond pads in the peripheral area of the die.

(31) Designs can provide general purpose input, output, input/output (I/O) and electrostatic discharge (ESD) protection circuits connected to the bond pads for each family having the same input voltage high (VIH), input voltage low (VIL), output voltage high (VOH), output voltage low (VOL) requirements for all of the parts in the family. The designs can provide general purpose I/O circuits to be selected as an input or an output circuit via an I/O_SEL pin or feature. As such, any I/O circuit can be configured as an input or an output.

(32) The propagation delay between any input/output combination can be equalized, simplifying the data sheet, design, characterization and testing of each part in a family. The propagation delays can be equalized by adding redundant logic gates on fast circuit paths to make the delays approximately the same for every path. The layout can then be carefully planned out to make each circuit path have the approximately the same interconnect delay by making each circuit path follow the same repeated layout structure. The high density of the logic circuits makes this approach feasible by trading off layout area efficiency for equalized repeating layout structures.

(33) Using non-volatile memory for programming master parts has significant benefits since parts can be programed at final test, simplifying wafer production and reducing inventory. Using non-volatile memory, all functions within a pin group can be designed with a single mask design.

(34) Entering into a non-volatile program mode can be enabled by triggering a test mode of the part. The availability of programmable input and output circuits in these logic devices makes a test mode design feasible, and different test mode schemes can be implemented. An example is a test mode scheme where a semiconductor device enters test mode by pulling one of the I/Os above Vcc. At this point, other two I/Os can be used as a serial data input and a serial clock input. These types of schemes can be implemented with few hundreds of transistor gates leaving enough area for implementing product operating logic functions.

(35) Some design combinations may use both lower-voltage and higher density transistor gates for the I/O circuits and the core operating circuits. These lower voltage transistor gates could operate at such as 1.2 volts, 1.8 volts, or lower below a supply voltage VDD. In this case, an internal sub-μA low drop out (LDO) voltage regulator is designed in the IC and the operating logic and any non-volatile memory is run at a lower voltage VDDL level. Level shifting circuits could be used between IO circuits and the digital core logic circuits.

(36) FIG. 14, in accordance with the disclosure, depicts a partial schematic diagram of an integrated circuit 1400 with selectable dual AND, OR, NAND, and NOR gates using multiplexers. IC 1400 includes 1A input bond pad 1402, 1B input bond pad 1404, 1Y output bond pad 1406, 2A input bond pad 1408, 2B input bond pad 1410, and 2Y output bond pad 1412. Lead 1414 connects the 1A input bond pad 1402 to the A inputs of AND gate 1416, OR gate 1418, NAND gate 1420, and NOR gate 1422. Lead 1424 connects the 1B input bond pad 1404 to the B inputs of AND gate 1416, OR gate 1418, NAND gate 1420, and NOR gate 1422.

(37) Lead 1426 connects the Y output of AND gate 1416 to an input of multiplexer 1428. Lead 1430 connects the Y output of OR gate 1418 to an input of multiplexer 1428. Lead 1432 connects the Y output of NAND gate 1420 to an input of multiplexer 1428. Lead 1434 connects the Y output of NOR gate 1422 to an input of multiplexer 1428. Lead 1436 connects the output of multiplexer 1428 to 1Y output bond pad 1406.

(38) IC 1400 also includes 2A input bond pad 1408, 2B input bond pad 1410, and 2Y output bond pad 1412. Lead 1437 connects the 2A input bond pad 1408 to the A inputs of AND gate 1438, OR gate 1440, NAND gate 1442, and NOR gate 1444. Lead 1446 connects the 2B input bond pad 1410 to the B inputs of AND gate 1438, OR gate 1440, NAND gate 1442, and NOR gate 1444.

(39) Lead 1448 connects the Y output of AND gate 1438 to an input of multiplexer 1450. Lead 1452 connects the Y output of OR gate 1440 to an input of multiplexer 1450. Lead 1454 connects the Y output of NAND gate 1442 to an input of multiplexer 1450. Lead 1456 connects the Y output of NOR gate 1444 to an input of multiplexer 1450. Lead 1458 connects the output of multiplexer 1450 to 2Y output bond pad 1412.

(40) Multiplexer 1428 has two control input leads, S10 control input lead 1460 and S11 control input lead 1462. Multiplexer 1450 has two control input leads, S20 control input lead 1464 and S21 control input lead 1466. Multiplexers 1428 and 1450, depending on the binary combination of the logic states on the S10, S11, S20, S21 control signal leads 1460-1466, each selectably connect one of the Y outputs of the gates to the output bond pads 1406 and 1412. The source of the control signals on the control input leads will be described in later figures.

(41) IC 1400 also has a Vcc bond pad 1468 and a GND bond pad 1470.

(42) In one design and in one package with the 1A, 1B, 1Y, 2A, 2B, 2Y, Vcc and GND bond pads connected to external pins in an eight pin package, IC 1400 selectably provides one of four logical functions of dual AND gates 1416 and 1438, or dual OR gates 1418 and 1440, or dual NAND gates 1420 and 1442, or dual NOR gates 1422 and 1444, depending upon the control signals occurring on control input leads 1460, 1462, 1464, and 1466.

(43) In the same design and with only the 1A, 1B, 1Y, Vcc and GND bond pads connected to external pins in a five pin package, IC 1400 selectably provides one of four logical functions of a single dual input AND gate 1416, or a single dual input OR gate 1418, or a single dual input NAND gate 1420, or a single dual input NOR gate 1422, depending upon the control signals occurring on control input leads 1460 and 1462.

(44) In the same design and with only the 2A, 2B, 2Y, Vcc, and GND bond pads connected to external pins in a five pin package, IC 1400 selectably provides one of four logical functions of a single dual input AND gate 1438, or a single dual input OR gate 1440, or a single dual input NAND gate 1442, or a single dual input NOR gate 1444, depending upon the control signals occurring on control input leads 1464 and 1466.

(45) Depending upon the binary combination of logic states on the S10, S11, S20, and S21 control signal leads, 1460-1466, IC 1400 selectably provides the logical function of single, dual input AND gate 200, single, dual input NAND gate 300, single, dual input OR gate 400, single, dual input NOR gate 500, or dual, dual input AND gate 1300 in this one design. In one package, IC 1400 can provide any one of at least eight logical functions, as follows:

(46) dual AND gates 1416, 1438;

(47) dual OR gates 1418, 1440;

(48) dual NAND gates 1420, 1442;

(49) dual NOR gates 1422, 1444;

(50) a single, dual input AND gate;

(51) a single, dual input OR gate;

(52) a single, dual input NAND gate;

(53) a single, dual input NOR gate;

(54) or any combination of single, dual input gates desired.

(55) This arrangement of logical functions in one design reduces engineering design time by designing eight selectable parts at one time, instead of designing eight separate parts. This arrangement of logical functions in one design also reduces inventory and time to deliver a customer order. By making IC 1400 only to an intermediate manufacturing step, keeping only that intermediate product in inventory, and later finishing manufacturing by selecting the desired logical function according to a customer order, this design can reduce inventory requirements and time to delivery after the customer order.

(56) FIG. 15, in accordance with the disclosure, depicts a partial schematic diagram of an integrated circuit 1500 with selectable dual AND, OR, NAND, and NOR gates and D-type flip flops using multiplexers. IC 1500 is the same as IC 1400 with an addition of D-type flip flops 1502 and 1504 and the replacement of the multiplexers 1428 and 1450 with multiplexers 1506 and 1508.

(57) Lead 1414 connects the 1A input bond pad 1402 to the D input of D-type flip flop 1502. Lead 1424 connects the 1B input bond pad 1404 to the C inputs of D-type flip flop 1504. Lead 1510 connects the Q output of D-type flip flop 1502 to an input of multiplexer 1506.

(58) Lead 1437 connects the 2A input bond pad 1408 to the D input of D-type flip flop 1504. Lead 1446 connects the 2B input bond pad 1410 to the C input of D-type flip flop 1504. Lead 1512 connects the Q output of D-type flip flop 1504 to an input of multiplexer 1508.

(59) Multiplexer 1506 has three control input leads, S10 control input lead 1514, S11 control input lead 1516, and S12 control input lead 1518. Multiplexer 1508 has three control input leads, S20 control input lead 1520, S21 control input lead 1522, and S22 control input lead 1524. Multiplexers 1506 and 1508, depending on the control signals, each selectably connect one of the Y outputs of the gates or the Q outputs of the D-type flip flops to the output bond pads 1406 and 1412. The source of the control signals on the control input leads will be described in later figures.

(60) IC 1500 also has a Vcc bond pad 1468 and a GND bond pad 1470.

(61) In one design and in one package with the 1A, 1B, 1Y, 2A, 2B, 2Y, Vcc and GND bond pads connected to external pins in an eight pin package, IC 1400 selectably provides one of four logical functions of dual AND gates 1416 and 1438, or dual OR gates 1418 and 1440, or dual NAND gates 1420 and 1442, or dual NOR gates 1422 and 1444, or dual D-type flip flops 1506 and 1508, depending upon the binary combination of control signals occurring on the S10, S11, S12, S20, S21, S22 control input leads 1514, 1516, 1518, 1520, 1522, and 1524.

(62) In the same design and with only the 1A, 1B, 1Y, Vcc and GND bond pads connected to external pins in a five pin package, IC 1400 selectably provides one of four logical functions of a single dual input AND gate 1416, or a single dual input OR gate 1418, or a single dual input NAND gate 1420, or a single dual input NOR gate 1422, or a single D-type flip flop 1506, depending upon the control signals occurring on control input leads 1514, 1516, and 1518.

(63) In the same design and with only the 2A, 2B, 2Y, Vcc, and GND bond pads connected to external pins in a five pin package, IC 1400 selectably provides one of four logical functions of a single dual input AND gate 1438, or a single dual input OR gate 1440, or a single dual input NAND gate 1442, or a single dual input NOR gate 1444, or a single D-type flip flop 1508, depending upon the control signals occurring on control input leads 1520, 1522, and 1524.

(64) IC 1500 selectably provides the logical function of single, dual input AND gate 200, or single, dual input NAND gate 300, or single, dual input OR gate 400, or single, dual input NOR gate 500, or dual, dual input AND gate 1300, or D-type flip flop 700 in this one design. In one package, IC 1500 can provide any one of at least ten functions, as follows:

(65) dual AND gates 1416, 1438;

(66) dual OR gates 1418, 1440;

(67) dual NAND gates 1420, 1442;

(68) dual NOR gates 1422, 1444;

(69) dual D-type flip flops 1506, 1508;

(70) a single, dual input AND gate;

(71) a single, dual input OR gate;

(72) a single, dual input NAND gate;

(73) a single, dual input NOR gate;

(74) a single D-type flip flop;

(75) or any combination of single, dual input gates desired.

(76) The binary combination of three control signals for each multiplexer 1506 and 1508 occurring on the S10, S11, S12, S20, S21, S22 control input leads 1514, 1516, 1518, 1520, 1522, and 1524 selects up to eight different inputs for connection to output leads 1436 and 1458. Although FIG. 15 depicts the multiplexers selecting one of only five logic functions, the three control signals could select up to eight logic functions for connection to output leads 1436 and 1458. With multiplexers having more control signal inputs, more logic functions could be included in an IC design and be individually selected by the control signals.

(77) FIG. 16, in an alternative implementation, depicts a partial schematic diagram of an integrated circuit 1600 with selectable AND, OR, NAND, and NOR gates. IC 1600 is similar to IC 1400 but with alternative open connections between the Y outputs and the 1Y bond pad 1406. One selected open connection is closed with such as a metal mask connection during the manufacturing process.

(78) Lead 1602 connects 1Y bond pad 1406 to open connection terminals 1604, 1606, 1608, and 1610. Lead 1612 connects the Y output of AND gate 1416 to open connection terminal 1614. Lead 1616 connects the Y output of OR gate 1418 to open connection terminal 1618. Lead 1620 connects the Y output of NAND gate 1420 to open connection terminal 1620. Lead 1624 connects the Y output of NOR gate 1422 to open connection terminal 1626.

(79) During a manufacturing step, one of the open connections, formed by the pairs of open connection terminals, is closed to select the finished function for IC 1600. The closing can be implemented by adding a metal or other conductive material strap, such as strap 1630 connecting a pair of open connection terminals.

(80) FIG. 17, in an alternative implementation, depicts a partial schematic diagram of an integrated circuit 1700 with selectable AND, OR, NAND, and NOR gates. IC 100 is similar to IC 1400 but with fuses between the Y outputs and the 1Y bond pad 1406. One selected open fuse is closed or three selected closed fuses are opened during the manufacturing process.

(81) Lead 1702 connects 1Y bond pad 1406 to one side of fuses 1704, 1706, 1708, and 1710. Lead 1714 connects the Y output of AND gate 1416 to the other side of fuse 1704. Lead 1716 connects the Y output of OR gate 1418 to the other side of fuse 1706. Lead 1718 connects the Y output of NAND gate 1420 to the other side of fuse 1708. Lead 1720 connects the Y output of NOR gate 1422 to the other side of fuse 1710.

(82) Fuses 1704, 1706, 1708, and 1710 can be implemented in either open type or closed type. An open type fuse can be closed in manufacturing with such as a laser beam. A closed type fuse can be opened in manufacturing with such as a laser beam during manufacturing.

(83) During a manufacturing step, one of the open fuses is closed to select the finished function for IC 1700. Alternatively, selected ones of the closed fuses are opened to select the finished function for IC 1700.

(84) FIG. 18, in an alternative implementation, depicts a partial schematic diagram of an integrated circuit 1800 with two AND gates, an OR gate, and a propagation delay buffer.

(85) IC 1800 has a 1A input bond pad 1802, a 1B input bond pad 1804, 1Y output bond 1806, and 2Y output bond pad 1808. Lead 1810 connects the 1A input bond pad 1802 to the A inputs of AND gates 1814 and 1816. Lead 1812 connects the 1B input bond pad to the B inputs of AND gated 1814 and 1816. Lead 1818 connects the Y output of AND gate 1814 to the A input of OR gate 1820. Lead 1822 connects the Y output of AND gate 1816 to the B input of OR gate 1820 and to the input of delay buffer 1824. Lead 1826 connects the output of delay buffer 1824 to the 1Y output bond pad 1806. Lead 1828 connects the Y output of OR gate 1820 to the 2Y output bond pad 1808.

(86) The purpose of the two AND gates and one OR gate is to provide the logical function of the combination. The purpose of the delay buffer 1824 is to provide a propagation delay t.sub.pd to the 1Y output bond pad 1806 that approximates the propagation delay t.sub.pd to the 2Y output bond pad 1808 introduced by the OR gate 1820. With the delay buffer 1824, the outputs at the 1Y and 2Y bond pads will appear at approximately the same times. In complex functions of the logic circuitry such a delay buffer with a certain propagation delay can be implemented as needed to obtain a desired timing of output signals.

(87) FIG. 19 depicts an alternative arrangement 1900 using open connections providing multiplexer control signals S10, S11, S20, and S21 of FIG. 14. Lead 1902 connects a logic “H” to open connection terminals 1906, 1908, 1910, and 1912. Lead 1904 connects a logic “L” to open connection terminals 1914, 1916, 1918, and 1920. S10 lead 1460 connects to open connection terminals 1922 and 1924. S11 lead 1462 connects to open connection terminals 1926 and 1928. S20 lead 1464 connects to open connection terminals 1930 and 1932. S21 lead 1466 connects to open connection terminals 1934 and 1936.

(88) During a manufacturing step, four of the open connections, formed by the pairs of open connection terminals, is closed to select the finished function for an IC. The closing can be implemented by adding a metal or other conductive material strap, such as straps 1940 and 1942 connecting a pair of open connection terminals.

(89) FIG. 20 depicts an alternative arrangement 2000 using fuses to provide multiplexer control signals S10, S11, S20, and S21. Arrangement 2000 is similar to arrangement 1900, but replacing the open connection terminals with fuses.

(90) Lead 1902 connects a logic “H” to one side of fuses 2002, 2004, 2006, and 2008. Lead 1904 connects a logic “L” to one side of fuses 2010, 2012, 2014, and 2016. S10 lead 1460 connects to the other sides of fuses 2002 and 201. S11 lead 1462 connects to the other sides of fuses 2004 and 2012. S20 lead 1464 connects to the other sides of fuses 2006 and 2014. S21 lead 1466 connects to the other sides of fuses 2008 and 2016.

(91) Fuses 2002 through 2016 can be implemented in either open type or closed type. An open type fuse can be closed in manufacturing with such as a laser beam. A closed type fuse can be opened in manufacturing with such as a laser beam during manufacturing.

(92) During a manufacturing step, four of the open fuses are closed to select the finished function for an IC. Alternatively, selected ones of the closed fuses are opened to select the finished function for an IC.

(93) FIG. 21 depicts an alternative arrangement 2100 using non-volatile memory to provide multiplexer control signals S10, S11, S20, and S21. Arrangement 2100 has a non-volatile memory 2102, program (PGM) input bond pad 2104, BIT 0 input bond pad 2106, BIT 1 input bond pad 2108, BIT 2 input bond pad 2110, BIT 3 input bond pad 2112, and program voltage (PGM VOLT) input bond pad 2114.

(94) Leads 2116 through 2126, respectively, connect the input bond pads 2104 through 2114 to inputs of the non-volatile memory 2102. The S10, S11, S20, and S21 control leads 1460 through 1466 also are connected to outputs of the non-volatile memory 2102.

(95) In operation, non-volatile memory 2102 is programmed to provide a desired control signal on the S10, S11, S20, and S21 outputs. Programming can occur by activating the program input bond pad 2104, providing a programming voltage on input bond pad 2114 and desired programming BITS 0-3 on input bond pads 2106 through 2112. Programming would occur late in the manufacturing process to reduce inventory of differentiated parts. The programming would determine the function of the finished logic part.

(96) Bond pads 2104 through 2114 would not have to be additional bond pads on an integrated circuit but could be the functional input and output bond pads for a finished product that are placed in a programming mode by such as an over voltage on one bond pad. After programming the non-volatile memory, the programming bond pads would revert to normal functional bond pads.

(97) FIG. 22 depicts an alternative arrangement 2200 using non-volatile memory and an I.sup.2C interface to provide multiplexer control signals S10, S11, S20, and S21. Arrangement 2200 is similar to arrangement 2100, but uses an I.sup.2C interface to program the non-volatile memory. Arrangement 2200 has non-volatile memory 2202, an SDA input bond pad 2204, a SCK input bond pad 2206, and an I.sup.2C interface circuit 2208.

(98) Lead 2210 connects the SDA input bond pad to the SDA input of the I.sup.2C interface circuitry 2208. Lead 2212 connects the SCK input bond pad to the SCK input of the I.sup.2C interface circuitry. Lead 2214 connects the O parallel outputs of I.sup.2C interface circuitry to the I parallel inputs of non-volatile memory 2202.

(99) In operation, programming bits are transferred into the non-volatile memory 2202 through the I.sup.2C interface circuitry over the SDA and SCK input bond pads. Again, bond pads 2114, 2204, 2206 would not have to be additional bond pads on an integrated circuit, but could be the functional input and output bond pads for a finished product that are placed in a programming mode by such as an over voltage on one bond pad. After programming the non-volatile memory, the programming bond pads would revert to normal functional bond pads.

(100) FIG. 23 depicts a semiconductor die 2300 having a peripheral area 2302 and a core area 2304.

(101) FIG. 24 depicts the semiconductor die 2300 as having input and output circuitry in the peripheral area 2302. The input and output circuitry can include input and output bond pads, input circuitry, output circuitry, and ESD protection circuitry. Die 2300 has functional logic and programming circuitry in the core area 2304.

(102) FIG. 25 depicts an IC 2500 having a VDD voltage source lead 2502, a sub-μA LDO voltage regulator circuit 2504, I/O circuits 2506, level shifter circuits 2508, core circuitry 2510, VDDL low voltage supply lead 2512, and logic connection leads 2514. The LDO voltage regulator circuit receives the VDD supply voltage, such as 3.3 volts, from the source lead 2502 and provides the VDDL low voltage at such as 1.2 volts or 1.8 volts to the core circuits 2510 and the level shifting circuits 2508. The I/O circuits and the level shifter circuits receive the supply voltage VDD from source lead 2502. Logic connections 2514 provide communication between the level shifter circuits 2508 and the core circuits 2510.

(103) In IC 2500, the core circuits 2510 can be implemented in high density, low voltage transistor gates using advanced semiconductor process technologies to include multiple logic functions in one design. Not only does the high density reduce the semiconductor area required for each logic function, the low voltage operation also reduces power consumption, providing further advance in the supply of digital logic function products.

(104) In FIG. 26, flow chart 2600 describes one process for making ICs according to the disclosure. In step 2602, the process partially fabricates a semiconductor die to an intermediate process step. The semiconductor die has a certain number of bond pads. The die also has logic function, input, and output circuits for that certain number of bond pads. The die also has incomplete logic function selection structure.

(105) In step 2604, the partially fabricated die is tested. In step 2606 the partially fabricated die is placed in inventory. In step 2608, a customer order for a specific logic function is received.

(106) In step 2610, the process finishes fabricating the semiconductor die with final selection structure to select the specific logic function, input(s), and output(s), from the multiple, available logic function circuits, input circuits, and output circuits in the die to fulfill the customer order. In step 2612 the finished die is encapsulated, tested, and delivered to the customer.

(107) The process of FIG. 26 reduces the inventory of logic function ICs by partially fabricating a semiconductor die for a certain number of bond pads, which limit the smallness of the die or require that the die be of a certain minimum size. The bond pads are fabricated in the peripheral area of the die. The partially fabricated die also includes as many logic function, input, and output circuits as can operate with that certain number of bond pads and as can be fabricated in the core area of the die. The partially fabricated die also includes incomplete selection structure, such as open connections between leads or closed or open fuses.

(108) The partially fabricated die is then tested and placed in inventory. The multiple logic functions available in the partially fabricated die reduce the number of different die that must be kept in inventory.

(109) When a customer order for a specific logic function is received, the partially finished die is removed from inventory and finished with selection structure, such as with the metal layer straps closing the open connections between leads or by opening or closing fuses as was previously described, to obtain the ordered specific logic function. The die is then encapsulated, tested, and delivered to the customer.

(110) Although the description in this disclosure has particularly described open connections, straps, and open or closed fuses as selection structures, these selection structures may be replaced with any structure providing a selectable switch function.

(111) In FIG. 27, flow chart 2700 describes another process for making ICs according to the disclosure. In step 2702, the process fabricates an encapsulated IC to have a certain number of bond pads. The die also has logic function, input, and output circuits for that certain number of bond pads. The die also has logic function selection circuits. In step 2704, the encapsulated IC is tested, and in step 2706 the encapsulated IC is placed in inventory. At this step or point, the IC has no logic function at the package pins.

(112) In step 2708, a customer order for a specific logic function is received.

(113) In step 2710, the selection circuits, such as a non-volatile memory using such as a parallel interface or a serial I.sup.2C interface, of the encapsulated IC are electrically programmed to select from the multiple, available logic function circuits, input circuits, and output circuits in the die to obtain the logic function to fulfill the customer order. The electrical programming occurs as described earlier concerning the non-volatile memory.

(114) In step 2712, the logic function parts are delivered to the customer.

(115) The process of FIG. 27 reduces the inventory of logic function ICs by fabricating encapsulated ICs having a certain number of bond pads, which limit the smallness of the die or require that the die be of a certain minimum size. The bond pads are fabricated in the peripheral area of the die. The partially fabricated die also includes as many logic function, input, and output circuits as can operate with that certain number of bond pads and as can be fabricated in the core area of the die. The encapsulated IC also includes selection circuits, such as non-volatile memory with a parallel or serial interface.

(116) The encapsulated IC is then tested and placed in inventory. The multiple logic functions available in the IC reduce the number of different ICs that must be kept in inventory. At this step or point, the encapsulated IC provides no logic function.

(117) When a customer order for a specific logic function is received, the encapsulated IC is removed from inventory and the non-volatile memory is electrically programmed as was previously described, to obtain the ordered specific logic function. The programmed IC is then delivered to the customer.

(118) In a broader sense, any mechanical or electrical programming function or structure, other than open connections and straps, fuses, or non-volatile memory, that can be maintained during the life of the IC comes within the scope of this disclosure for selecting a logic function from the available, multiple logic functions of the die or IC.

(119) The figures and text describe simple implementations of the disclosure. More complex combinations and other similar implementations are possible using these examples and explanations.