INRUSH CURRENT PREVENTION CIRCUIT

Abstract

An inrush current prevention circuit, according to one possible configuration, includes: a power supply input terminal; a high-resistance element to restrict an inrush current flowing in when a power supply voltage is applied to the power supply input terminal; a low-resistance bypass element connected in parallel with the high-resistance element and configured to operate so as to cause current to bypass the high-resistance element when an output voltage being output from the inrush current prevention circuit to a load exceeds a bypass threshold; and bypass threshold setting circuit that divides the power supply voltage in accordance with the output voltage, and sets the bypass threshold in accordance with a voltage value of a voltage dividing point of the bypass threshold setting circuit.

Claims

1. An inrush current prevention circuit comprising: a power supply input terminal; a high-resistance element to restrict an inrush current flowing in when a power supply voltage is applied to the power supply input terminal; a low-resistance bypass element connected in parallel with the high-resistance element and configured to operate so as to cause current to bypass the high-resistance element when an output voltage being output from the inrush current prevention circuit to a load exceeds a bypass threshold; and a bypass threshold setting circuit that divides the power supply voltage in accordance with the output voltage, and sets the bypass threshold in accordance with a voltage value of a voltage dividing point of the bypass threshold setting circuit.

2. The inrush current prevention circuit according to claim 1, wherein the bypass threshold setting circuit includes: a first comparator that compares a value corresponding to the output voltage and a first threshold; a first switching element that operates in accordance with an output signal of the first comparator when the output voltage corresponding value exceeds the first threshold; and a voltage dividing circuit that divides the power supply voltage in accordance with an operation of the first switching element, and the voltage dividing point is in the voltage dividing circuit, and the value of the voltage dividing point is set as the bypass threshold when the output voltage corresponding value exceeds the first threshold.

3. The inrush current prevention circuit according to claim 2, wherein the output voltage corresponding value is a voltage resulting from the output voltage to the load being divided, and the first threshold is set in accordance with a lower limit value of a rated input voltage range.

4. The inrush current prevention circuit according to claim 2, wherein the first threshold is set lower than a minimum operating voltage of the load.

5. The inrush current prevention circuit according to claim 3, wherein the first threshold is set lower than a minimum operating voltage of the load.

6. The inrush current prevention circuit according to claim 2, further comprising: a second comparator that compares the output voltage to the load and the bypass threshold; and a second switching element that operates in accordance with an output signal of the second comparator when the output voltage exceeds the bypass threshold, wherein the bypass element bypasses the high-resistance element in accordance with an operation of the second switching element.

7. The inrush current prevention circuit according to claim 3, further comprising: a second comparator that compares the output voltage to the load and the bypass threshold; and a second switching element that operates in accordance with an output signal of the second comparator when the output voltage exceeds the bypass threshold, wherein the bypass element bypasses the high-resistance element in accordance with an operation of the second switching element.

8. The inrush current prevention circuit according to claim 4, further comprising: a second comparator that compares the output voltage to the load and the bypass threshold; and a second switching element that operates in accordance with an output signal of the second comparator when the output voltage exceeds the bypass threshold, wherein the bypass element bypasses the high-resistance element in accordance with an operation of the second switching element.

9. The inrush current prevention circuit according to claim 5, further comprising: a second comparator that compares the output voltage to the load and the bypass threshold; and a second switching element that operates in accordance with an output signal of the second comparator when the output voltage exceeds the bypass threshold, wherein the bypass element bypasses the high-resistance element in accordance with an operation of the second switching element.

10. The inrush current prevention circuit according to claim 6, wherein the second comparator has hysteresis characteristics.

11. The inrush current prevention circuit according to claim 7, wherein the second comparator has hysteresis characteristics.

12. The inrush current prevention circuit according to claim 8, wherein the second comparator has hysteresis characteristics.

13. The inrush current prevention circuit according to claim 9, wherein the second comparator has hysteresis characteristics.

14. The inrush current prevention circuit according to claim 6, comprising a delay circuit to delay the output signal of the second comparator and to apply the delayed output signal to the second switching element.

15. The inrush current prevention circuit according to claim 7, comprising a delay circuit to delay the output signal of the second comparator and to apply the delayed output signal to the second switching element.

16. The inrush current prevention circuit according to claim 8, comprising a delay circuit to delay the output signal of the second comparator and to apply the delayed output signal to the second switching element.

17. The inrush current prevention circuit according to claim 10, comprising a delay circuit to delay the output signal of the second comparator and to apply the delayed output signal to the second switching element.

18. The inrush current prevention circuit according to claim 1, wherein n parallel circuits of the high-resistance element and bypass element are connected in series between the power supply input terminal and load, n being a plural number, the bypass threshold setting circuit sets voltages of n voltage dividing points in the voltage dividing circuit that divides the power supply voltage as n bypass thresholds, and for each of the n parallel circuits, the respective bypass element is caused to operate when the output voltage exceeds the respective bypass threshold, thereby bypassing the respective high-resistance element connected in parallel with the respective bypass element.

19. The inrush current prevention circuit according to claim 5, wherein n parallel circuits of the high-resistance element and bypass element are connected in series between the power supply input terminal and load, n being a plural number, the bypass threshold setting circuit sets voltages of n voltage dividing points in the voltage dividing circuit that divides the power supply voltage as n bypass thresholds, and for each of the n parallel circuits, the respective bypass element is caused to operate when the output voltage exceeds the respective bypass threshold, thereby bypassing the respective high-resistance element connected in parallel with the respective bypass element.

20. The inrush current prevention circuit according to claim 6, wherein n parallel circuits of the high-resistance element and bypass element are connected in series between the power supply input terminal and load, n being a plural number, the second comparator is disposed as n second comparators, the second switching element is disposed as n second switching elements, respectively configured to operate in accordance with output signals of the n second comparators, and respectively configured to operate the bypass elements of the n parallel circuits, the bypass threshold setting circuit applies voltages of n voltage dividing points in the voltage dividing circuit to the n second comparators respectively as n bypass thresholds, and for each of the n parallel circuits, the respective bypass element is turned on by the respective second switching element being turned on when the output voltage exceeds the respective bypass threshold, thereby bypassing the respective high-resistance element connected in parallel with the respective bypass element.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG. 1 is a circuit diagram showing a first embodiment of the disclosure.

[0039] FIG. 2 is a circuit diagram showing a second embodiment of the disclosure.

[0040] FIG. 3 is a circuit diagram showing a main portion of a third embodiment of the disclosure.

[0041] FIG. 4 is a circuit diagram showing existing technology described in JP '166.

[0042] FIG. 5 is a circuit diagram showing existing technology described in JP '448.

[0043] FIG. 6 is a circuit diagram showing existing technology described in JP '870.

DESCRIPTION OF EMBODIMENTS

[0044] Hereafter, based on the drawings, embodiments of the disclosure will be described.

[0045] FIG. 1 shows an inrush current prevention circuit according to a first embodiment of the disclosure. In FIG. 1, one end of each of capacitor 3 and load 4 is connected via a current limiting resistor 2 acting as a high-resistance element to a power supply input terminal 1, to which a direct current power supply (not shown) is connected.

[0046] The two ends of the current limiting resistor 2 are connected one each to a source S and drain D of a P-type MOSFET (hereafter referred to simply as an FET) 5 acting as a bypass element (a bypass switching element). Also, a pull-up resistor 6 and a second switching element 7 are connected in series between the power supply input terminal 1 and a ground point, and a connection point of the two is connected to a gate G of the FET 5.

[0047] The switching element 7 is a bipolar transistor, and an output signal of a second comparator 8 is applied to a base of the switching element 7. A voltage (output voltage) V.sub.c of one end of the capacitor 3 is applied to a positive input terminal of the comparator 8.

[0048] Meanwhile, resistors 9 and 10, which divide an input voltage (power supply voltage) V.sub.i, and a first switching element 11, which is a bipolar transistor, are connected in series between the power supply input terminal 1 and a ground point, and a connection point of the resistors 9 and 10, that is, a voltage dividing point, is connected to a negative input terminal of the comparator 8.

[0049] Also, resistors 12 and 13, which divide the output voltage V.sub.c, are connected in series between one end of the capacitor 3 and a ground point, and a voltage (a value corresponding to the output voltage) V.sub.cd of a voltage dividing point to which the resistors 12 and 13 are connected is applied to a positive input terminal of a first comparator 14. A reference voltage V.sub.ref of a reference power supply 15 is applied to a negative input terminal of the comparator 14, and an output signal of the comparator 14 is applied to a base of the switching element 11.

[0050] Herein, reference code 16 is a bypass threshold setting circuit and is also an example of a bypass threshold setting means. Bypass threshold setting circuit 16 is formed of the voltage dividing resistors 9, 10, 12, and 13, the switching element 11, the comparator 14, and the reference power supply 15, and a main portion thereof can be configured of, for example, a generic IC.

[0051] The bypass threshold setting circuit 16 operates so that the input voltage V.sub.i is divided in accordance with the magnitude of the output voltage V.sub.c by a voltage dividing circuit formed of the resistors 9 and 10, and a voltage V.sub.id of the voltage dividing point of the resistors 9 and 10 is set as a threshold (bypass threshold) of the second comparator 8.

[0052] The second comparator 8 outputs a high level or low level signal in accordance with a result of comparing the voltage V.sub.c of the capacitor 3 and a voltage set by the input voltage V.sub.i being divided by the resistors 9 and 10, that is, the bypass threshold V.sub.id, thereby controlling the second switching element 7 on and off. The voltage dividing ratio of the resistors 9 and 10 is arbitrary, but in terms of restricting an inrush current when the FET 5 carries out a bypass operation, it is sufficient, taking resistance values of the resistors 9 and 10 to be R.sub.9 and R.sub.10 respectively, to select resistance values so that R.sub.10/(R.sub.9+R.sub.10) is roughly in the region of 0.9 (90%).

[0053] The first comparator 14 outputs a high level or low level signal in accordance with a result of comparing the output voltage corresponding value V.sub.cd, which is the voltage V.sub.c of the capacitor 3 divided by the resistors 12 and 13, and the reference voltage V.sub.ref, thereby controlling the first switching element 11 on and off. Herein, the voltage dividing ratio of the resistors 12 and 13 is desirably such that the switching element 11 can be turned on when the generated voltage V.sub.cd corresponding to the voltage V.sub.c is lower than a minimum operating voltage of the load 4.

[0054] Next, an operation of the first embodiment will be described.

[0055] When the power supply to the circuit is turned on and the input voltage V.sub.i is applied, charging of the capacitor 3 is started by a current whose magnitude is limited by the current limiting resistor 2. A magnitude relationship between the divided voltage value V.sub.cd of the output voltage V.sub.c, which gradually rises in accompaniment to the charging, and the reference voltage V.sub.ref is such that the output signal of the comparator 14 is at a low level for a period for which V.sub.cd≦V.sub.ref, and the switching element 11 maintains an off-state.

[0056] Because of this, the voltage V.sub.id of the negative input terminal of the comparator 8 is pulled up to the power supply input terminal 1 by the resistor 9, and becomes equivalent to the input voltage V.sub.i.

[0057] At this time, it is clear that V.sub.i>V.sub.c, because of which V.sub.id>V.sub.c, the output signal of the comparator 8 is at a low level, and the switching element 7 is in an off-state. Because of this, the gate G of the FET 5 is pulled up to the input voltage V.sub.i by the resistor 6, because of which the gate G-to-source S voltage of the FET 5 becomes roughly 0V, and the FET 5 maintains an off-state.

[0058] Next, a description will be given of an operation when the charging of the capacitor 3 proceeds, and the voltage V.sub.c rises to an extent that V.sub.cd>V.sub.ref.

[0059] In this case, as V.sub.cd>V.sub.ref, the output signal of the comparator 14 is at a high level, and the switching element 11 is in an on-state. Herein, provisionally taking a collector-emitter voltage of the switching element 11 to be 0V in order to facilitate understanding, the voltage V.sub.id of the voltage dividing point of the resistors 9 and 10 is a value determined by the resistance values R.sub.9 and R.sub.10 of the resistors 9 and 10 respectively. For example, when taking the resistance value R.sub.9 to be 1 kΩ and the resistance value R.sub.10 to be 9 kΩ, voltage V.sub.id that is 90% of the input voltage V.sub.i is applied to the negative input terminal of the comparator 8 as the bypass threshold.

[0060] The voltage V.sub.c is input into the positive input terminal of the comparator 8, because of which, according to the heretofore described example of the resistance values R.sub.9 and R.sub.10, the output signal of the comparator 8 is at a low level, and the switching element 7 maintains an off-state, when V.sub.c is 90% or less of V.sub.i. When V.sub.c exceeds 90% of V.sub.i, the output signal of the comparator 8 inverts to a high level, and the switching element 7 switches to an on-state. When provisionally taking a collector-emitter voltage of the switching element 7 to be 0V in order to facilitate understanding, the gate G-to-source S voltage of the FET 5 is −V.sub.iV at this time, because of which the FET 5 is in an on-state, and the current limiting resistor 2 is bypassed.

[0061] For example, when the rated input voltage range is 5 to 15V and the ratio of the resistance values R.sub.9 and R.sub.10 is 1:9, the voltage V.sub.c when the input voltage V.sub.i is 5V is 90% (4.5V) or more of the input voltage V.sub.i. Because of this, a potential difference across the current limiting resistor 2 (a drain D-to-source S voltage of the FET 5) when the FET 5 switches from an off-state to an on-state is at most 0.5V. Also, the voltage V.sub.c when the input voltage V.sub.i is 15V is 90% (13.5V) or more of the input voltage V.sub.i, because of which, in the same way, the potential difference across the current limiting resistor 2 is at most 1.5V. Consequently, it does not happen that an excessive current flows into the capacitor 3 or load 4 when the FET 5 shifts to an on-state.

[0062] According to the first embodiment, as heretofore described, a bypass threshold that forms a condition triggering a bypass operation of the FET 5 can be set in accordance with a voltage division ratio of the input voltage V.sub.i, because of which an inrush current at a time of a bypass operation can be reliably restricted, even when the rated input voltage range is wide.

[0063] Next, based on FIG. 2, a description will be given of a second embodiment of the disclosure.

[0064] In FIG. 2, the same reference sign is allotted to a portion having the same function as in FIG. 1, and a description thereof omitted, and the description hereafter centers on a portion differing from FIG. 1.

[0065] In FIG. 2, a resistor 19 is connected between the drain D of the FET 5 and the positive input terminal of the comparator 8, and a resistor 20 is connected between the positive input terminal of the comparator 8 and an output terminal. The resistors 19 and 20 are for applying hysteresis characteristics to the comparator 8 in accordance with a ratio of resistance values of the resistors 19 and 20.

[0066] Also, a diode 21, capacitor 22, and resistors 23 and 24, which configure a delay circuit, are connected between the output terminal of the comparator 8 and the switching element 7.

[0067] Furthermore, a Zener diode 18 is connected with the polarity shown in the drawing between the source S and gate G of the FET 5, and a resistor 17 is connected between an anode of the Zener diode 18 and the collector of the switching element 7.

[0068] The Zener diode 18 has an application of protecting the FET 5 against an input overvoltage, while the resistor 17 has an application of protecting the Zener diode 18 when an input overvoltage is generated, and neither affects a main circuit operation of the disclosure.

[0069] In the first embodiment, a bypass threshold for the FET 5 to switch to an on-state is fixed only by a voltage division ratio based on the resistance values R.sub.9 and R.sub.10 of the resistors 9 and 10, but in the second embodiment, the resistors 19 and 20 are selected so that when resistance values of the resistors 19 and 20 are taken to be R.sub.19 and R.sub.20 respectively, {R.sub.10/(R.sub.9+R.sub.10)}×{(R.sub.19+R.sub.20)/R.sub.20} is roughly in the region of 0.9 (90%).

[0070] By hysteresis characteristics being applied to the comparator 8 by the resistors 19 and 20, concern that the FET 5 will repeat an on/off operation is reduced, even when, for example, the voltage V.sub.c repeatedly fluctuates so as to straddle the bypass threshold due to the effect of noise or the like.

[0071] Furthermore, by the delay circuit formed of the diode 21, capacitor 22, and resistors 23 and 24 being provided on the output side of the comparator 8, an on-state of the FET 5 can be maintained and power supplied for a period for which the load 4 continues operating when, for example, the voltage V.sub.c monotonically decreases to an extent that V.sub.cd<V.sub.ref.

[0072] Next, an operation of the second embodiment will be described.

[0073] Immediately after the power supply is turned on, an operation for a period for which the magnitude relationship between the divided voltage value V.sub.cd of the voltage V.sub.c and the reference voltage V.sub.ref is V.sub.cd<V.sub.ref is the same as in the first embodiment, the output signal of the comparator 14 is at a low level, and the switching element 11 is in an off-state. Also, the voltage V.sub.id of the negative input terminal of the comparator 8 is equivalent to the input voltage V.sub.i.

[0074] As V.sub.i>V.sub.c at this time, V.sub.id>V.sub.c, the output signal of the comparator 8 is at a low level, and the switching element 7 is in an off-state. Therefore, the gate G of the FET 5 is pulled up to the input voltage V.sub.i by the resistors 17 and 6, and the gate G-to-source S voltage of the FET 5 becomes roughly 0V, because of which the FET 5 maintains an off-state.

[0075] Next, a description will be given of an operation when the charging of the capacitor 3 proceeds, and the voltage V.sub.c rises to an extent that V.sub.cd>V.sub.ref.

[0076] When V.sub.cd>V.sub.ref, the output signal of the comparator 14 is at a high level, and the switching element 11 is in an on-state. Provisionally taking the collector-emitter voltage of the switching element 11 to be 0V, in the same way as in the first embodiment, the voltage V.sub.id of the voltage dividing point is a voltage division value of the resistors 9 and 10. For example, when taking the resistance value R.sub.9 of the resistor 9 to be 1 kΩ and the resistance value R.sub.10 of the resistor 10 to be 3 kΩ, a voltage that is 75% of the input voltage V.sub.i is applied to the negative input terminal of the comparator 8 as the bypass threshold. In the event that the output signal of the comparator 8 inverts from a low level to a high level at this time, it is sufficient to reselect the resistance values R.sub.9 and R.sub.10 together with the resistance values R.sub.19 and R.sub.20 of the hysteresis resistors 19 and 20.

[0077] When the voltage V.sub.c of the capacitor 3 rises further, and exceeds a voltage wherein the voltage that is 75% of the input voltage V.sub.i and the hysteresis voltage set by the resistors 19 and 20 are added together, the output signal of the comparator 8 inverts from a low level to a high level.

[0078] For example, when the resistance value R.sub.19 is taken to be 8 kΩ and the resistance value R.sub.20 is taken to be 4 kΩ, {R.sub.10/(R.sub.9+R.sub.10)}×{(R.sub.19+R.sub.20)/R.sub.20} is 0.9 (90%), because of which, when the voltage V.sub.c of the capacitor 3 rises to or above 90% of the input voltage V.sub.i, the output signal of the comparator 8 inverts from a low level to a high level, the capacitor 22 in the delay circuit is charged via the diode 21, and the switching element 7 switches to an on-state. No charging resistor of the capacitor 22 is shown in FIG. 2, but when wishing to further delay an operation of turning on the FET 5, it is sufficient to insert a charging resistor having a predetermined resistance value between a cathode of the diode 21 and one end of the capacitor 22.

[0079] When the output signal of the comparator 8 switches to a high level and the switching element 7 shifts to an on-state, the gate G-to-source S voltage of the FET 5 is −V.sub.iV when provisionally taking the collector-emitter voltage of the switching element 7 to be 0V, in the same way as previously described, because of which the FET 5 is in an on-state, and the current limiting resistor 2 is bypassed.

[0080] In the second embodiment too, as heretofore described, a bypass threshold that forms a condition triggering a bypass operation of the FET 5 can be set in accordance with a voltage division ratio of the input voltage V.sub.i, because of which an inrush current at a time of a bypass operation can be reliably restricted, even when the rated input voltage range is wide.

[0081] Next, a description will be given of an operation in the second embodiment when the input voltage V.sub.i decreases.

[0082] When the input voltage V.sub.i is within the rated input range, the FET 5 is in an on-state, because of which the magnitude relationship between V.sub.i and V.sub.c, although strictly speaking V.sub.i>V.sub.c, is such that V.sub.i and V.sub.c are roughly equal values. As the switching element 11 is also in an on-state at this time, the dividing point voltage V.sub.id is always lower than the voltage V.sub.c of the capacitor 3 within the rated input range.

[0083] Consequently, even when the input voltage V.sub.i decreases within the rated input range, the output signal of the comparator 8 does not invert from a high level to a low level, because of which the FET 5 maintains an on-state.

[0084] Herein, a minimum operating voltage is generally specified for a part corresponding to the load 4 in FIG. 2, but in actuality, the load 4 can operate even when a voltage slightly lower than the minimum operating voltage is applied. Because of this, when the voltage V.sub.c decreases to an extent such as to fall under the rated input range of the load 4, it is necessary to avoid a situation wherein the FET 5 switches to an off-state despite the load 4 operating, and the delay circuit in FIG. 2 is provided in consideration of the above-mentioned point.

[0085] That is, when the voltage V.sub.c decreases to an extent that, for example, V.sub.cd<V.sub.ref, the output signal of the comparator 14 inverts from a high level to a low level. By the switching element 11 switching to an off-state at this time, the input voltage V.sub.i is applied via the resistor 9 to the negative input terminal of the comparator 8.

[0086] As V.sub.i>V.sub.c, as previously described, the output signal of the comparator 8 inverts from a high level to a low level, but by appropriately setting the values of the capacitor 22 and resistors 23 and 24 in the delay circuit, an on-state of the FET 5 can be held for a desired delay time, and a drive state of the load 4 can be maintained.

[0087] Next, FIG. 3 is a circuit diagram showing a main portion of a third embodiment of the disclosure.

[0088] The third embodiment envisages a case wherein the rated input voltage range is extremely wide, multiple stages of the second comparator 8, second switching element 7, current limiting resistor 2, and FET 5 of the first and second embodiments are provided, and an inrush current at a time of a bypass operation is restricted by the FETs 5 being sequentially turned on in accordance with the magnitude of the voltage V.sub.c of the capacitor 3.

[0089] In FIG. 3, n (n is a multiple) current limiting resistors 2.sub.1 to 2.sub.n are connected in series between the power supply input terminal 1 and one end of the capacitor 3, and FETs 5.sub.1 to 5.sub.n are connected in parallel to the resistors 2.sub.1 to 2.sub.n respectively.

[0090] The drain D of the FET 5.sub.1 on the capacitor 3 side is connected to each positive input terminal of n second comparators 8.sub.1 to 8.sub.n provided corresponding to the current limiting resistors 2.sub.1 to 2.sub.n, and each negative input terminal of the comparators 8.sub.1 to 8.sub.n is connected to a voltage dividing point between resistors in a series circuit of voltage dividing resistors 9.sub.1 to 9.sub.n and a resistor 10 connected between the power supply input terminal 1 and a ground point.

[0091] Also, output terminals of the second comparators 8.sub.1 to 8.sub.n are connected to bases of n second switching elements 7.sub.1 to 7.sub.n respectively, and collectors of the switching elements 7.sub.1 to 7.sub.n are connected via resistors 6.sub.1 to 6.sub.n to the source S of the FET 5.sub.n. Also, emitters of the switching elements 7.sub.1 to 7.sub.n are all grounded.

[0092] Also, as a configuration of bypass threshold setting circuit 16A is the same as in the first and second embodiments except for the series circuit of voltage dividing resistors 9.sub.1 to 9.sub.n, a description thereof will be omitted here.

[0093] In the third embodiment, the FETs 5.sub.1 to 5.sub.n switch to an on-state in an order of 5.sub.n to 5.sub.n-1 and so on until 5.sub.2 to 5.sub.1 while the voltage V.sub.c of the capacitor 3 gradually rises (while a gap between the input voltage V.sub.i and the voltage V.sub.c decreases) after the power supply is turned on.

[0094] For example, when a ratio of a combined resistance value of the series circuit of resistors 9.sub.1 to 9.sub.n and a resistance value of the resistor 10 is 9:1, a voltage V.sub.idn of a connection point of the resistors 9.sub.n and 10 is 0.5V when the input voltage V.sub.i is 5V, and the voltage V.sub.idn is applied to the negative input terminal of the comparator 8.sub.n as the bypass threshold. Because of this, the output signal of the comparator 8.sub.n switches to a high level at a point at which the voltage V.sub.c of the capacitor 3 exceeds 0.5V, the switching element 7.sub.n switches to an on-state, and the FET 5.sub.n also switches to an on-state. At this point, the source S-to-drain D voltage of the FET 5.sub.n is of an insignificant value.

[0095] Also, as voltages of voltage dividing points of the resistors 9.sub.1 to 9.sub.n and 10 increase in an order of V.sub.idn to V.sub.idn-1 and so on until V.sub.id2 to V.sub.id1, the comparator output signals switch to a high level in an order of 8.sub.n to 8.sub.n-1 and so on until 8.sub.2 to 8.sub.1 while the voltage V.sub.c of the capacitor 3 rises, and the FETs also switch to an on-state in an order of 5.sub.n to 5.sub.n-1 and so on until 5.sub.2 to 5.sub.1.

[0096] That is, the current limiting resistors are bypassed in an order of 2.sub.n to 2.sub.n-1 and so on until 2.sub.2 to 2.sub.1 together with the rise of the voltage V.sub.c of the capacitor 3, and all of the current limiting resistors 2.sub.1 to 2.sub.n are bypassed at a point at which the voltage V.sub.c exceeds the voltage V.sub.id1 of the voltage dividing point of the resistors 9.sub.1 and 9.sub.2.

[0097] Consequently, by appropriately selecting the values of the voltage dividing resistors 9.sub.1 to 9.sub.n and 10, a potential difference across the series circuit of current limiting resistors 2.sub.1 to 2.sub.n when all of the current limiting resistors are bypassed can be reduced, and no excessive inrush current flows into the capacitor 3 or load 4.

[0098] When the input voltage V.sub.i is extremely large, each of the voltage dividing point voltages V.sub.id1 to V.sub.idn also increases in accordance with the magnitude of the input voltage V.sub.i, but as the potential difference across the series circuit of current limiting resistors 2.sub.1 to 2.sub.n becomes a small value owing to the same kind of operation as when the input voltage V.sub.i is small, current flowing via the FETs 5.sub.1 to 5.sub.n is reduced by a bypass operation, and generation of an inrush current can be prevented.

[0099] In the third embodiment too, in the same way as in the second embodiment, the second comparators 8.sub.1 to 8.sub.n may be provided with hysteresis characteristics, and a delay circuit may be inserted between the second comparators 8.sub.1 to 8.sub.n and switching elements 7.sub.1 to 7.sub.n.

[0100] Embodiments of the disclosure can be utilized as various kinds of direct current power supply device wherein a range of rated input voltage from a power supply is wide, and which have an application of supplying direct current voltage of a predetermined magnitude to a load.

[0101] Inclusion in this disclosure of any characterization of any product or method of the related art does not imply or admit that such characterization was known in the prior art or that such characterization would have been appreciated by one of ordinary skill in the art at the time a claimed invention was made, even if the product or method itself was known in the prior art at the time of invention of the present disclosure. For example, if a related art document discussed in the foregoing sections of this disclosure constitutes prior art, the inclusion of any characterization of the related art document does not imply or admit that such characterization of the related art document was known in the prior art or would have been appreciated by one of ordinary skill in the art at the time a claimed invention was made, especially if the characterization is not disclosed in the related art document itself.

[0102] Although a few embodiments have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.

[0103] Reference signs and numerals are as follows: [0104] 1: Power supply input terminal [0105] 2, 2.sub.1 to 2.sub.n: Current limiting resistor [0106] 3: Capacitor [0107] 4: Load [0108] 5, 5.sub.1 to 5.sub.n: FET [0109] 7, 7.sub.1 to 7.sub.n, 11: Switching element [0110] 6, 6.sub.1 to 6.sub.n, 9, 9.sub.1 to 9.sub.n, 10, 12, 13, 17, 19, 20, 23, 24: Resistor [0111] 8, 8.sub.1 to 8.sub.n, 14: Comparator [0112] 15: Reference power supply [0113] 16, 16A: Bypass threshold setting circuit [0114] 18: Zener diode [0115] 21: Diode [0116] 22: Capacitor [0117] G: Gate [0118] S: Source [0119] D: Drain