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Charge Injection for Ultra-Fast Voltage Control in Voltage Regulators

20170269619 · 2017-09-21

    Inventors

    Cpc classification

    International classification

    Abstract

    This application relates to a circuit for generating an output voltage and regulating the output voltage to a target voltage. The circuit includes a switchable voltage divider circuit configured to generate a feedback voltage that is a variable fraction of the output voltage, an error amplifier stage configured to generate a control voltage on the basis of a reference voltage and the variable fraction of the output voltage, a buffer stage configured to generate the output voltage on the basis of the control voltage, and a charge injection circuit configured to inject charge at an intermediate node between the error amplifier stage and the buffer stage to thereby modify the control voltage generated by the error amplifier stage. The application further relates to a method of operating such circuit.

    Claims

    1. A circuit for generating an output voltage and regulating the output voltage to a target voltage, the circuit comprising: a switchable voltage divider circuit configured to generate a voltage that is a variable fraction of the output voltage; an error amplifier stage configured to generate a control voltage on the basis of a reference voltage and the variable fraction of the output voltage; a buffer stage configured to generate the output voltage on the basis of the control voltage; and a charge injection circuit configured to inject charge at an intermediate node between the error amplifier stage and the buffer stage to thereby modify the control voltage generated by the error amplifier stage.

    2. The circuit according to claim 1, wherein the charge injection circuit is configured to inject charge at the intermediate node in such a manner that the control voltage is lowered if the variable fraction of the output voltage is larger than the reference voltage and raised if the variable fraction of the output voltage is smaller than the reference voltage.

    3. The circuit according to claim 1, wherein the charge injection circuit comprises: a capacitive element; and a switching circuit configured to be switchable to a first configuration in which the capacitive element is disconnected from the intermediate node and coupled between the output voltage and a first voltage level below the output voltage, and a second configuration in which the capacitive element is coupled between the intermediate node and a second voltage level above the first voltage level.

    4. The circuit according to claim 3, further comprising a control logic for periodically switching the switching circuit between the first configuration and the second configuration while the fraction of the output voltage is below the reference voltage.

    5. The circuit according to claim 4, wherein the switching circuit is further configured to be switchable to a third configuration in which the capacitive element is disconnected from the intermediate node and coupled between the output voltage and the second voltage level, and a fourth configuration in which the capacitive element is coupled between the intermediate node and the first voltage level.

    6. The circuit according to claim 5, wherein the control logic is further configured to periodically switch the switching circuit between the third configuration and the fourth configuration while the fraction of the output voltage is above the reference voltage.

    7. The circuit according to claim 3, wherein the switching circuit comprises: a first switching element for switchably coupling a first terminal of the capacitive element to the first voltage level; a second switching element for switchably coupling the first terminal of the capacitive element to the second voltage level; a third switching element for switchably coupling a second terminal of the capacitive element to the output voltage; and a fourth switching element for switchably coupling the second terminal of the capacitive element to the intermediate node.

    8. The circuit according to claim 1, further comprising a second capacitive element coupled between the intermediate node and a predetermined voltage level.

    9. The circuit according to claim 8, wherein a capacity of the second capacitive element is larger than a capacity of the first capacitive element by a factor of ten or more.

    10. The circuit according to claim 1, wherein the charge injection circuit comprises a controllable current source.

    11. A method of generating an output voltage and regulating the output voltage to a target voltage, the method comprising: generating a voltage that is a variable fraction of the output voltage in accordance with a control signal depending on a desired target voltage; generating a control voltage on the basis of a reference voltage and the variable fraction of the output voltage; buffering the control voltage to generate the output voltage; and modifying the generated control voltage by means of charge injection.

    12. The method according to claim 11, wherein modifying the control voltage involves lowering the control voltage if the variable fraction of the output voltage is larger than the reference voltage and raising the control voltage if the variable fraction of the output voltage is smaller than the reference voltage.

    13. The method according to claim 11, wherein charge injection is performed using a capacitive element and the method further comprises the steps of: comparing the variable fraction of the output voltage to the reference voltage; and if the fraction of the output voltage is below the reference voltage, periodically switching between a first configuration in which the capacitive element is disconnected from a voltage level of the control voltage and coupled between the output voltage and a first voltage level below the output voltage, and a second configuration in which the capacitive element is coupled between the voltage level of the control voltage and a second voltage level above the first voltage level.

    14. The method according to claim 13, further comprising the steps of: if the fraction of the output voltage is above the reference voltage, periodically switching between a third configuration in which the capacitive element is disconnected from the voltage level of the control voltage and coupled between the output voltage and the second voltage level, and a fourth configuration in which the capacitive element is coupled between the voltage level of the control voltage and the first voltage level.

    15. The method according to claim 13, further comprising the steps of: switching a first switching element that switchably couples a first terminal of the capacitive element to the first voltage level; switching a second switching element that switchably couples the first terminal of the capacitive element to the second voltage level; switching a third switching element that switchably couples a second terminal of the capacitive element to the output voltage; and switching a fourth switching element that switchably couples the second terminal of the capacitive element to the voltage level of the control voltage.

    16. The method according to claim 11, wherein charge injection is performed by means of a controllable current source.

    17. The method according to claim 11, wherein the charge injection circuit comprises: a capacitive element; and a switching circuit which is switchable to a first configuration in which the capacitive element is disconnected from the intermediate node and coupled between the output voltage and a first voltage level below the output voltage, and a second configuration in which the capacitive element is coupled between the intermediate node and a second voltage level above the first voltage level.

    18. The method according to claim 17, wherein the switching circuit is switchable to a third configuration in which the capacitive element is disconnected from the intermediate node and coupled between the output voltage and the second voltage level, and a fourth configuration in which the capacitive element is coupled between the intermediate node and the first voltage level.

    19. The method according to claim 11, further comprising a second capacitive element coupled between the intermediate node and a predetermined voltage level.

    20. The method according to claim 19, wherein a capacity of the second capacitive element is larger than a capacity of the first capacitive element by a factor of ten or more.

    Description

    BRIEF DESCRIPTION OF THE DRAWINGS

    [0027] Embodiments of the disclosure are explained below in an exemplary manner with reference to the accompanying drawings, wherein

    [0028] FIG. 1 schematically illustrates an example of a circuit for generating an output voltage and regulating the output voltage to a target voltage to which embodiments of the disclosure may be applied,

    [0029] FIG. 2 schematically illustrates another example of a circuit for generating an output voltage and regulating the output voltage to a target voltage to which embodiments of the disclosure may be applied,

    [0030] FIG. 3 schematically illustrates an example of a circuit for generating an output voltage and is regulating the output voltage to a target voltage according to embodiments of the disclosure,

    [0031] FIG. 4 schematically illustrates another example of a circuit for generating an output voltage and regulating the output voltage to a target voltage according to embodiments of the disclosure,

    [0032] FIG. 5A and FIG. 5B schematically illustrate an example of operation of the circuit of FIG. 4 for a desired target voltage above the current output voltage,

    [0033] FIG. 6A and FIG. 6B schematically illustrate an example of operation of the circuit of FIG. 4 for a desired target voltage below the current output voltage,

    [0034] FIG. 7A and FIG. 7B are time charts schematically illustrating voltage levels and control signal levels in the circuit of FIG. 4, and

    [0035] FIG. 8 schematically illustrates yet another example of a circuit for generating an output voltage and regulating the output voltage to a target voltage according to embodiments of the disclosure.

    DESCRIPTION

    [0036] An example of a voltage regulator 100 to which embodiments of the disclosure may be applied is schematically illustrated in FIG. 1. The voltage regulator 100 may be said to correspond to a circuit for generating an output voltage and regulating the output voltage to a target voltage. For example, the voltage regulator 100 may be a LDO. The voltage regulator 100 may comprise an error amplifier stage and a buffer stage 30 coupled (e.g., connected) in series with each other. The error amplifier stage may comprise an error amplifier 20. The error amplifier 20 may comprise, or be, an OTA. The voltage regulator 100 may further comprise a switchable voltage divider circuit 10 for generating a voltage V.sub.Rtap (feedback voltage) that is a fraction of the output voltage of the voltage regulator 100. The fraction may be a variable fraction that is adjustable by switching operation of the switchable voltage divider circuit 10, for example under control of a digital control signal. The feedback voltage V.sub.Rtap may be supplied to an input port (e.g., negative, or inverting input) of the error amplifier stage (e.g., of the error amplifier 20). A reference voltage V.sub.REF (e.g., fixed reference voltage) may be supplied to the other input port (e.g., positive, or non-inverting input) of the error amplifier stage (e.g., of the error amplifier 20).

    [0037] The error amplifier stage may convert a differential input voltage (e.g., a difference between the reference voltage V.sub.REF and the feedback voltage V.sub.Rtap) to a single-ended output. The error amplifier stage may generate, as the single-ended output, a control voltage V.sub.control that may be supplied to the buffer stage 30. Thus, the error amplifier stage may be said to generate the control voltage V.sub.control on the basis of the reference voltage V.sub.REF and the feedback voltage V.sub.Rtap. The voltage regulator 100 may further comprise a capacitive element (compensation capacitive element) 40 connected between a predetermined voltage level (e.g., ground) and an intermediate node 25 between an output terminal of the error amplifier 20 and the buffer stage 30. The capacitive element 40 may have compensation capacitance C.sub.c. The error amplifier stage may be said to include the capacitive element 40.

    [0038] The buffer stage 30 may include a buffer amplifier, such as, for example, a level shifter (with or without offset). The buffer stage 30 may further include a pass device (pass transistor) of the voltage regulator 100 for passing an output current of the voltage regulator 100. The buffer stage 30 may output (e.g., generate), as the output voltage V.sub.out, a voltage that depends on the control voltage V.sub.control. Thus, the buffer stage 30 may be said to buffer the control voltage V.sub.control to generate the output voltage V.sub.out. The buffer stage 30 may be further said to operate under control of the error amplifier stage (e.g., error amplifier 20). The output voltage V.sub.out output by the buffer stage 30 may correspond to the control voltage V.sub.control (e.g., may be equal to said voltage), or may be offset from the control voltage V.sub.control by a voltage offset (e.g., constant offset, such as an offset resulting from a threshold voltage of a transistor comprised by the buffer stage 30). The output voltage V.sub.out may be output at an output node 35 of the voltage regulator 100.

    [0039] The buffer stage 30 may have high bandwidth and low output impedance in order to be able to drive an electrical load 60 that has (high) load capacitance (CO 50. The buffer stage 30 regulates V.sub.out based on the control voltage V.sub.control. By contrast, the error amplifier stage (e.g., the error amplifier 20) may be designed for low bandwidth so as to provide for a dominant pole in the system connected to the compensation capacitance element 40. Thus, the main loop of the voltage regulator 100, which includes the error amplifier stage, may have much lower bandwidth than the buffer loop which includes the buffer stage 30.

    [0040] In the voltage regulator 100, the output voltage V.sub.out may be controlled by controlling the variable fraction of the output voltage V.sub.out that is output by the switchable voltage divider circuit 10 as the feedback voltage V.sub.Rtap. In other words, the output voltage V.sub.out may be controlled by changing the divider ratio of the switchable voltage divider circuit 10. As indicated above, the value of the variable fraction may be controlled by switching operation of the switchable voltage divider circuit 10. Said switching operation may be performed in accordance with (e.g., under control of) a digital control signal for setting the desired target voltage of the voltage regulator 100. Thus, the switchable voltage divider circuit 10 may be said to generate the feedback voltage in accordance with a (digital) control signal that depends (or is indicative of) the desired target voltage.

    [0041] If the value of said variable fraction is increased, the error amplifier stage will regulate the control voltage V.sub.control (and thus, the output voltage V.sub.out), such that the increased feedback voltage V.sub.Rtap given by the increased fraction of the output voltage V.sub.out and the reference voltage V.sub.REF agree with each other. That is, the control voltage V.sub.control output by the error amplifier stage will be reduced, and thus the output voltage V.sub.out will be reduced. On the other hand, if the value of said variable fraction is decreased, the error amplifier stage will regulate the control voltage V.sub.control (and thus, the output voltage V.sub.out), such that the decreased feedback voltage V.sub.Rtap given by the decreased fraction of the output voltage V.sub.out and the reference voltage V.sub.REF agree with each other. That is, the control voltage V.sub.control output by the error amplifier stage will be increased, and thus the output voltage V.sub.out will be increased. As a result, the output voltage V.sub.out may be controlled to agree with the desired target voltage that may depend on (e.g., may be substantially given by) the reference voltage V.sub.REF divided by the present value of the variable fraction.

    [0042] As the buffer stage 30 may have very high bandwidth, the output voltage V.sub.out will follow the control voltage V.sub.control almost immediately. Therefore, the speed of the output voltage change (change rate) is determined essentially by the bandwidth of the error amplifier stage (e.g., error amplifier 20), which is given by the bias current of the error amplifier 20 and the compensation capacitance C.sub.c.

    [0043] Another example of a voltage regulator 200 to which embodiments of the disclosure may be applied is schematically illustrated in FIG. 2. The voltage regulator 200 of FIG. 2 may be seen as an exemplary, specific implementation of the voltage regulator 100 of FIG. 1. Single or plural details of implementation of the below description may be employed in the context of the voltage regulator 100 of FIG. 1, without the necessity to employ each and every detail of implementation. Some of these details of implementation relate to the switchable voltage divider circuit 10 and to the buffer stage 30. Moreover, unless indicated otherwise, like-numbered elements in FIG. 1 and FIG. 2 are identical and repeated description thereof is omitted for reasons of conciseness.

    [0044] The switchable voltage divider circuit 10 in the voltage regulator 200 of FIG. 2 may comprise a plurality of resistance elements (e.g., resistors) 11-1, 11-2, 12-1, 12-2 that are coupled (e.g., connected) in series between a voltage level of the output voltage V.sub.out and ground. Alternatively, the switchable voltage divider circuit 10 may comprise a plurality of capacitive elements instead of resistive elements. The feedback voltage V.sub.Rtap may be output from (e.g., tapped at) an intermediate node 13 of the switchable voltage divider circuit 10. The plurality of resistance elements 11-1, 11-2 coupled (e.g., connected) between the intermediate node 13 and the voltage level of the output voltage V.sub.out may be switchable, so that a total resistance value of a circuit path between the intermediate node 13 and the voltage level of the output voltage V.sub.out may be controlled by switching of these resistance elements 11-1, 11-2. Switching of these resistance elements 11-1, 11-2 may involve selectively bypassing respective resistance elements.

    [0045] The buffer stage 30 in the voltage regulator 200 of FIG. 2 may comprise a feedback loop. In other words, the buffer stage 30 may receive the generated output voltage V.sub.out and the control voltage V.sub.control as inputs. For example, the buffer stage 30 may comprise a buffer amplifier, and the output voltage V.sub.out output by the buffer amplifier may be fed back to an input port (e.g., the negative, or inverting input) of the buffer amplifier. The control voltage V.sub.control may be supplied to the other input port (e.g., the positive, or non-inverting input) of the buffer amplifier.

    [0046] Next, embodiments of the disclosure will be described with reference to FIG. 3 to FIG. 8. Notably, embodiments of the disclosure may be applied to either voltage regulator described above.

    [0047] Broadly speaking, the concept of the present disclosure relates to charge injection to the output of the error amplifier stage (e.g., error amplifier 20) by a charge injection circuit 70 to thereby simultaneously increase the change rate of the control voltage V.sub.control and of the output voltage V.sub.out.

    [0048] FIG. 3 schematically illustrates an example of a voltage regulator 300 according to embodiments of the disclosure. The voltage regulator 300 may be said to correspond to a circuit for generating an output voltage and regulating the output voltage to a target voltage.

    [0049] The voltage regulator 300 differs from the voltage regulator 100 in FIG. 1 by comprising a charge injection circuit 70 for injecting (positive or negative) charge (i.e., electric charge) at the intermediate node 25. The charge injection circuit 70 may be coupled (e.g., connected) between the intermediate node 25 and a first voltage level (e.g., ground). Charge injection at the intermediate node 25 may serve to modify (adjust) the control voltage V.sub.control that is output by the error amplifier stage (e.g., error amplifier 20). The buffer stage 30 may operate under control of the modified control voltage.

    [0050] The charge injection circuit 70 may be configured to inject electric charge at the intermediate node 25. In particular, the charge injection circuit 70 may be configured to inject electric charge in such a manner that the modified control voltage is lower than the control voltage generated by the error amplifier stage, i.e. such that the control voltage is lowered, if the feedback voltage V.sub.Rtap is larger than the reference voltage V.sub.REF. The charge injection circuit 70 may be also configured to inject charge at the intermediate node 25 in such a manner that the modified control voltage is higher than the control voltage generated by the error amplifier stage, i.e. such that the control voltage is raised, if the feedback voltage V.sub.Rtap is smaller than the reference voltage V.sub.REF.

    [0051] FIG. 4 schematically illustrates another example of a voltage regulator 400 according to embodiments of the disclosure. The voltage regulator 400 of FIG. 4 may be seen as an exemplary, specific implementation of the voltage regulator 300 of FIG. 3. Single or plural details of implementation of the below description may be employed in the context of the voltage regulator 300 of FIG. 3, without the necessity to employ each and every detail of implementation. Some of these details of implementation relate to the charge injection circuit 70. Moreover, unless indicated otherwise, like-numbered elements in FIG. 3 and FIG. 4 are identical and repeated description thereof is omitted for reasons of conciseness.

    [0052] The voltage regulator 400 differs from the voltage regulator 200 in FIG. 2 by comprising the charge injection circuit 70 for injecting or taking out charge (i.e., electric charge) at the intermediate node 25. In general, the charge injection circuit 70 may be said to inject charge. In particular, the charge injection circuit may be said to inject negative charge or (virtually) inject positive charge, the latter corresponding to taking out negative charge. The arrangement (e.g., coupling) and operation of the charge injection circuit 70 may be identical to the arrangement (e.g., coupling) and operation of the charge injection circuit 70 in FIG. 3. It is to be understood that FIG. 4 shows a specific exemplary implementation of the charge injection circuit 70.

    [0053] Accordingly, the charge injection circuit 70 may include a (first) capacitive element 80 (C.sub.F). The first capacitive element 80 may include, or be, a capacitor. The charge injection circuit 70 may further include a switching circuit (e.g., an assembly of switching elements). The switching circuit may be switchable to a first configuration and a second configuration. In the first configuration of the switching circuit, the first capacitive element 80 may be disconnected from the intermediate node 25 and coupled (e.g., connected) between the voltage level of the output voltage V.sub.out and the first voltage level. The first voltage level may be below the voltage level of the output voltage V.sub.out. The first voltage level may be ground, for example. In the second configuration of the switching circuit, the first capacitive element 80 may be coupled (e.g., connected) between the intermediate node 25 and a second voltage level. The second voltage level may be above the first voltage level. Further, the second voltage level may be below the voltage level of the output voltage V.sub.out. The second voltage level may be a voltage level of a voltage V.sub.refdvc output by the switchable voltage divider circuit 10. Alternatively, the second voltage level may be a predetermined voltage level of a voltage output by a reference voltage supply, for example.

    [0054] The switching circuit may be further switchable to a third configuration and a fourth configuration. In the third configuration of the switching circuit, the first capacitive element 80 may be disconnected from the intermediate node 25 and coupled (e.g., connected) between the voltage level of the output voltage V.sub.out and the second voltage level. In the fourth configuration of the switching circuit, the first capacitive element may be coupled (e.g., connected) between the intermediate node 25 and the first voltage level.

    [0055] In embodiments, the switching circuit may include first to fourth switching elements 91, 92, 93, 94, such as switches, for example, (e.g., controllable switches). The first to fourth switching elements 91, 92, 93, 94 may include, or be, transistors, for example. The first switching element 91 may be configured (e.g., arranged) for switchably coupling (e.g., connecting) a first terminal of the first capacitive element 80 to the first voltage level. The second switching element 92 may be configured (e.g., arranged) for switchably coupling (e.g., connecting) the first terminal of the first capacitive element 80 to the second voltage level. For example, the second switching element 92 may be coupled (e.g., connected) between the first terminal of the first capacitive element 80 and an additional tap (second intermediate node) 14 of the switchable voltage divider circuit 10. The third switching element 93 may be configured (e.g., arranged) for switchably coupling (e.g., connecting) a second terminal of the first capacitive element 80 to the voltage level of the output voltage V.sub.out. The fourth switching element 94 may be configured (e.g., arranged) for switchably coupling (e.g., connecting) the second terminal of the first capacitive element 80 to the intermediate node 25.

    [0056] For the first configuration of the switching circuit, the first and third switching elements 91, 93 may be closed (i.e., may allow a current to pass), and the second and fourth switching elements 92, 94 may be open (i.e., may substantially block currents). In the second configuration, the first and third switching elements 91, 93 may be open and the second and fourth switching elements 92, 94 may be closed. In the third configuration, the second and third switching elements 92, 93 may be closed and the first and fourth switching elements 91, 94 may be open. Lastly, in the fourth configuration, the second and third switching elements 92, 93 may be open and the first and fourth switching elements 91, 94 may be closed. Here, the closed state of a switching element is understood to refer to a conducting state, and the open state of a switching element is understood to refer to a substantially non-conducting state. The first to fourth switching elements may be implemented by transistors, for example, as indicated above.

    [0057] The voltage regulator 400 may further include a second capacitive element 40 connected between the intermediate node 25 and a predetermined voltage level. The second capacitive element may be the compensation capacitive element 40 described above in the context of FIG. 1. The predetermined voltage level may be the first voltage level (e.g., ground). The first capacitive element 80 may have a smaller capacitance than the second capacitive element 40. For example, the capacitance (capacitance value) C.sub.C of the second capacitive element 40 may be larger than the capacitance (capacitance value) C.sub.F of the first capacitive element 80 by a factor of 10 or more. In embodiments, for example, the capacitance C.sub.C of the second capacitive element 40 may be larger than the capacitance C.sub.F of the first capacitive element 80 by a factor of between 25 and 45. As will be described below, the relative sizes of capacitances of the first and second capacitive elements 80, 40 may set the size of the increase or decrease ΔV.sub.control of the control voltage V.sub.control resulting from charge injection.

    [0058] The voltage regulator 400 may further include a control logic (not shown in FIG. 4) for controlling the switching circuit. The control logic may periodically switch the switching circuit between the first configuration and the second configuration while the feedback voltage V.sub.Rtap is below the reference voltage V.sub.REF (i.e., while the output voltage V.sub.out is desired to be raised). Also, the control logic may periodically switch the switching circuit between the third configuration and the fourth configuration while the feedback voltage V.sub.Rtap is above the reference voltage V.sub.REF (i.e., while the output voltage V.sub.out is desired to be lowered). The control logic may be implemented by a digital control block of a PMIC comprising the voltage regulator 400.

    [0059] Operation (such as DVC operation, for example) for increasing or decreasing the output voltage V.sub.out may consist of two phases each. The respective two phases may be alternatingly repeated until the desired target voltage has been reached. Repetition may be performed in a periodic manner, such as on the basis of a clock signal, for example. Moreover, repetition may be performed under control of the control logic. FIG. 5A and FIG. 5B schematically illustrate an example of the respective two phases of operation of the voltage regulator 400 of FIG. 4 for a desired target voltage above the current output voltage (voltage up operation, e.g., DVC up operation). FIG. 6A and FIG. 6B schematically illustrate an example of the respective two phases of operation of the voltage regulator 400 for a desired target voltage below the current output voltage (voltage down operation, e.g., DVC down operation).

    [0060] FIG. 5A schematically illustrates the switch configuration and corresponding voltages for the first phase (phase 1) of raising the output voltage V.sub.out (voltage up operation, e.g., DVC up operation). During this phase, which may be referred to as charging phase, the switching circuit may be in the first configuration. Accordingly, the first and third switching elements 91, 93 may be closed and the second and fourth switching elements 92, 94 may be open. Thus, the first capacitive element 80 may be coupled (e.g., connected) between ground (as an example of the first voltage level) and the voltage level of the output voltage V.sub.out, and may be charged up to the output voltage V.sub.out. Thus, the voltage V.sub.CF across the first capacitive element 80 will rise. The current flow during this phase is indicated by the bent arrow in FIG. 5A (notably, electrons will flow in the opposite direction). On the other hand, the control voltage V.sub.control and the output voltage V.sub.out may remain unchanged during this phase.

    [0061] FIG. 5B schematically illustrates the switch configuration and corresponding voltages for the second phase (phase 2) of raising the output voltage V.sub.out (voltage up operation, e.g., DVC up operation). During this phase, which may be referred to as discharging phase, the switching circuit may be in the second configuration. Accordingly, the first and third switching elements 91, 93 may be open and the second and fourth switching elements 92, 94 may be closed. Thus, the first capacitive element 80 may be coupled (e.g., connected) between the intermediate node 25 and the second voltage level V.sub.refdvc. Since the second voltage level V.sub.refdvc is above ground (as an example of the first voltage level), the voltage V.sub.CF on the first capacitive element 80 is boosted by up by the second voltage V.sub.refdvc (in general, by the difference between the second voltage and the first voltage if the first voltage level is different from the ground voltage level). Therefore, the first capacitive element 80 may be discharged over the fourth switching element 94 to the second capacitive element 40. The current flow during this phase is indicated by the bent arrow in FIG. 5B (notably, electrons will flow in the opposite direction). At the same time, the control voltage V.sub.control increases due to the electric charge shared between the first and second capacitive elements 80, 40. In particular, a voltage change of the control voltage V.sub.control (resulting voltage change at the end of the second phase) may be given by


    ΔV.sub.control=ΔV.sub.out=C.sub.F/(C.sub.C+C.sub.F).Math.V.sub.refdvc.

    [0062] For the first voltage level different from ground, V.sub.refdvc in the above equation would need to be replaced by the difference between the second voltage level and the first voltage level.

    [0063] As can be seen from the above equation, the step size by which the control voltage V.sub.control is changed (i.e., increased in the present case) is set by the second voltage (in general, by the difference between the second voltage and the first voltage if the first voltage level is different from the ground voltage level) and the ratio between the capacitance C.sub.F of the first capacitive element 80 and the sum of the capacitances C.sub.F and C.sub.C of the first and second capacitive elements 80, 40.

    [0064] The buffer stage 30 will drive the load capacitance (i.e., the output voltage V.sub.out) to follow the control voltage V.sub.control.

    [0065] As indicated above, the first and second phases of operation (voltage up operation, e.g., DVC up operation) may be alternatingly repeated until the output voltage V.sub.out is increased up to the desired target voltage.

    [0066] FIG. 6A schematically illustrates the switch configuration and corresponding voltages for the first phase (phase 1) of lowering the output voltage V.sub.out (voltage down operation, e.g., DVC down operation). During this phase, which may be referred to as charging phase, the switching circuit may be in the third configuration. Accordingly, the second and third switching elements 92, 93 may be closed and the first and fourth switching elements 91, 94 may be open. Thus, the first capacitive element 80 may be coupled (e.g., connected) between the second voltage level V.sub.refdvc and the voltage level of the output voltage V.sub.out and may be charged up to the output voltage V.sub.out. Thus, the voltage V.sub.CF across the first capacitive element 80 will rise. The current flow during this phase is indicated by the bent arrow in FIG. 6A. On the other hand, the control voltage V.sub.control and the output voltage V.sub.out may remain unchanged during this phase.

    [0067] FIG. 6B schematically illustrates the switch configuration and corresponding voltages for the second phase (phase 2) of lowering the output voltage V.sub.out (voltage down operation, e.g., DVC down operation). During this phase, which may be referred to as discharging phase, the switching circuit may be in the•fourth configuration. Accordingly, the second and third switching elements 92, 93 may be open and the first and fourth switching elements 91, 94 may be closed. Thus, the first capacitive element 80 may be coupled (e.g., connected) between the intermediate node 25 and ground (as an example of the first voltage level). Since the first voltage level is below the second voltage level, the voltage on the first capacitive element 80 is boosted down by a difference between the second voltage V.sub.refdvc and the first voltage (e.g., ground). For the first voltage corresponding to ground, the voltage on the first capacitive element 80 is boosted down by the second voltage V.sub.refdvc. Therefore, the second capacitive element 40 may be discharged, over the fourth switching element 94, to the first capacitive element 80. The current flow of during this phase is indicated by the bent arrow in FIG. 6B. At the same time, the control voltage V.sub.control decreases due to the electric charge shared between the first and second capacitive elements 80, 40. In particular, a voltage change of the control voltage V.sub.control (resulting voltage change at the end of the second phase) may be given by


    V.sub.control=ΔV.sub.out=−C.sub.F/(C.sub.C+C.sub.F).Math.V.sub.refdvc.

    [0068] For the first voltage level different from ground, V.sub.refdvc in the above equation would need to be replaced by the difference between the second voltage level and the first voltage level.

    [0069] Also here, the buffer stage 30 will drive the load capacitance (i.e., the output voltage V.sub.out) to follow the control voltage V.sub.control.

    [0070] As indicated above, the first and second phases of operation (voltage down operation, e.g., DVC down operation) may be alternatingly repeated until the output voltage V.sub.out is decreased down to the desired target voltage.

    [0071] FIG. 7A and FIG. 7B are time charts schematically illustrating voltage levels of the control voltage V.sub.control and the output voltage V.sub.out as well as control signal levels for the first to fourth switching elements 91-94 in the voltage regulator 400 for voltage up operation and voltage down operation, respectively.

    [0072] In FIG. 7A, the horizontal axis indicates time in arbitrary units, and the vertical axis indicates voltage in arbitrary units. Graphs 701, 702, 703, and 704, from top to bottom, indicate control signals for the first to fourth switching elements 91-94, respectively. A high level of the control signal indicates a closed state of the respective switching element, and a low level of the control signal indicates an open state of the respective switching element. Graph 705 indicates the voltage level of the output voltage V.sub.out. Graph 706 finally indicates the voltage level of the control voltage V.sub.control.

    [0073] At t=0, the switching circuit of the charge injection circuit 70 is in the first configuration (first phase of voltage up operation): The first and third switching elements 91, 93 are closed, and the second and fourth switching elements 92, 94 are open. During this phase, the first capacitive element 80 is charged and the control voltage V.sub.control and the output voltage V.sub.out remain substantially constant, apart from comparatively slow regulation by the error amplifier stage. Then, the switching circuit of the charge injection circuit 70 transitions (e.g., is switched) to the second configuration (second phase of voltage up operation): The first and third switching elements 91, 93 are open, and the second and fourth switching elements 92, 94 are closed. During this phase, the first capacitive element 80 is (partially) discharged into the second capacitive element 40 and the control voltage V.sub.control is gradually raised up to a total voltage change of ΔV.sub.control. The buffer stage 30 drives the output voltage V.sub.out to follow the control voltage V.sub.control. Then, the switching circuit of the charge injection circuit 70 transitions to the first configuration again, and the process repeats. During each full cycle of the first and second phases, the control voltage V.sub.control is raised by a total amount of V.sub.control that is determined by the capacitances of the first and second capacitive elements 80, 40 and the first and second voltage levels (in particular, a difference between these voltage levels).

    [0074] In FIG. 7B, graphs 711, 712, 713, and 714, from top to bottom, indicate control signals for the third, first, fourth, and second switching elements 93, 91, 94, 92, respectively. Graph 715 indicates the voltage level of the output voltage V.sub.out. Graph 716 finally indicates the voltage level of the control voltage V.sub.control.

    [0075] At t=0, the switching circuit of the charge injection circuit 70 is in the fourth configuration (second phase of voltage down operation). Then, the switching circuit transitions to the third configuration (first phase of voltage down operation): The second and third switching elements 92, 93 are closed, and the first and fourth switching elements 91, 94 are open. During this phase, the first capacitive element 80 is charged and the control voltage V.sub.control and the output voltage V.sub.out remain substantially constant, apart from comparatively slow regulation by the error amplifier stage. Then, the switching circuit of the charge injection circuit 70 transitions (e.g. is switched) to the fourth configuration (second phase of voltage down operation): The second and third switching elements 92, 93 are open, and the first and fourth switching elements 91, 94 are closed. During this phase, the second capacitive element 40 is (partially) discharged into the first capacitive element 80 and the control voltage V.sub.control is gradually lowered by a total voltage change of ΔV.sub.control. The buffer stage 30 drives the output voltage V.sub.out to follow the control voltage V.sub.control. Then, the switching circuit of the charge injection circuit 70 transitions to the third configuration again, and so forth. During each full cycle of the first and second phases, the control voltage V.sub.control is lowered by a total amount of ΔV.sub.control that is determined by the capacitances of the first and second capacitive elements 80, 40 and the first and second voltage levels (in particular, a difference between these voltage levels).

    [0076] FIG. 8 schematically illustrates yet another example of a voltage regulator 500 according to embodiments of the disclosure. The voltage regulator 500 of FIG. 8 may be seen as an exemplary, specific implementation of the voltage regulators 300, 400 of FIG. 3 and FIG. 4, respectively. Single or plural details of implementation of the below description may be employed in the context of the voltage regulators 300, 400, without the necessity to employ each and every detail of implementation. Some of these details of implementation relate to the switchable voltage divider circuit 10, the error amplifier stage, the buffer stage 30, and the charge injection circuit 70. Moreover, unless indicated otherwise, like-numbered elements in FIG. 3, FIG. 4, and FIG. 8 are identical and repeated description thereof is omitted for reasons of conciseness.

    [0077] In this specific example, the error amplifier 20 is implemented by transistors 21A, 21B, 21C, 21D, 21E. A bias voltage for the error amplifier 20 may be set at a control terminal (e.g., gate terminal) of transistor 21A. The reference voltage V.sub.REF may be input at the control terminal (e.g., gate terminal) of transistor 21B. Further in the specific example, the buffer stage 30 is implemented by transistors 31A, 31B, 31C, 31D, which form the first part of the buffer stage 30 and transistors 32A, 32B, 32C are the second part of the buffer stage 30. This buffer stage 30 is only able to source, but not sink current. Therefore, the sink stage is implemented in a similar manner by reusing the transistors of the first part 31A, 31B, 31C, 31D and adding transistors 33A, 33B, 33C, 33D, 33E for the second part to provide sink capability. Transistor 34A is a replica of Transistor 31A to match the voltage difference between the control voltage V.sub.control and the output voltage V.sub.out. Current source 34B is required to provide bias current for the replica transistor 34A. Transistor 33A determines, based on the output of the first part of the buffer stage formed by transistors 31A, 31B, 31C, 31D and it gate voltage, whether the source stage or the sink stage will be active. The aforementioned transistors may be FET or MOSFET transistors, such as PMOS transistors or NMOS transistors, for example. The main loop comprises the error amplifier stage and the buffer stage. Dotted arrows in FIG. 8 indicate the DVC up path, and dash-dotted arrows indicate the DVC down path. Notably, the voltage regulator 500 has five inversion stages in source or sink mode, thus resulting in negative feedback.

    [0078] In the voltage regulator 500, transistor 32C implements a source pass device, and transistor 33E implements a sink pass device. Since the sink pass device is smaller than the source pass device, the (absolute value of the) slope of change of the output voltage V.sub.out for voltage down operation in FIG. 7B is smaller than the respective slope for voltage up operation in FIG. 7A. Transistor 32B implements a diode with low capacitance.

    [0079] A voltage offset between the output voltage V.sub.out and the control voltage V.sub.control (the output voltage V.sub.out being lower by the offset voltage than the control voltage V.sub.control) may result from a threshold voltage of transistor 31A. Notably, such voltage offset may be compensated at transistor 34A.

    [0080] In alternative embodiments, the charge injection circuit 70 may be implemented by a controllable (e.g., switchable) current source, such as a controllable current source with source/sink capability. The controllable current source may operate under control of the control logic. The controllable current source may be configured to intermittently inject a predetermined (positive or negative) electric charge at the intermediate node 25 while the output voltage V.sub.out is desired to be raised or lowered.

    [0081] It should be noted that the apparatus features described above correspond to respective method features that may however not be explicitly described, for reasons of conciseness. The disclosure of the present document is considered to extend also to such method features. In particular, the present disclosure is understood to relate to methods of operating the circuits described above.

    [0082] It should further be noted that the description and drawings merely illustrate the principles of the proposed apparatus. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiment outlined in the present document are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the proposed method. Furthermore, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.