MICROELECTROMECHANICAL SYSTEM STRUCTURE AND METHOD FOR FABRICATING THE SAME

Abstract

A microelectromechanical system structure and a method for fabricating the same are provided. A method for fabricating a MEMS structure includes the following steps. A first substrate is provided, wherein a transistor, a first dielectric layer and an interconnection structure are formed thereon. A second substrate is provided, wherein a second dielectric layer and a thermal stability layer are formed on the second substrate. The first substrate is bonded to the second substrate, and the second substrate removed. A conductive layer is formed within the second dielectric layer and electrically connected to the interconnection structure. The thermal stability layer is located between the conductive layer and the interconnection structure. A growth temperature of a material of the thermal stability layer is higher than a growth temperature of a material of the conductive layer and a growth temperature of a material of the interconnection structure.

Claims

1. A microelectromechanical system (MEMS) structure, comprising: a substrate having a transistor thereon; a dielectric layer disposed on the substrate; an interconnection structure disposed within the dielectric layer and electrically connected to the transistor; a thermal stability layer disposed within the dielectric layer and located above the interconnection structure; and a conductive layer disposed within the dielectric layer and electrically connected to the interconnection structure, wherein the thermal stability layer is located in between the conductive layer and the interconnection structure, and wherein a growth temperature of a material of the thermal stability layer is higher than a growth temperature of a material of the conductive layer and a growth temperature of a material of the interconnection structure.

2. The MEMS structure according to claim 1, wherein the substrate and the dielectric layer further comprises a cavity formed therein, wherein the cavity exposes a region of the interconnection structure.

3. The MEMS structure according to claim 1, wherein the material of the thermal stability layer comprises polysilicon, low pressure silicon nitride (LP-SiN), or amorphous silicon.

4. The MEMS structure according to claim 1, wherein the material of the interconnection structure comprises Ti, TiN, Al, Ta, TaN, Cu, Ge, Au or Ni.

5. The MEMS structure according to claim 1, wherein the material of the conductive layer comprises Ti, TiN, Al, Ta, TaN, Cu, Ge, Au or Ni.

6. The MEMS structure according to claim 1, wherein the growth temperature of the material of the thermal stability layer is above 500° C.

7. The MEMS structure according to claim 1, wherein the growth temperature of the material of the interconnection structure is from 50° C. to 450° C.

8. The MEMS structure according to claim 1, wherein the growth temperature of the material of the conductive layer is from 50° C. to 450° C.

9. A method for fabricating a microelectromechanical system (MEMS) structure, comprising: providing a first substrate, wherein a transistor, a first dielectric layer and an interconnection structure are formed thereon, the transistor is disposed on the first substrate, the first dielectric layer is disposed on the first substrate and covering the transistor, and the interconnection structure is disposed within the first dielectric layer and electrically connected to the transistor; providing a second substrate, wherein a second dielectric layer and a thermal stability layer are formed on the second substrate, the second dielectric layer is disposed on the second substrate, and the thermal stability layer is located within the second dielectric layer; bonding the first substrate to the second substrate; removing the second substrate; and forming a conductive layer within the second dielectric layer, wherein the conductive layer is electrically connected to the interconnection structure, wherein the thermal stability layer is located between the conductive layer and the interconnection structure, and wherein a growth temperature of a material of the thermal stability layer is higher than a growth temperature of a material of the conductive layer and a growth temperature of a material of the interconnection structure.

10. The method for fabricating the MEMS structure according to claim 9, further comprises removing a part of the first substrate and a part of the first dielectric layer after forming the conductive layer to form a cavity that exposes a region of the interconnection structure.

11. The method for fabricating the MEMS structure according to claim 9, wherein bonding the first substrate to the second substrate is performed by fusion bonding between the first dielectric layer and the second dielectric layer.

12. The method for fabricating the MEMS structure according to claim 9, wherein the material of the thermal stability layer comprises polysilicon, low pressure silicon nitride, or amorphous silicon.

13. The method for fabricating the MEMS structure according to claim 9, wherein the material of the interconnection structure comprises Ti, TiN, Al, Ta, TaN, Cu, Ge, Au or Ni.

14. The method for fabricating the MEMS structure according to claim 9, wherein the material of the conductive layer comprises Ti, TiN, Al, Ta, TaN, Cu, Ge, Au or Ni.

15. The method for fabricating the MEMS structure according to claim 9, wherein the growth temperature of the material of the thermal stability layer is above 500° C.

16. The method for fabricating the MEMS structure according to claim 9, wherein the growth temperature of the material of the interconnection structure is from 50° C. to 450° C.

17. The method for fabricating the MEMS structure according to claim 9, wherein the growth temperature of the material of the conductive layer is from 50° C. to 450° C.

18. The method for fabricating the MEMS structure according to claim 9, wherein the first dielectric layer is formed by PECVD, SACVD or HDP-CVD.

19. The method for fabricating the MEMS structure according to claim 9, wherein the second dielectric layer is formed by PECVD, SACVD or HDP-CVD.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0027] FIG. 1A to FIG. 1F are sectional diagrams of the fabricating process of a MEMS structure according to an embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

[0028] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0029] FIG. 1A to FIG. 1F are sectional diagrams of the fabricating process of a MEMS structure according to an embodiment of the invention. Referring to FIG. 1A, the fabricating process of a MEMS structure of the invention includes providing a first substrate 102. The first substrate 102 is for example, a silicon substrate. A transistor 104, a first dielectric layer 110 and interconnection structure 105 are formed on the first substrate 102. The transistor 104 is disposed on the first substrate 102. The transistor 104 may be a MOS transistor, which includes a gate 104a, a gate dielectric layer 104b and doping regions 104c located in the substrate 102 at two sides of the gate 104a. In the embodiment, the doping regions 104c are used as a source and a drain of a transistor. Herein, the first substrate 102 is a so-called MOS substrate with a MOS device.

[0030] The first dielectric layer 110 is disposed on the first substrate 102 and covers the transistor 104. The material of the first dielectric layer 110 is for example, silicon oxide or other suitable dielectric materials. In the present embodiment. The first dielectric layer 110 for example includes, a first part 110a, a second part 110b and a third part 110c. The method of forming the first part 110a, the second part 110b and the third part 110c of the first dielectric layer 110 will be described in detail in the successive paragraphs below.

[0031] The interconnection structure 105 is disposed within the first dielectric layer 110 and electrically connected to the transistor 104. The material of the interconnection structure 105 includes Ti, TiN, Al, Ta, TaN, Cu, Ge, Au or Ni. The interconnection structure 105 may include a plurality of conductive plugs 106, 108 and a plurality of conductive layers 107, 109. In the present embodiment, the conductive layer 107 is located above the transistor 104, and is electrically connected to the transistor 104 through the conductive plugs 106. Furthermore, the conductive layer 109 is located above the conductive layer 107, and is electrically connected to the conductive layer 107 through conductive plugs 108. The method of forming the plurality of conductive plugs 106, 108 and the plurality of conductive layers 107, 109 will be described in detail in the successive paragraphs below.

[0032] After forming the transistor 104, the first dielectric layer 110 and the interconnection structure 105 is for example manufactured by the following method. Specifically, the first part 110a of the first dielectric layer 110 is formed on the substrate 102 and covers the transistor 104. A dual damascene process was performed so as to form the conductive plugs 106 and conductive layer 107 within the first part 110a of the dielectric layer 110. Herein, the conductive layer 107 is electrically connected to the transistor 104 through the conductive plugs 106. In the next step, the second part 110b of the first dielectric layer 110 is formed on the first part 110a and covers the conductive layer 107. Another dual damascene process was performed so as to form the conductive plugs 108 and conductive layer 109 within the second part 110b of the first dielectric layer 110. Herein, the conductive layer 109 is electrically connected to the conductive layer 107 through the conductive plugs 108. A third part 110c of the first dielectric layer 110 is then formed on the second part 110b. In the above embodiment, the growth temperature of the material of the interconnection structure 105 (material for forming conductive plugs 106 and 108 and conductive layers 107 and 109) is from 50° C. to 450° C. Furthermore, each of the first part 110a, the second part 110b and the third part 110c may be formed by PECVD, SACVD or HDP-CVD.

[0033] Although only two layers of conductive plugs 106, 108 with conductive layers 107, 109 are shown in the above embodiment, it should be noted that the number of layers of the conductive plugs and conductive layers are not particularly limited and this can be adjusted based on requirements. Furthermore, the first dielectric layer 110 is defined as all the parts that cover the interconnection structure 105. That is, the number of parts of the first dielectric layer 110 may vary depending on the layers of conductive layer used.

[0034] Next, referring to FIG. 1B, a second substrate 202 is provided. The second substrate 202 is for example, a silicon substrate. The second substrate 202 includes a second dielectric layer 208 and a thermal stability layer 204 that are formed on the second substrate 202. Herein, the thermal stability layer 204 refers to a layer with high growth temperature (above 500° C.). The thermal stability layer 204 may be used for the MEMS device. In the present embodiment, the second dielectric layer 208 for example includes a first part 208a and a second part 208b. The method of forming the first part 208a and the second part 208b of the second dielectric layer 208 will be described in detail in the successive paragraphs below. The material of the second dielectric layer 208 is for example, silicon oxide or other suitable dielectric materials. The material of the thermal stability layer 204 includes polysilicon, low pressure silicon nitride (LP-SiN) or amorphous silicon. Furthermore, the growth temperature of the material of the thermal stability layer 204 is above 500° C.

[0035] As shown in FIG. 1B, the second dielectric layer 208 and the thermal stability layer 204 are for example manufactured by the following method. Specifically, a first part 208a of the second dielectric layer 208 is formed to cover the second substrate 202. A thermal stability material layer is formed on top of the first part 208a and is patterned to form the thermal stability layer 204. A second part 208b of the second dielectric layer 208 is formed to cover the first part 208a and the thermal stability layer 204. In the above embodiment, each of the first part 208a and the second part 208b may be formed by PECVD, SACVD or HDP-CVD. Herein, the second substrate 202 is a so-called MEMS substrate with a MEMS device.

[0036] Next, referring to FIG. 1C, the first substrate 102 is bonded to the second substrate 202. In the embodiment, the bonding of the first substrate 102 to the second substrate 202 is performed by fusion bonding between the first dielectric layer 110 and the second dielectric layer 208. For instance, in an embodiment of the invention, a material of the first dielectric layer 110 and the second dielectric layer 208 is SiO.sub.2. As such, the first dielectric layer 110 may be bonded to the second dielectric layer 208 through siloxane (Si—O—Si) groups. However, the present invention is not particularly limited thereto, and other types of fusion bonding may be utilized.

[0037] Next, referring to FIG. 1D, the second substrate 202 is removed to expose a surface of the second dielectric layer 208. In the embodiment, the second substrate 202 is for example removed by using chemical-mechanical planarization (CMP) polishing, wherein a first part 208a of the second dielectric layer 208 is exposed after the CMP process. However, the method for removing the second substrate 202 is not particularly limited thereto and other known methods may be used.

[0038] Subsequently, referring to FIG. 1E, a conductive layer 302 is formed within the second dielectric layer 208 and conductive plug 304 are formed within the second dielectric layer 208 and the third part 110c of the first dielectric layer 110 through a dual damascene process, wherein the conductive layer 302 is electrically connected to the interconnect structure 105 through the conductive plug 304. In the present embodiment, the conductive layer 302 and the conductive plug 304 together constitute a second interconnection structure. The material of the second interconnection structure (conductive layer 302 and conductive plug 304) includes Ti, TiN, Al, Ta, TaN, Cu, Ge, Au or Ni. In addition, the material of the second interconnection structure (conductive layer 302 and conductive plug 304) may have a lower growth temperature (ex. 50° C. to 450° C.).

[0039] In the above embodiment, the growth temperature of the material of the second interconnection structure (conductive layer 302 and conductive plug 304) is from 50° C. to 450° C. Therefore, when fabricating the second interconnection structure, the low fabrication temperature will not affect the low growth temperature materials used in the interconnection structure 105 and the transistor 104 of the MOS device. That is, a good reliability of the MEMS structure can be obtained.

[0040] Finally, referring to FIG. 1F, a part of the first substrate 102 and a part of the first dielectric layer 110 are removed to form a cavity 306 that exposes a region of the interconnection structure 105 to complete a MEMS structure 10 of the invention. In the present embodiment, the cavity 306 exposes a portion of the conductive layer 107 of the interconnection structure 105. The part of the first substrate 102 and the part of the first dielectric layer 110 may be removed by dry etching to form a cavity 306, however, the invention is not particularly limited thereto.

[0041] In the above embodiment, the thermal stability layer 204 is formed between the conductive layer 302 and the interconnection structure 105. Furthermore, the growth temperature of the material of the thermal stability layer 204 is higher than the growth temperature of the material of the conductive layer 302 and the growth temperature of the material of the interconnection structure 105. Since the thermal stability layer 204 is pre-fabricated on the second substrate 202 with a high manufacturing/growth temperature prior to bonding the first substrate to the second substrate, therefore, the high growth temperature will not affect the low growth temperature materials used in the MOS device (interconnection structure 105 and transistor 104). In addition, since the second interconnection structure (conductive layer 302 and conductive plug 304) with a low manufacturing/growth temperature is fabricated after the bonding the first substrate to the second substrate, the low growth temperature will also not affect the low growth temperature materials used in the MOS device (interconnection structure 105 and transistor 104). As such, a good reliability of the MEMS structure can be achieved.

[0042] The MEMS structure according to an embodiment of the invention can be referred to the MEMS structure 10 according to FIG. 1F. For the MEMS structure of the invention, the thermal stability layer 204 is pre-fabricated on the second substrate 202 of the MEMS device and bonded to the first substrate of the MOS device, wherein the second interconnection structure (conductive layer 302 and conductive plug 304) is fabricated thereafter. As such, the thermal stability layer 204 having a high growth temperature will be located between the interconnection structure 105 and the conductive layer 302 having low growth temperatures. Therefore, a good reliability of the MEMS structure can be achieved.

[0043] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.