HYBRID CONTROL TECHNIQUE FOR POWER CONVERTERS

Abstract

A power conversion circuit includes a high-side MOSFET and a low-side MOSFET. A conduction terminal of the high-side MOSFET is coupled to a conduction terminal of the low-side MOSFET at a half-bridge (HB) circuit node. The high-side MOSFET is switched off. Voltage potential transitions of the HB circuit node are counted while the high-side MOSFET and low-side MOSFET are off. Assertion of a control signal to the low-side MOSFET is postponed for two voltage potential transitions of the HB circuit node after the high-side MOSFET is switched off. The low-side MOSFET is switched off by de-asserting the control signal to the low-side MOSFET. Switching on the high-side MOSFET is postponed for two voltage potential transitions of the HB circuit node after switching off the low-side MOSFET.

Claims

1. A method of generating a voltage signal, comprising: providing a power conversion circuit including a high-side MOSFET and a low-side MOSFET, wherein a conduction terminal of the high-side MOSFET is coupled to a conduction terminal of the low-side MOSFET at a half-bridge (HB) circuit node; switching off the high-side MOSFET; counting voltage potential transitions of the HB circuit node while the high-side MOSFET and low-side MOSFET are off; and postponing assertion of a control signal to the low-side MOSFET for two voltage potential transitions of the HB circuit node after switching off the high-side MOSFET.

2. The method of claim 1, further including: switching off the low-side MOSFET by de-asserting the control signal to the low-side MOSFET; and postponing switching on the high-side MOSFET for two voltage potential transitions of the HB circuit node after switching off the low-side MOSFET.

3. The method of claim 1, further including: postponing assertion of the control signal to the low-side MOSFET for a first number of valleys of a voltage potential of the HB circuit node after switching off the high-side MOSFET; and postponing switching on the high-side MOSFET for a second number of peaks of the voltage potential of the HB circuit node after switching off the low-side MOSFET, wherein the first number and second number are equal.

4. The method of claim 3, further including determining the first number based on output power, output voltage, or primary current of the power conversion circuit.

5. The method of claim 1, further including providing a capacitor coupled to the HB circuit node.

6. The method of claim 5, further including providing a switch coupled between the capacitor and the HB circuit node.

7. The method of claim 1, further including detecting voltage potential transitions of the HB circuit node using a dV/dt sensor.

8. A method of generating a power signal, comprising: providing a power conversion circuit including a first switch coupled to a second switch at a half-bridge (HB) circuit node; detecting voltage potential transitions of the HB circuit node; and counting peaks or valleys of the HB circuit node based on the voltage potential transitions while the first switch and second switch remain off.

9. The method of claim 8, further including: switching off the first switch; and switching on the second switch after a first number of peaks have elapsed since switching off the first switch.

10. The method of claim 9, further including: switching off the second switch; and switching on the first switch after a second number of valleys have elapsed since switching off the second switch, wherein the first number is equal to the second number.

11. The method of claim 9, further including determining the first number based on a feedback voltage or primary current of the power conversion circuit.

12. The method of claim 11, further including increasing the first number when the feedback voltage is reduced below a first threshold.

13. The method of claim 12, further including entering a skip mode when the feedback voltage is reduced below a second threshold.

14. The method of claim 8, further including coupling a switched capacitance to the HB circuit node.

15. A power conversion circuit, comprising: a first switch including a conduction terminal and a control terminal; a second switch including a conduction terminal of the second switch coupled to the conduction terminal of the first switch; a dV/dt sensor coupled to the conduction terminal of the first switch; and a valley/peak detection and lockout block including an input coupled to an output of the dV/dt sensor and an output of the valley/peak detection and lockout block configured to delay assertion of a control signal to the control terminal of the first switch.

16. The power conversion circuit of claim 15, wherein the valley/peak detection and lockout block further includes a counter configured to count peaks and valleys of voltage potential at the conduction terminal of the first switch based on the output of the dV/dt sensor.

17. The power conversion circuit of claim 15, further including a capacitor coupled to the conduction terminal of the first switch.

18. The power conversion circuit of claim 17, further including a third switch coupled between the capacitor and the conduction terminal of the first switch.

19. The power conversion circuit of claim 15, further including a transformer comprising a primary winding coupled to the conduction terminal of the first switch.

20. The power conversion circuit of claim 19, wherein the power conversion circuit is an LLC resonant mode converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG. 1 illustrates an exemplary electronic device that uses an LLC resonant mode converter;

[0033] FIGS. 2a-2f illustrate operation of a resonant mode LLC power converter;

[0034] FIG. 3 illustrates a circuit and block diagram of an LLC resonant mode converter that includes a quasi-resonant (QR) mode to increase efficiency at light loads;

[0035] FIGS. 4a-4b illustrate a dV/dt sensor;

[0036] FIGS. 5a-5c illustrate an LLC resonant mode converter operating in QR mode; and

[0037] FIG. 6 illustrates an LLC resonant mode converter with QR mode and a switched resonant capacitor.

DETAILED DESCRIPTION OF THE DRAWINGS

[0038] The following describes one or more embodiments with reference to the figures, in which like numerals represent the same or similar elements. While the figures are described in terms of the best mode for achieving certain objectives, the description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure.

[0039] FIG. 3 illustrates a switch-mode power supply (SMPS) 200. SMPS 200 is similar to SMPS 100, except that the controller of SMPS 200 implements a hybrid control technique for switching MOSFETs 112 and 116 under light load conditions. Rather than entering skip mode, and ceasing switching of MOSFETs 112 and 116 entirely, SMPS 200 enters a quasi-resonant (QR) mode that delays turning on MOSFETs 112 and 116 to lower the switching frequency while still periodically turning on MOSFETs 112 and 116 in an alternating fashion to maintain balanced operation. The controller of SMPS 200 aligns switching of MOSFETs 112 and 116 with peaks and valleys during resonant oscillations of the voltage potential at HB node 122 in order to maintain zero voltage switching (ZVS), reduce acoustic noise generation by SMPS 200, and improve light load efficiency.

[0040] As seen in FIG. 2f, after a pulse of control signal 118 to low-side MOSFET 116, HB node 122 resonates periodically even without additional input from MOSFET 112 or 116 turning on. Under normal frequency modulation operation, SMPS 100 always switches high-side MOSFET 112 on when the voltage potential of HB node 122 first reaches a peak, just after time 2 in FIG. 2f, by resonance between resonant inductor 128, primary winding 132, resonant capacitor 136, and other parasitic inductances and capacitances. HB node 122 and V.sub.IN node 110 are at approximately the same voltage potential, and there is nearly zero voltage drop across high-side MOSFET 112 when high-side MOSFET 112 is turned on.

[0041] In QR mode, SMPS 200 skips turning on high-side MOSFET 112 just after time 2. HB node 122 continues oscillating with the resonance of resonant inductor 128, primary winding 132, and resonant capacitor 136. SMPS 200 delays turning on high-side MOSFET 112 until a subsequent peak of HB node 122 is detected. The next pulse of control signal 114 to low-side MOSFET 116 is delayed by valley/peak detection and lockout block 224 until the second peak, third peak, or any other subsequent peak of the voltage potential at HB node 122. The number of peaks to delay for after each pulse of control signal 118 before turning on high-side MOSFET 112 is modified as needed to adjust the amount of power transferred from primary side 102 to secondary side 104. As long as high-side MOSFET 112 is turned on while the voltage potential of HB node 122 is near the voltage potential of V.sub.IN node 110, ZVS is achieved. The oscillations of HB node 122 are diminished over time so that the voltage peaks no longer reach V.sub.IN node 110. High-side MOSFET 112 is turned on during the peaks of HB node 122 to reduce switching losses even if ZVS is not achievable.

[0042] After eventually pulsing control signal 114 to turn on high-side MOSFET 112 during a peak of the voltage potential at HB node 122, SMPS 200 waits a similar number of valleys before turning on low-side MOSFET 116 again. A valley is the time when the voltage potential of HB node 122 is near the voltage potential of ground node 108, or at least near a local minimum. While HB node 122 is near the voltage potential of ground node 108, low-side MOSFET 116 is turned on with ZVS. If HB node 122 diminishes such that the voltage potential of HB node 122 does not reach the voltage potential of ground node 108, low-side MOSFET 116 is still turned on in the valleys of HB node 122 to reduce power losses and hard switching of MOSFET 116.

[0043] SMPS 200 continues alternating between pulsing control signal 114 to turn on high-side MOSFET 112, and pulsing control signal 118 to turn on low-side MOSFET 116, while delaying a number of valleys or a number of peaks between each pulse. Valley/peak detection and lockout block 224 increases the number of valleys or peaks to wait between each pulse as the load on SMPS 200 is further reduced. Valley/peak detection and lockout block 224 decreases the number of valleys or peaks skipped between each pulse as the load on SMPS 200 increases.

[0044] FIG. 3 illustrates portions of the controller of SMPS 200 as current sensing and processing block 202, dV/dt sensor 220, valley/peak detection and lockout block 224, T.sub.ON and T.sub.OFF modulation block 226, driver logic 230, and HB driver 232. While certain functionality of SMPS 200 is described as being performed by specific blocks, the described functionality may be split among functional blocks differently in other embodiments. Capacitor 201 represents the parasitic capacitances of MOSFETs 112 and 116 for purposes of analysis. Capacitors 204 and 206 form a voltage divider between primary winding 132 and ground node 108 with current sense (CS) node 208 between capacitors 204 and 206 coupled to current sensing and processing block 202. Resistor 210 is coupled between CS node 208 and ground node 108 in parallel with capacitor 206.

[0045] Current sensing and processing block 202 senses the resonant current through primary winding 132 by observing the voltage potential of CS node 208. Current sensing and processing block 202 is also coupled to FB node 160 to observe the voltage potential of V.sub.OUT node 150. Current sensing and processing block 202 provides a metric signal 203 to valley/peak detection and lockout block 224. Valley/peak detection and lockout block 224 compares metric signal 203 against thresholds to determine when to enter or exit QR mode, and how many peaks or valleys to skip when in QR mode. Metric signal 203 can be based solely on FB node 160, CS node 208, another desired metric, or a combination thereof. Current sensing and processing block 202 also generates a turn-off signal 205 that tells T.sub.ON and T.sub.OFF modulation block 226 to switch off whichever MOSFET 112 or 116 is turned on based on a comparison between FB node 160 and CS node 208.

[0046] The dV/dt sensor 220 includes an input coupled to HB node 122 and outputs dV/dt signal 222 to valley/peak detection and lockout block 224. Valley/peak detection and lockout block 224 receives dV/dt signal 222 to determine when peaks and valleys of voltage potential at HB node 122 occur. In one embodiment, dV/dt signal 222 comprises two separate one-bit outputs, negative dV/dt signal 222a and positive dV/dt signal 222b. The dV/dt sensor 220 outputs a logic one value on negative dV/dt signal 222a when a magnitude of −dV/dt on HB node 122 is greater than a threshold. Otherwise, negative dV/dt signal 222a is output as a logic zero value, i.e., while the voltage potential at HB node 122 is rising or not changing significantly. Similarly, dV/dt sensor 220 outputs a logic one value on positive dV/dt signal 222b when a magnitude of dV/dt on HB node 122 is greater than a threshold. Otherwise, dV/dt sensor 220 outputs a logic zero value at positive dV/dt signal 222b, i.e., when the voltage potential of HB node 122 is falling or not changing significantly. Other signaling schemes for detecting and communicating valleys and peaks of HB node 122 are used in other embodiments.

[0047] FIG. 4a illustrates one embodiment of dV/dt sensor 220. The dV/dt sensor 220 includes HB node 122 as an input, and outputs dV/dt signals 222a and 222b. Op-amp 260 is configured as a differentiator by capacitor 264 and resistor 266. The output of op-amp 260 at circuit node 270 is a voltage potential approximately proportional to dV/dt of HB node 122 due to the configuration of op-amp 260 as a differentiator. Op-amp 261 is configured to compare the dV/dt of HB node 122, represented by the voltage potential at circuit node 270, against a negative dV/dt threshold voltage 272. If the voltage potential at circuit node 270 is below negative dV/dt threshold voltage 272, then negative dV/dt signal 222a is asserted by op-amp 261. Op-amp 262 compares the voltage potential at circuit node 270 against positive dV/dt threshold voltage 274 and asserts positive dV/dt signal 222b if the positive dV/dt of HB node 122 exceeds the threshold. In one embodiment, op-amp 260 and resistor 266 are not used, and capacitor 264 is directly coupled to inputs of op-amps 261 and 262.

[0048] FIG. 4b illustrates operation of dV/dt sensor 220. The voltage potential at HB node 122 drops relatively rapidly near time 1 once high-side MOSFET 112 is turned off. The falling voltage potential at HB node 122 causes the voltage potential at circuit node 270 to be reduced below threshold voltage 272, and negative dV/dt signal 222a is asserted while HB node 122 falls near time 1. Between time 1 and time 2, the voltage potential of HB node 122 is relatively steady, and neither of dV/dt signals 222a and 222b are asserted. Low-side MOSFET 116 is switched off at time 2, and driver logic 230 ceases switching of MOSFETs 112 and 116 as in FIG. 2f. However, primary side 102 continues to resonate after low-side MOSFET 116 is switched off at time 2, and HB node 122 oscillates between the voltage potentials of V.sub.IN node 110 and ground node 108 while also diminishing over time.

[0049] Around time 2 in FIG. 4b, while the LLC tank of SMPS 200 begins to resonate, the voltage potential of HB node 122 rises from the voltage potential of ground node 108 to the voltage potential of V.sub.IN node 110. The voltage potential rise over time, or dV/dt, of HB node 122 causes the voltage potential at circuit node 270 to exceed the threshold voltage 272 in dV/dt sensor 220, and positive dV/dt signal 222b is asserted. HB node 122 continues to oscillate between ground node 108 and V.sub.IN node 110 while diminishing after time 2. The dV/dt signals 222 continue pulsing at the transitions of HB node 122.

[0050] Valley/peak detection and lockout block 224 receives dV/dt signals 222, which indicate when peaks and valleys of the voltage potential at HB node 122 occur. A voltage peak of HB node 122 is reached when the voltage potential of HB node 122 substantially stops rising. A voltage potential peak occurs when HB node 122 is at approximately the highest voltage potential value of HB node 122, at least for a particular resonant cycle. A valley of HB node 122 is a negative peak, i.e., reached when the voltage potential of HB node 122 substantially stops falling. A valley of HB node 122 means that approximately the lowest voltage potential value for a particular resonant cycle is reached.

[0051] A positive, or logic one, value of negative dV/dt signal 222a indicates that the voltage potential of HB node 122 is actively falling. A positive value of positive dV/dt signal 222b indicates that the voltage potential of HB node 122 is actively increasing. Negative transitions, i.e., a transition from a logic one value to a logic zero value, of negative dV/dt signal 222a indicate that a period of negative voltage change on HB node 122 has ended, and thus a valley has been reached. The voltage potential of HB node 122 remains substantially within a valley, i.e., near a local minimum, until the voltage potential at HB node 122 begins to rise again and positive dV/dt signal 222b is asserted by dV/dt sensor 220. Valley/peak detection and lockout block 224 understands the voltage potential of HB node 122 to be in a valley between a pulse of negative dV/dt signal 222a and a pulse of positive dV/dt signal 222b.

[0052] Negative transitions of positive dV/dt signal 222b indicate that a period of positive voltage change on HB node 122 has ended and a peak has been reached. The voltage potential of HB node 122 remains substantially within a peak, i.e., near a local maximum, until the voltage potential at HB node 122 begins to fall again and negative dV/dt signal 222a is asserted by dV/dt sensor 220. Valley/peak detection and lockout block 224 understands the voltage potential of HB node 122 to be in a peak between a pulse of positive dV/dt signal 222b and a pulse of negative dV/dt signal 222a.

[0053] Returning to FIG. 3, valley/peak detection and lockout block 224 receives information pertaining to output voltage potential at V.sub.OUT node 150, the electric current through primary winding 132, or another metric as metric signal 203. Valley/peak detection and lockout block 224 uses metric signal 203 to detect the load on SMPS 200 coupled to V.sub.OUT node 150, and then determines when conditions indicate QR mode should be entered and how many valleys and peaks should be skipped before each pulse of control signals 114 and 118. QR mode is entered based on output power of SMPS 200, output current, resonant current, or another appropriate metric in various embodiments.

[0054] As the load on SMPS 200 decreases, metric signal 203 from current sensing and processing block 202 shifts in recognition that less power is required to be transferred from primary side 102 to secondary side 104. Valley/peak detection begins inserting breaks between pulses of control signals 114 and 118 when metric signal 203 moves across a QR mode turn-on threshold. In other embodiments, primary current sensing and processing block 202 determines when QR mode should be entered, and communicates a number of valleys/peak to skip using signal 203.

[0055] T.sub.ON and T.sub.OFF modulation block 226 is responsible for timing of transitions of control signals 114 and 118. When a MOSFET 112 or 116 is turned on, T.sub.ON and T.sub.OFF modulation block 226 receives turn-off signal 205 from a comparator in current sensing and processing block that compares CS node 208 against FB node 160. T.sub.ON and T.sub.OFF modulation block 226 switches off control signal 114 or 118 once the CS node 208 voltage potential crosses the FB node 160 voltage potential. In some embodiments, current sensing and processing block 202 shifts or divides the voltage potentials of FB node 160 or CS node 208 prior to the comparison to generate turn-off signal 205.

[0056] After switching off a control signal 114 or 118 under normal operation, T.sub.ON and T.sub.OFF modulation block 226 waits a dead-time period to allow resonance to carry HB node 122 from ground potential to line voltage potential, or vice versa, and then turns on the opposite control signal 114 or 118. However, when current sensing and processing block 202 and valley/peak detection and lockout block 224 have turned on QR mode, a delay signal 225 from valley/peak detection and lockout block 224 to T.sub.ON and T.sub.OFF modulation block 226 causes the T.sub.ON and T.sub.OFF modulation block to insert additional delay in turning on the opposite control signal. In some embodiments, delay signal 225 is a one-bit digital signal. In other embodiments, separate signals are used for delaying control signal 114 and delaying control signal 118.

[0057] Valley/peak detection and lockout block 224 asserts delay signal 225 to T.sub.ON and T.sub.OFF modulation block 226 when QR mode is entered. Delay signal 225 stops T.sub.ON and T.sub.OFF modulation block 226 from immediately turning on a MOSFET 112 or 116. Valley/peak detection and lockout block 224 counts peaks or valleys of HB node 122 based on pulses of dV/dt signal 222 until a desired number of valleys or peaks have been skipped. The number of peaks or valleys to skip is indicated by comparing metric signal 203 against a plurality of thresholds within valley/peak detection and lockout block 224. Once the number of valleys or peaks have passed, valley/peak detection and lockout block 224 de-asserts delay signal 225 and T.sub.ON and T.sub.OFF modulation block 226 directs driver logic block 230 to assert the next control signal 114 or 118. T.sub.ON and T.sub.OFF modulation block 226 acknowledges that the next MOSFET 112 or 116 was turned on using a return signal to valley/peak detection and lockout block 224. Valley/peak detection and lockout block 224 asserts delay signal 225 again, and begins counting peaks or valleys for the next delay.

[0058] Driver logic 230 creates the control signals to gates 114 and 118 based on signals received from T.sub.ON and T.sub.OFF modulation block 226, and outputs the control signals to HB driver block 232. HB driver block 232 is an amplifier that provides the output current necessary to switch MOSFETs 112 and 116.

[0059] By entering quasi-resonant mode, SMPS 200 omits some switching periods to reduce the effective operating frequency. Magnetizing current is reduced, which increases overall efficiency due to magnetizing current contributing less to power losses during light load operation. SMPS 200 still operates in continuous operation mode, even when QR mode is enabled, by regularly issuing pulses that alternatively turn on MOSFETs 112 and 116 under ZVS conditions. The continued switching of MOSFETs 112 and 116 with delayed turn-on times reduces acoustic noise of SMPS 200 relative to entering skip mode and temporarily stopping all switching of the MOSFETs. SMPS 200 omits switching pulses in a controlled manner during QR mode rather than stopping all switching as in skip mode.

[0060] In QR mode, SMPS 200 detects parasitic ringing peaks and valleys and activates the opposite switch in those time periods, when power losses are reduced. Similar delays are utilized prior to turning on high-side MOSFET 112 and low-side MOSFET 116 so that SMPS 200 operates symmetrically. More parasitic oscillation periods are omitted when load is reduced further. In some embodiments, skip mode is entered, or SMPS 200 is switched completely off, when the load is reduced sufficiently or completely disconnected.

[0061] FIGS. 5a-5c illustrate SMPS 200 operating in QR mode. The X, or horizontal, axes in FIGS. 5a-5c illustrate the passage of time. The X-axes are labelled to show approximate times when HB node 122 transitions, rather than in units of time. The Y, or vertical, axes in FIGS. 5a-5c illustrate voltage potentials or logical values. In FIG. 5a, the load of SMPS 200 has fallen below a first threshold for valley/peak detection and lockout block 224 determining that one valley and one peak should be skipped each power cycle. Low-side MOSFET 116 is turned on by control signal 118 between time 1 and time 2 in FIG. 5a. HB node 122 is coupled to ground node 108 by low-side MOSFET 116 between time 1 and time 2, and is held at approximately ground potential. The voltage potential of HB node 122 falling to ground potential around time 1 causes negative dV/dt signal 222a to be briefly asserted at approximately time 1, indicating a negative dV/dt on HB node 122.

[0062] At time 2 in FIG. 5a, after control signal 118 is de-asserted, energy in the resonant tank of SMPS 200 transitions HB node 122 to near the voltage potential of V.sub.IN node 110. Under normal frequency modulation operation, T.sub.ON and T.sub.OFF modulation block 226 would cause driver logic 230 to assert control signal 114 and turn on high-side MOSFET 112 once the voltage potential of HB node 122 reaches approximately the voltage potential of V.sub.IN node 110. However, SMPS 200 is in QR mode, and valley/peak detection and lockout block 224 asserts delay signal 225 to T.sub.ON and T.sub.OFF modulation block 226 to skip turning on high-side MOSFET 112 during peak 300 of HB node 122.

[0063] The positive transition of HB node 122 around time 2 in FIG. 5a is detected by dV/dt sensor 220 and a pulse of positive dV/dt signal 222b is observed at approximately time 2. The pulse of positive dV/dt signal 222b results in a counter in valley/peak detection and lockout block 224 being incremented or decremented. The voltage potential of HB node 122 returns to approximately ground potential at time 3, but low-side MOSFET 116 is not turned on. Low-side MOSFET 116 was the most recent MOSFET turned on, so SMPS 200 is waiting for a peak of HB node 122 to turn on high-side MOSFET 112 to maintain balanced operation.

[0064] At approximately time 4, resonance returns the voltage potential at HB node 122 to approximately the voltage potential of V.sub.IN node 110. HB node 122 remains in peak 302 between time 4 and time 5. The pulse of positive dV/dt signal 222b around time 4 causes valley/peak detection and lockout block 224 to de-assert delay signal 225 to T.sub.ON and T.sub.OFF modulation block 226 since the counter in valley/peak detection and lockout block 224 has been incremented or decremented to the desired threshold to skip one peak. De-asserting delay signal 225 by valley/peak detection and lockout block 224 signals T.sub.ON and T.sub.OFF modulation block 226 to start the next pulse of control signal 114 to turn on high-side MOSFET 112 at time 4.

[0065] After high-side MOSFET 112 is turned off at time 5 in FIG. 5a, the voltage potential at HB node 122 returns to approximately ground potential and stays in valley 304 between time 5 and 6. A counter in valley/peak detection and lockout block 224 is incremented or decremented to indicate that a valley was skipped and the next valley should produce a pulse of control signal 118. HB node 122 rises to approximately the voltage potential of V.sub.IN node 110 at time 6, and returns low to be in valley 306 between time 7 and time 8. Since valley 304 was skipped, and the current power output of SMPS 200 indicates that only one valley should be skipped each power cycle, the pulse of negative dV/dt signal 222a at time 7 causes valley/peak detection and lockout block 224 to de-assert delay signal 225 so that control signal 118 is asserted from time 7 to time 8 and valley 306 is not skipped.

[0066] The cycle restarts, with SMPS 200 skipping peak 300 from time 8 to time 9 in FIG. 5a, and asserting control signal 114 from time 10 to time 11 during peak 302. During QR mode when one peak and one valley is skipped per power cycle, SMPS 200 skips a peak 300 after each assertion of control signal 118. SMPS 200 asserts control signal 114 to turn on high-side MOSFET 112 during peak 302, which is the second peak of HB node 122 to occur after control signal 118 is de-asserted. To keep approximately symmetrical operation, SMPS 200 similarly skips a valley 304 after each assertion of control signal 114 to high-side MOSFET 112. SMPS 200 asserts control signal 118 to low-side MOSFET 116 during valley 306, which is the second valley to occur after each assertion of control signal 114.

[0067] SMPS 200 continues operating as shown in FIG. 5a, skipping one peak 300 and one valley 304 during each power cycle, until the load of SMPS 200 crosses a threshold. If the load of SMPS 200 increases over a threshold, QR mode will cease. SMPS 200 will assert control signal 114 to high-side MOSFET 112 during each peak of HB node 122, and will also assert control signal 118 to low-side MOSFET 116 during each valley of HB node 122. If the load of SMPS 200 is reduced below a threshold, the QR mode will be modified to skip additional peaks and additional valleys during each power cycle as illustrated in FIGS. 5b and 5c. In some embodiments, the QR mode transitions include a built-in hysteresis to reduce the likelihood that SMPS 200 rapidly moves back and forth between two states.

[0068] In FIG. 5b, the load on SMPS 200 has been reduced below a threshold indicating that three peaks and three valleys should be skipped each power cycle. Control signal 118 to low-side MOSFET 116 is asserted from time 1 to time 2 in FIG. 5b, similar to FIG. 5a. After control signal 118 is lowered at time 2, HB node 122 oscillates between the voltage potential of ground node 108 and the voltage potential of V.sub.IN node 110 as in FIG. 2f. Positive dV/dt signal 222b pulses at times 2, 4, 6, and 8 in FIG. 5b to indicate the beginning of peaks 320, 322, 324, and 326, respectively. The positive dV/dt signal 222b pulses at times 2, 4, and 6 increment the counter in valley/peak detection and lockout block 224. Just prior to time 8, the counter indicates that three pulses, 320, 322, and 324, have been skipped, so valley/peak detection and lockout block 224 de-asserts delay signal 225 when peak 326 is detected. Control signal 114 to high-side MOSFET 112 is asserted during peak 326 because delay signal 225 was de-asserted.

[0069] Control signal 114 to high-side MOSFET 112 is de-asserted at time 9, and HB node 122 again oscillates between the voltage potentials of ground node 108 and V.sub.IN node 110. Valley/peak detection and lockout block 224 counts and skips valleys 330, 332, and 334. At time 15 in FIG. 5b, the counter in valley/peak detection and lockout block 224 indicates that three valleys have been skipped, so the pulse of negative dV/dt signal 222a at time 15 causes the valley/peak detection and lockout block to de-assert delay signal 225 so that control signal 118 to low-side MOSFET 116 is asserted during valley 336 from time 15 to time 16.

[0070] SMPS 200 continues skipping three peaks 320, 322, and 324 after each pulse of control signal 118 to low-side MOSFET 116, and three valleys 330, 332, and 334 after each pulse of control signal 114 to high-side MOSFET 112, while the load of SMPS 200 stays within the thresholds for skipping three peaks and three valleys per power cycle. SMPS 200 remains approximately balanced and symmetrical because pulses of control signals 114 and 118 alternate and are approximately evenly spaced. QR mode allows SMPS 200 to reduce switching frequency, reducing magnetizing current through transformer 130, without increasing the power transfer from primary side 102 to secondary side 104.

[0071] FIG. 5c illustrates SMPS 200 with a load reduced beyond a threshold for skipping twelve peaks and twelve valleys each power cycle. SMPS 200 asserts control signal 118 to low-side MOSFET 116 from time 1 to time 2 in FIG. 5c. Low-side MOSFET 116 couples HB node 122 to ground node 108 from time 1 to time 2. HB node 122 oscillates with resonance after low-side MOSFET 116 is turned off at time 2, and valley/peak detection and lockout block 224 asserts delay signal 225. The dV/dt sensor 220 pulses positive dV/dt signal 222b to valley/peak detection and lockout block 224 at each rising edge of HB node 122. Valley/peak detection and lockout block 224 counts thirteen pulses of positive dV/dt signal 222b before de-asserting delay signal 225 to skip twelve peaks 350a-350l of HB node 122. In other embodiments, valley/peak detection and lockout block 224 counts twelve pulses of negative dV/dt signal 222a to skip twelve peaks 350a-350l.

[0072] On the rising edge of the thirteenth peak, 350m, of HB node 122, the counter in valley/peak lockout block 224 indicates the desired number of peaks has been skipped. Delay signal 225 is de-asserted by valley/peak detection and lockout block 224 to indicate that T.sub.ON & T.sub.OFF modulation block 226 should allow the next control signal 114 or 118 to be asserted. Since control signal 118 to lower MOSFET 116 was most recently asserted, from time 1 to time 2, driver logic 230 asserts control signal 114 to high-side MOSFET 112 at time 3 in FIG. 5c. Once control signal 114 is turned off at time 4, SMPS 200 skips twelve valleys of HB node 122 and turns control signal 118 to low-side MOSFET 116 back on. Alternating between turning on high-side MOSFET 112 and low-side MOSFET 116 maintains balanced operation of SMPS 200 even though the pulses are delayed to skip a certain number of valleys and peaks of HB node 122.

[0073] In FIG. 5c, the load on SMPS 200 is relatively low. Inserting a delay of twelve peaks and twelve valleys each power cycle results in MOSFETs 112 and 116 turning on when the voltage oscillations on HB node 122 have significantly diminished. The peaks of HB node 122 no longer reach the input voltage potential at V.sub.IN node 110, and the valleys no longer reach the voltage potential of ground node 108. ZVS is not achieved because the voltage potential of HB node 122 does not fully reach the input voltage or ground voltage. High-side MOSFET 112 is switched on near peaks of HB node 122, and low-side MOSFET 116 is switched on near valleys, so that switching losses attributed to turning on MOSFETs 112 and 116 are reduced even though ZVS may not be attained.

[0074] When the load of SMPS 200 is even further reduced, and QR mode skips a greater number of valleys and peaks each cycle, switching losses may be significantly increased as HB node 122 diminishes further before MOSFETs 112 and 116 are turned on, as in FIG. 2f. An output power threshold of SMPS 200 exists, below which the switching losses of MOSFETs 112 and 116 are increased so far that QR mode is exited and skip mode is enabled. Both MOSFETs 112 and 116 remain turned off until more power is needed to be transferred from primary side 102 to secondary side 104.

[0075] QR mode is entered by SMPS 200 when output load is reduced and magnetizing current becomes the dominating contributor to power losses in the power converter. When QR mode is entered, SMPS 200 begins to omit switching pulses in a controlled manner. After high side MOSFET 112 is switched off, HB node 122 swings between ground level and input voltage level naturally based on energy stored in resonant inductor 128 and resonance with resonant capacitor 136. QR mode of SMPS 200 omits turning on low-side MOSFET 116 when HB node 122 initially swings to a valley near ground node 108 to reduce power transferred to secondary side 104. The body diode of low-side MOSFET 116 conducts for a period of time until the energy stored in resonant inductor 128 is diminished. Thereafter, oscillation occurs between total primary side 102 inductance, e.g., primary winding 132 and resonant inductor 128, and HB node 122 capacitance, e.g., capacitor 201 and other stray capacitances of PCB 52 and transformer 130. The resonant oscillations swing HB node voltage up and down between ground and input voltages.

[0076] The amplitude of the parasitic oscillation decays with time as shown in FIG. 2f. QR mode of SMPS 200 detects peaks and valleys of the parasitic ringing and activates the opposite switch during the time when switching losses are substantially minimized. That is, low-side MOSFET 116 is activated during valleys of HB node 122 when voltage across low-side MOSFET 116 is nearly zero, and high-side MOSFET 112 is activated during peaks of HB node 122 when voltage across high-side MOSFET 112 is nearly zero. Symmetrical operation is achieved when QR mode is activated by skipping a similar number of peaks before activating high-side MOSFET 112 and valleys before activating low-side MOSFET 116. As the output power drops further, additional parasitic oscillation periods are omitted in order to further prolong off-time between driver pulses and further reduce energy transferred to secondary side 104. SMPS 200 transitions into skip mode or off-mode in cases when the load is lowered beyond levels where QR mode provides efficiency gains.

[0077] Hysteresis is used when switching between frequency modulation mode, QR mode, and skip mode so that SMPS 200 does not oscillate between two modes. Hysteresis is also used within QR mode when switching the number of valleys and peaks to skip. The threshold required for transitioning between QR mode skipping two peaks/valleys and QR mode skipping three peaks/valleys is lower than the threshold output power must meet to return back to only skipping two peaks/valleys from skipping three peaks/valleys. Skipping a similar number of peaks as valleys, alternating between turning on high-side MOSFET 112 and low-side MOSFET 116, and using a similar turn-on time between high-side MOSFET 112 and low-side MOSFET 116, results in balanced operation that reduces switching frequency at light loads.

[0078] In QR mode, the on-times of high-side MOSFET 112 and low-side MOSFET 116 continue to be controlled by current sensing and processing block 202 based on a similar comparison between FB node 160 and CS node 208 as in frequency modulation mode. In some embodiments, pulse widths of control signals 114 and 118 are increased when SMPS transitions from frequency modulation mode to QR mode. Even though on-times of MOSFETs 112 and 116 may be longer each pulse, less total power is transferred from primary side 102 to secondary side 104 over time due to pulses being omitted. In some embodiments, the feedback loop transfer characteristics with respect to current through primary winding 132, as detected at CS node 208, change slope when QR mode is activated in order to reduce gain characteristic discontinuities.

[0079] In some embodiments, there may be a desire to slow down the parasitic oscillations between capacitance of HB node 122 and total inductance connected in series on primary side 102. FIG. 6 illustrates an LLC resonant mode converter embodiment as SMPS 360 with additional capacitors coupled to HB node 122 to slow the resonant oscillations. Capacitor 362 is coupled between HB node 122 and V.sub.IN node 110. Capacitor 364 is coupled between HB node 122 and ground node 108. Capacitor 366 and switch 370 are coupled in series between HB node 122 and ground node 108. Control signal 372 from T.sub.ON and T.sub.OFF modulation block 226 operates switch 370. In other embodiments, control signal 372 is generated by valley/peak detection and lockout block 224.

[0080] Capacitors 362 and 364 are connected in parallel with MOSFETs 112 and 116, respectfully, and increase the total capacitance of HB node 122. The increased capacitance slows the oscillations of HB node 122 seen in FIG. 2f to increase the amount of time between pulses of control signals 114 and 118 during QR mode. With a larger capacitance of HB node 122, skipping a specific number of peaks and valleys, e.g., 4 peaks, takes a longer amount of time than with only capacitor 201. Adding capacitors 362 and 364 increases efficiency at light load by allowing more time between pulses of control signals 114 and 118. On the other hand, capacitors 362 and 364 may impact full load efficiency.

[0081] Another solution is to use switchable capacitor 366. Capacitor 366 is switchable using control signal 372 and switch 370. In one embodiment, switch 370 is a MOSFET on a common integrated circuit with the controller of SMPS 360. SMPS 360 opens switch 370 during normal frequency modulation operation because additional capacitance on HB node 122 is not desired, and potentially reduces efficiency of SMPS 360. SMPS 360 closes switch 370 during QR mode to couple capacitor 366 between HB node 122 and ground node 108. Switch 370 and capacitor 366 allow the resonant oscillation period of SMPS 360 to be extended during QR mode without a significant impact on efficiency during frequency modulation mode. Switch 370 may be opened during skip mode to reduce power consumption of SMPS 360 during very light or no load conditions. Magnetizing current, which causes a large portion of losses during light load operation is reduced, and overall efficiency is increased.

[0082] Capacitors 362, 364, and 366 are all used in one embodiment. In other embodiments, only one or two of the capacitors are added to SMPS 200 to create SMPS 360. Switch 370 and capacitor 366 are used in one embodiment without capacitors 362 and 364 to increase efficiency during light load with a lower impact on efficiency during medium and heavy loads. In other embodiments, capacitors 362 and 364 are used without capacitor 366 and switch 370. In one embodiment, switch 370 and capacitor 366 are used along with another switched capacitor coupled between V.sub.IN node 110 and HB node 122.

[0083] While one or more embodiments have been illustrated and described in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present disclosure.