Semiconductor device and power supply unit utilizing the same

Abstract

A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.

Claims

1. A semiconductor device comprising external terminals and incorporating a switch circuit composed of a transistor switch, wherein the external terminals are arranged along one side of the semiconductor device, and wherein an output end of the switch circuit is connected to a plurality of terminals out of the external terminals inside the semiconductor device, and the plurality of terminals are connected together outside the semiconductor device.

2. The semiconductor device according to claim 1, wherein the transistor switch is a bipolar transistor.

3. The semiconductor device according to claim 1, wherein the transistor switch is a MOSFET.

4. The semiconductor device according to claim 1, wherein the plurality of terminals are arranged such that at least one other terminal is located between every two of the plurality of terminals.

5. The semiconductor device according to claim 4, wherein the other terminal is a terminal in which no current, or only an extremely small current compared with a current passing through the switch circuit, passes.

6. The semiconductor device according to claim 4, wherein the plurality of terminals are all outermost peripheral terminals among the external terminals.

7. The semiconductor device according to claim 1, wherein the external terminals are ball grid alley terminals.

8. The semiconductor device according to claim 1, further comprising a drive circuit which turns the transistor switch on and off, wherein as the switch circuit is turned on and off, an input voltage is converted into an output voltage, which is output.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a circuit arrangement of an IC in accordance with one embodiment of the invention and an inventive power supply unit utilizing the IC.

(2) FIG. 2 shows a BGA structure of terminals on one side of the IC of FIG. 1.

(3) FIG. 3 shows a circuit arrangement of a conventional switching power supply unit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

(4) An inventive semiconductor device and a power supply unit utilizing the same will now be described by way of example with reference to the accompanying drawings.

(5) Referring to FIG. 1, there is shown schematically an IC 10A in accordance with one embodiment of the invention and a power supply unit utilizing the IC 10A. The IC 10A includes an IC chip 11A. FIG. 2 shows a ball grid array (BGA) structure in which pluralities of ball terminals are arranged in a lattice configuration on one side of the IC 10A.

(6) Symbols Lo, Do, Co, Vin, and Vout of FIG. 3 respectively refer to a coil, a diode, a capacitor, an input voltage, and an output voltage, as in FIG. 1.

(7) The IC 10A is a WL-CSP type IC having a reduced size. The IC 10A is a WL-CSP type IC having a reduced size. Formed on one side (e.g. backside) of the IC 10A is a BGA structure of ball terminals B1-1-Bn-m arrayed in m rows and n columns, as shown in FIG. 2.

(8) Referring back to FIG. 1, there are shown a switch circuit consisting of transistor switches Q1-Q3, and a drive circuit 20 for driving these transistor switches Q1-Q3, all formed in the IC 10A. Although the transistor switches Q1-Q3 of the example shown herein are NPN bipolar transistors, they can be of another type of transistors such as MOSFETs for example. These transistor switches Q1-Q3 are simultaneously switched on and off by an ON-OFF drive signal issued from the drive circuit 20.

(9) The switch circuit is shown having three transistor switches Q1-Q3, but it may have only one transistor switch. However, from the point of preventing the switch circuit from being influenced by breaking of wires and/or loose connection of terminals, it is preferred to provide the switch circuit with at least two transistor switches. Furthermore, if the switch circuit has more than one transistor switch, it has extra current drive capability.

(10) The collectors of the transistor switches Q1-Q3 are respectively connected to multiple ball terminals B2-1, B4-1, and B6-1 belonging to the BGA terminals B1-1-Bn-m via the respective pads P2-1, P4-1, P6-1 of the IC chip 11A and the bumps associated with the pads. These collectors are preferably connected with one another.

(11) The multiple ball terminals B2-1, B4-1, and B6-1 to which the respective collectors of the transistor switches Q1-Q3 are connected are also connected to one another outside the IC 10A. The multiple ball terminals B2-1, B4-1, and B6-1 coupled together are connected to the node of the coil Lo and the diode Do.

(12) It should be understood that although three ball terminals are connected to the coil Lo in the example shown, two ball terminals will be sufficient in order to shunt the current Io. However, to ensure reduction of Joule heat due to the resistance Rb of a ball terminal (including contact resistance and wiring resistance) and to prevent the switching circuit from being influenced by breaking of wires and/or loose contact of pads, more than two wires are preferably connected to the coil Lo.

(13) As the transistor switches Q1-Q3 are turned on, the current Io flowing through the coil Lo increases with time. The current Jo is shunted evenly to the multiple ball terminals B2-1, B4-1, and B6-1, thereby providing each of the transistor switches Q1-Q3 with current of about Io/3.

(14) When the transistor switches Q1-Q3 are turned off, the energy accumulated in the coil Lo will be liberated to the diode Do and the capacitor Co, where the current is rectified and smoothed before it is output as the output voltage Vout. The output voltage Vout may be controlled in the same manner as conventional, as described in connection with FIG. 3.

(15) This arrangement permits the shunted current to each of the parallelly connected multiple ball terminals B2-1, B4-1, and B6-1 to be reduced to or below a permissible level, and causes the Joule heat due to the contact resistance of the IC 10A with the substrate to be sufficiently reduced. Accordingly, hazardous melting of the ball terminals of the BGA structure can be avoided.

(16) Since the resultant contact resistance of the multiple ball terminals is reduced to Rb/3, the power loss by the terminals and their surroundings, is reduced. In addition, the Joule heat is distributed over the multiple ball terminals. Thus, the conversion efficiency of the power supply unit is improved accordingly.

(17) It will be appreciated that the switch circuit is little influenced by breaking of wires and/or loose contact of the pads if it happens, due to the fact that the multiple ball terminals B2-1, B4-1, and B6-1 are parallelly connected and so are the switching transistors Q1-Q3.

(18) Referring again to FIGS. 1 and 2, it is shown that each pair of nearest neighbors of the multiple ball terminals B2-1, B4-1, and B6-1 is provided therebetween at least one interposing ball terminal B3-1 and B5-1 other than the multiple ball terminals. It should be understood that there can be more than one interposing ball terminal between each pair of nearest neighbors of the multiple ball terminals B2-1, B4-1, and B6-1.

(19) These interposing ball terminals are terminals through which flows no or an extremely small amount of current (e.g. Io/10) as compared with the current (Io/3) flowing through the multiple ball terminals B2-1, B4-1, and B6-1.

(20) By placing at least one such interposing terminal in between each pair of nearest neighbors of the multiple ball terminals in the manner as described above, not only the resultant resistance of the multiple ball terminals is reduced but also the heat radiating area thereof is increased and dispersed, thereby facilitating suppression of the temperature rise in the respective multiple ball terminals.

(21) All the multiple ball terminals B2-1, B4-1, and B6-1 are located at the outermost peripheral terminal positions of the BGA configuration. Thus, external wiring leads connected to these terminals can be made thicker to reduce their electric resistances and enhance their heat-dissipative power as compared with those connected to terminals located at inner terminal positions of the BGA structure.

(22) It will be understood that, although the invention has been described with a particular reference to a BGA structure, the invention is not limited to the example as described and shown above. For example, the invention contemplates an IC having a pin gripped array (PGA) structure in which pluralities of pin-shaped terminals are arranged in a lattice configuration on one side of the IC.

(23) The invention can be applied to a wide range of switching power supply units utilizing a switching circuit, including a step-up dc-dc conversion type power supply unit as shown in FIG. 1, a step-down dc-dc conversion type power supply unit and a step-down dc-ac conversion type power supply unit. The invention can be also applied to motor drivers utilizing a switch circuit.