Reference circuit arrangement and method for generating a reference voltage

Abstract

A reference circuit arrangement comprises a branched current path connecting a first and second terminal via an intermediate terminal. The intermediate terminal is connected to a reference terminal. A current path is coupled between the first and second terminal via the reference terminal. A feedback loop is connected to the first and second terminal and designed to control, at the first and second terminal, a virtual ground potential. A reference path is connected to the feedback loop having a reference input for receiving from the feedback loop a reference current and reference output to provide a reference voltage.

Claims

1. A reference circuit arrangement comprising: a branched first current path connecting a first and second terminal via an intermediate terminal in which the intermediate terminal is connected to a reference terminal; a second current path that splits into first and second current paths connecting the first terminal and the second terminal to the reference terminal, respectively, wherein the reference terminal is connected with a ground potential, and wherein the first and second current paths form a y-connection to the ground potential; a feedback loop connected to the first and second terminal designed to control, at the first and second terminal, a virtual ground potential; and a reference path connected to the feedback loop having a reference input for receiving from the feedback loop a reference current and having a reference output to provide a reference voltage.

2. The reference circuit arrangement according to claim 1, wherein the branched first current path provides a first current having a first temperature coefficient, wherein the second current path provides a second current having a second temperature coefficient, wherein the feedback loop is designed to provide the reference current depending on the sum of the first and second current, and wherein the reference path generates the reference voltage depending on the reference current.

3. The reference circuit arrangement according to claim 1, wherein the branched current path comprises: a matched pair of a first and second resistor connecting, in series, the first and second terminal via the intermediate terminal; and an intermediate resistor matched with the pair of the first and second resistor and connecting the intermediate terminal and to the reference terminal.

4. The reference circuit arrangement according to claim 3, wherein the intermediate resistor is matched to the pair of resistors having a resistance depending on the resistance of the matched pair of resistors.

5. The reference circuit arrangement according to claim 3, wherein the resistance R.sub.n of the intermediate resistor is given by $R_n=\frac{\left(N-1\right)}{2}{R}_1=\frac{\left(N-1\right)}{2}{R}_2,$ in which N is an integer or real number equal or greater than 1, and R.sub.1, R.sub.2 denotes the resistance of the first and second resistor, respectively.

6. The reference circuit arrangement according to claim 1, wherein the second current path comprises a proportional-to-absolute-temperature resistor coupled between the first and second terminal via a first reference element and a second reference element each connected to the reference terminal.

7. The reference circuit arrangement according to claim 6, wherein a mismatched pair of diodes comprises the first reference element and second reference element.

8. The reference circuit arrangement according to claim 1, wherein the feedback loop comprises: an operational amplifier connected via its non-inverting and inverting input to the first and second terminal, respectively; a first and second transistor with their load sides being coupled to the supply terminal and connected to the non-inverting and inverting input of the operational amplifier, respectively; and the feedback output connected to the respective control side of the first and second transistor and connected to an output of the operational amplifier and the feedback output connected to the reference path.

9. The reference circuit arrangement according to claim 8, wherein the integer or real number N depends on the offset of the operational amplifier.

10. The reference circuit arrangement according to claim 1, wherein the reference path comprises a reference transistor connected, via its control side, to the feedback output, and connected, via its load side, between the supply terminal, the reference output and a reference resistor connected to the reference terminal.

11. A method for generating a reference voltage comprising: providing a first current from a branched first current path connecting a first and a second terminal via an intermediate terminal, wherein the intermediate terminal is connected to a reference terminal connected with a ground potential; providing a second current from a second current path that splits into first and second current paths connecting the first terminal and the second terminal to the reference terminal, respectively, wherein the reference terminal is connected with a ground potential, and wherein the first and second current paths form a y-connection to the ground potential; controlling, at the first and second terminal, a virtual ground potential using a feedback loop; and generating a reference voltage depending on the first and second current.

12. The method according to claim 11, further comprising: providing the first current with a first temperature coefficient; providing the second current with a second temperature coefficient; summing the first and second current using the feedback loop; and generating the reference voltage from a reference current corresponding to the sum of the first and second current.

13. The method according to claim 12, further comprising setting the first temperature coefficient and the second temperature coefficient such as to render the reference current independent of an ambient temperature.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The text below explains further details using an exemplary embodiment with references to FIG. 1.

(2) FIG. 1 shows a first embodiment of a reference circuit arrangement according to the present principle.

(3) Like reference numerals designate corresponding similar parts or elements.

DETAILED DESCRIPTION

(4) FIG. 1 shows a first embodiment of a reference circuit arrangement according to the present principle. The circuit is based on a first and second current path CP1, CP2. The first current CP1 path is branched, i.e. a first and second terminal T+, T− are connected via a first and second resistor R1, R2. The first and second resistors R1, R2 are connected via an intermediate terminal TN. This intermediate terminal TN is connected to a reference terminal GND, connected to ground, via an intermediate resistor RN. First and second resistors R1, R2 are matched such that the resistance of resistors R1, R2 determine the resistance of the intermediate resistor RN. The resistance R.sub.n of the intermediate resistor RN is given by

(5) $R_n=\frac{\left(N-1\right)}{2}{R}_1=\frac{\left(N-1\right)}{2}{R}_2,$
in which N is an integer or real number strictly greater than 1 and R.sub.1, R.sub.2 denote the resistance of the first and second resistor R1, R2, respectively.

(6) The second current path CP2 comprises a first and second diode D1, D2 as reference elements and a proportional-to-absolute-temperature (PTAT) resistor Rptat. The diodes have mismatched current densities. The first terminal T+ is connected to the reference terminal GND via the PTAT resistor Rptat and the first diode D2. The second terminal T− is connected to the reference terminal GND via the second diode D1.

(7) A feedback loop FB comprises an operational amplifier OP. A non-inverting and an inverting input +, − of the operational amplifier OP are connected to the first and a second terminal T+, T−, respectively. The first and second terminal T+, T− as well as the inverting and non-inverting inputs +, − of the operational amplifier OP are connected to a current mirror established from a first and second transistor MN1, MN2. Both first and second transistors MN1, MN2 are gate-connected and connected to an output FBout of the feedback loop FB. An output OPout of the operational amplifier OP is also connected to the output FBout of the feedback loop FB. Both first and second transistors MN1, MN2 are coupled to a supply terminal Vdd.

(8) A reference circuit REF is connected to the output FBout of the feedback loop FB. This circuit comprises a reference transistor MNRef and a reference resistor Rref. The reference transistor MNRef is gate-connected to the two transistors MN1, MN2 of the current mirror via the output FBout. Along its load side the reference transistor MNRef is connected between the supply terminal Vdd, a reference output REF and the reference resistor Rref connected to the reference terminal GND.

(9) In one embodiment transistors used with the circuit are of MOSFET type and the circuit may be integrated as an integrated circuit.

(10) The first and second current paths CP1, CP2 build up the reference voltage at the output Vref of the circuit. The first current path CP1 contributes a first current Icp1 characterized by the base-emitter voltages Vbe across the first and second diode D1, D2. The second current path CP2 contributes a second current Icp2 proportional to the absolute temperature T. First and second current Icp1, Icp2 may be adjusted such as to compensate their respective temperature dependence. In particular, the first current Icp1 has a negative temperature coefficient which accounts for the positive temperature coefficient of the second current Icp2. For example, if the thermal voltage

(11) $V_T=\frac{k_{B}T}{q},$
resulting from the second current Icp2 by means of the PTAT resistors Rptat is used it may be multiplied by a factor of 22 to render the sum of first and second current Icp1, Icp2 independent on temperature. The thermal voltage V.sub.T depends on Boltzmann's constant k.sub.B, Temperature T, and the electron's charge q. Generally, the bandgap or reference voltage Vref results from

(12) $V_{\mathrm{ref}}=V_{\mathrm{be}}+n.Math.\frac{k_{B}T}{q},$
in which n denotes a scaling factor. If n=22, as mentioned above, the generated bandgap voltage or reference voltage Vref becomes approximately 1.2 V. In order to achieve fractions of this voltage the present principle provides means to suitably scale first and second current Icp1, Icp2.

(13) The first current path CP1 provides the first current Icp1 proportional to voltage drop Vbe. In fact, due to the virtual ground of the operational amplifier OP, the voltages at first and second terminals T+, T− of both first and second resistors R1, R2 are basically the same and set to Vbe. Because of this relationship and for the sake of simplicity in the following the resistance of first and second resistors R1, R2 is set to be R.sub.vbe/N in which R.sub.vbe denotes the resistance corresponding to a voltage drop equal to Vbe at first current Icp1. N is the number introduced above.

(14) Applying Kirchhoff s current law at the intermediate terminal TN of first and second resistors R1, R2, a voltage Vc at intermediate terminal TN follows from

(15) $2.Math.\frac{V_{\mathrm{be}}-V_c}{R_{\mathrm{vbe}}\text{/}N}=\frac{V_c}{\left(N-1\right).Math.R_{\mathrm{vbe}}\text{/}2N}$
which gives

(16) $V_c=\left(N-1\right).Math.\frac{V_{\mathrm{be}}}{N}.$

(17) The above relationship allows expressing the first current Icp1 in each resistor R1, R2 as

(18) $\mathrm{Icp}1=\frac{V_{\mathrm{be}}-V_c}{R_{\mathrm{vbe}}\text{/}N}=\frac{V_{\mathrm{be}}\text{/}N}{R_{\mathrm{vbe}}\text{/}N}=\frac{V_{\mathrm{be}}}{R_{\mathrm{vbe}}},$
i.e. the first current Icp1 is proportional to diode voltage Vbe. As Vbe has a negative temperature coefficient, the first current Icp1 will share the same temperature characteristic (neglecting the drift associated with resistors R1, R2).

(19) The second current path CP2 embodies a PTAT current generation, i.e. the voltage difference between first and second diodes D1, D2 is proportional to absolute temperature T and drops across resistor Rptat to generate the second current Icp2. Given A the ratio of current densities of first and second diode D1, D2, the current flowing across PTAT resistor Rptat is given by

(20) $\mathrm{Icp}2=V_T.Math.\frac{\ln A}{R_{\mathrm{ptat}}}.$

(21) The second current Icp2 increases with temperature T (neglecting, as a reasonable assumption, the drift of the PTAT resistor Rptat).

(22) In addition, first and second diodes D1, D2 drain the same current thus ensuring the virtual ground of the operational amplifier OP is given by the diode's voltage drop Vbe. The operational amplifier OP regulates the virtual ground such that first and second terminal T+, T− stay at the voltage Vbe of first and second diode D1, D2.

(23) Feedback loop FB arranges the current I1, I2 in the first and second transistors MN1, MN2 (here PMOS array) such as to render it equal to the sum of first and second currents Icp1, Icp2. As a result, the current I1, I2 (I1=I2) in the first and second transistors MN1, MN2 is given by

(24) $I1=I2=\mathrm{Icp}1+\mathrm{Icp}2=\frac{V_{\mathrm{be}}}{R_1}+\frac{V_T\ln A}{R_{\mathrm{ptat}}}.$

(25) This current I1, I2 is mirrored by the first and second transistors MN1, MN2 into the reference path REF, i.e. into reference transistor MNref. Finally, the matched reference resistor Rref generates a reference voltage Vref whose value is given by

(26) $V_{\mathrm{ref}}=R_{\mathrm{ref}}.Math.\left(\mathrm{Icp}1+\mathrm{Icp}2\right)=V_{\mathrm{be}}.Math.\frac{R_{\mathrm{ref}}}{R_{\mathrm{vbe}}}+V_T\frac{\ln A.Math.R_{\mathrm{ref}}}{R_{\mathrm{ptat}}}.$

(27) As this relationship is based on the ratio of matched resistors, the resulting thermal drift will be independent of the temperature sensitivity of these elements and only voltage Vbe and thermal voltage V.sub.T, weighted by geometrical ratios (i.e. A and resistor ratios), determine the final thermal coefficient of the voltage reference Vref. A suitable relationship between the multiplying factors for both V.sub.T and Vbe ensures no thermal drift for reference voltage Vref. In other words, reference resistor Rref has no impact on the resulting thermal drift and, thus, can be set to any convenient resistance to provide the reference voltage Vref.

(28) Moreover, as reference resistor Rref changes in the same way the weight of both opposite thermal contributions from first and second current Icp1, Icp2, the output reference voltage can be freely set by the choice of reference resistor Rref. The final thermal coefficient for the obtained reference voltage Vref is not altered by this choice. Thus, the proposed circuit allows for generating the reference voltage Vref within a flexible range utilizing an area saving design.

(29) The implementation based on sharing first and second resistors R1, R2 terminated between first and second terminals T+, T− and reference terminal via intermediate resistor RN guarantees the same reference voltage Vref and the same power consumption even if using smaller resistors. If there was no connection from intermediate terminal TN via intermediate resistor RN to reference terminal GND first and second resistors R1, R2 would add their resistances to result in 2*Rvbe/N. The present principle reduces their value from a total of 2*Rvbe/N to [(N+3)/2N]*Rvbe/N which allows for a reduction equal to [(N+3)/4N]=(0.25+0.75/N). This saves a reasonable amount of space if integrated into an integrated circuit.

(30) The operational amplifier OP regulates the virtual ground such that the first and second terminal T+, T− stay at the diode voltage Vbe of first and second diode D1, D2. Thus, implementing a resistor array by first and second resistors R1, R2 terminated between first and second terminals T+, T− and reference terminal GND via intermediate resistor RN does not lead to a short circuit. However, the operational amplifier OP may have a certain offset. This can be accounted for by setting the resistances of first and second resistors R1, R2 to an appropriate value and fit the resistance of the intermediate resistor RN accordingly. Monte Carlo simulations are of great help to determine a reasonable trade off between offset rejection and the amount of resistance Rvbe with respect to intermediate resistor RN.