FET INCLUDING AN INGAAS CHANNEL AND METHOD OF ENHANCING PERFORMANCE OF THE FET

Abstract

According to an embodiment of the present invention, a method of manufacturing a FET device having a set BTBT leakage and a maximum V.sub.DD includes: determining an x value in In.sub.xGa.sub.1−xAs according to the BTBT leakage and the maximum V.sub.DD, and forming a channel utilizing In.sub.xGa.sub.1−xA, wherein x is not 0.53.

Claims

1. A method of manufacturing a FET device having a set BTBT leakage and a maximum V.sub.DD, the method comprising: determining an x value in In.sub.xGa.sub.1−xAs according to the BTBT leakage and the maximum V.sub.DD; and forming a channel utilizing In.sub.xGa.sub.1−xA, wherein x is not 0.53.

2. The method of claim 1, wherein the maximum V.sub.DD is 0.85 V, and x is 0.40 or less.

3. The method of claim 1, wherein the device is an SLVT, and x is at least 0.60.

4. The method of claim 1, wherein the device is a RVT device, and x is 0.40 or less.

5. A method of manufacturing a FET device having a set BTBT leakage and a maximum V.sub.DD, the method comprising: determining a value of x in In.sub.xGa.sub.1−xAs according to the BTBT leakage and the maximum V.sub.DD; forming a first channel utilizing In.sub.xGa.sub.1−xA; determining BTBT leakage for an LVT and/or SLVT device; determining a value of y in In.sub.yGa.sub.1−yAs according to the BTBT leakage for the LVT and/or SLVT device; and forming a second channel utilizing In.sub.yGa.sub.1−yAs, wherein y is greater than x.

6. The method of claim 5, wherein y≧x+0.1.

7. A method of manufacturing a FET device comprising a RVT device, an LVT device and an SLVT device, the method comprising: determining an x value in In.sub.xGa.sub.1−xAs for a RVT; determining a y value in In.sub.yGa.sub.1−yAs for an LVT; determining a z value in In.sub.zGa.sub.1−zAs for an SLVT; and forming a channel comprising In.sub.xGa.sub.1−xAs for the RVT device, a channel comprising In.sub.yGa.sub.1−yAs for the LVT device and a channel comprising In.sub.zGa.sub.1−zAs for the SLVT device.

8. The method of claim 7, wherein x<y≦z.

9. The method of claim 8, further comprising forming a gate electrode utilizing a same work function material for each of the SLVT, LVT and RVT.

10. A FET device, comprising a gate electrode, an In.sub.xGa.sub.1−xAs channel, and a buffer layer between the gate electrode and the channel, wherein x is not 0.53, BTBT leakage is 0.1 nA/μm or lower, and the FET device is configured to operate with a maximum V.sub.DD of at least 0.7 V.

11. The FET device of claim 10, wherein x is about 0.3-0.4, and the FET device is configured to operate with the maximum V.sub.DD of at least 0.8 V.

12. The FET device of claim 10, wherein x is about 0.2-0.3, and the FET device is configured to operate with the maximum V.sub.DD of at least 0.8 V.

13. The FET device of claim 10, wherein the FET further comprises a buffer layer between the gate electrode and the channel, the buffer layer comprising InGaP and/or InAlAs.

14. The FET device of claim 10, further comprising a second FET comprising a second channel comprising In.sub.yGa.sub.1−yAs, wherein y is greater than x, and the second FET has a BTBT leakage of 1 nA/μm or lower.

15. The FET of claim 14, further comprising a third FET comprising a third channel comprising In.sub.zGa.sub.1−zAs, wherein z is greater than or equal to y, and the third FET has a BTBT leakage of 10 nA/μm or lower.

16. The FET of claim 15, wherein x<y<z.

17. The FET of claim 15, wherein 0.2≦x<y<z≦0.8

18. A FET device, comprising an SLVT, an LVT and a RVT, each of the SLVT, LVT and RVT comprises a gate electrode and an InGaAs channel, wherein the gate electrode for each of the SLVT, LVT and RVT comprises substantially a same work function material and same thickness, the InGaAs channel for RVT is represented by In.sub.xGa.sub.1−xAs, the InGaAs channel for LVT is represented by In.sub.yGa.sub.1−yAs, and the InGaAs channel for SLVT is represented by In.sub.zGa.sub.1−zAs, wherein x is not the same as y or z.

19. The FET device of claim 18, wherein z=y+0.1=x+0.2.

20. The FET device of claim 18, further comprising a buffer layer between the gate electrode and the channel, wherein the buffer layer for SLVT and LVT devices comprise InP, and the buffer for RVT device comprises InGaP and/or InAlAs.

21. The FET device of claim 18, wherein the FET device is horizontal nanosheet FET, and vertical spacing between nanosheets is about 15 nm or less.

22. The FET device of claim 21, wherein a width of the horizontal nanosheets is about 40 nm or less and the thickness of the horizontal nanosheets is about 10 nm or less.

23. The FET device of claim 18, wherein the FET device is fin FET, hNS FET, vertical FET, or vNS FET.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] These and other features and advantages of the present invention will be better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings. It is understood that selected structures and features have not been shown in certain drawings so as to provide better viewing of the remaining structures and features.

[0034] FIG. 1 is a schematic illustration of a cross sectional view of a hNS FET.

[0035] FIG. 2 is a schematic illustration of a vNS FET.

[0036] FIG. 3 is a graph illustrating the effect of channel thickness and gate length on BTBT leakage.

[0037] FIG. 4 is a graph showing the effect of In fraction on the bandgap.

[0038] FIG. 5 is a graph showing the effect of In content on BTBT at various gate lengths.

[0039] FIG. 6 is a graph showing the effect of In content on relative mobility.

[0040] FIG. 7 is a graph showing the effect of In content on relative injection velocity.

[0041] FIG. 8 is a graph illustrating the effect of In content in InGaAs channel on I eff at various gate lengths.

[0042] FIG. 9 is a graph illustrating the effect of In content in InGaAs channel on total parasitic leakage at various gate lengths.

[0043] FIG. 10 is a schematic illustration of a FET manufactured according to an embodiment of the present disclosure.

[0044] FIG. 11 is a schematic illustration of a FET manufactured according to an embodiment of the present disclosure.

[0045] FIG. 12 is a schematic illustration of a FET manufactured according to an embodiment of the present disclosure.

[0046] FIG. 13 is a schematic illustration of a hNS multi-Vt device.

[0047] FIG. 14 shows the conductive band of various materials.

[0048] FIG. 15 is a schematic illustration of a FET manufactured according to an embodiment of the present disclosure.

[0049] FIG. 16 shows the composition required for a given Vt flavor.

[0050] FIG. 17 is a graph illustrating the effect of nanosheet spacing in InGaAs channel on gate capacitance at various gate lengths.

[0051] FIG. 18 is a graph illustrating the effect of nanosheet spacing in InGaAs channel on gate parasitic capacitance.

[0052] FIG. 19 is a graph illustrating the effect of sheet thickness in InGaAs channel on BTBT leakage.

[0053] FIG. 20 is a graph illustrating the effect of sheet thickness in InGaAs channel on I.sub.eff.

DETAILED DESCRIPTION

[0054] Spatially relative terms, such as “below,” “beneath,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. Embodiments described herein will be described referring to plan views and/or cross-sectional views by way of ideal schematic views of the invention. Accordingly, the example views may be modified depending on manufacturing technologies and/or tolerances. Therefore, the embodiments of the invention are not limited to those shown in the views, but include modifications in configuration formed on the basis of manufacturing processes. Therefore, regions shown in the drawings have schematic properties, and shapes of regions shown in the drawings are examples of specific shapes of regions of elements and do not limit aspects of the invention.

[0055] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0056] Expressions such as “at least one of” or “at least one selected from” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Further, the use of “may” when describing embodiments of the present invention refers to “one or more embodiments of the present invention.” Also, the term “exemplary” is intended to refer to an example or illustration. It will be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on,” “directly connected to”, “directly coupled to”, or “immediately adjacent to” another element or layer, there are no intervening elements or layers present.

[0057] As used herein, the terms “substantially,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. Also, any numerical range recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of “1.0 to 10.0” is intended to include all subranges between (and including) the recited minimum value of 1.0 and the recited maximum value of 10.0, that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein. Accordingly, Applicant reserves the right to amend this specification, including the claims, to expressly recite any sub-range subsumed within the ranges expressly recited herein.

[0058] According to its architecture, FETs may be categorized as fin FET, hNS FET, vertical FET, vNS FET, etc. By way of example, FIG. 1 is a schematic illustration of a cross sectional view of a horizontal nanosheet (hNS) FET, and FIG. 2 is a schematic illustration of a vNS FET.

[0059] Referring to FIG. 1, the FET includes a plurality of channels 110 stacking vertically over one another, a plurality of gate stacks 120 surrounding each of the channels 110. Each gate stack 120 includes a gate electrode 122 surrounding the channel 110 in a gate-all-around structure, a high-K dielectric 124 in between the gate electrode 122 and the channel 110, and an internal spacer 130 between the gate electrode 122 and the source and drain electrodes 140. The FET also includes a substrate 150 and a pair of contact pads 160.

[0060] Referring to FIG. 2, the FET includes a bulk source electrode 340, a bulk drain electrode 350, and a channel 310 therebetween. The FET further includes a buffer layer 360 surrounding the channel region, a spacer 330 between the bulk source and drain electrodes and the gate electrode 322, and a high-K dielectric 324 in between the gate electrode 322 and the channel 310.

[0061] Here, the channel 110 and 310 may be formed of InGaAs. The high-K dielectric 124 and 324 may be formed of a suitable material, such as Al.sub.2O.sub.3 and/or Hf.sub.2O.sub.3. The spacers 130 and 330 may be formed of a lower K dielectric such as a metal oxide or a nitride. In one embodiment, the spacers 130 and 330 may be formed of SiO.sub.2. The buffer layer 360 may be formed of indium phosphite (InP). The source and drain electrodes 140, 340 and 350 may be formed of any suitable materials. In one embodiment, the source and drain electrodes are formed of substantially the same material as the channel, such as InGaAs, but with higher In fraction than the channel. Or, source and drain electrodes may be highly doped with a suitable dopant to provide low contact resistance. The gate electrode 122 and 322 may be formed of a suitable metal material, such as TiN. The substrate may be formed of SiO.sub.2 for an OI version of the process, or wide bandgap semiconductors such as InAlAs.

[0062] While three horizontal gates are illustrated in FIG. 1 and one vertical gate is illustrated in FIG. 2, embodiments of the present invention are not limited thereto.

[0063] According to an embodiment of the present disclosure, a method of manufacturing a FET device having a set BTBT leakage and a maximum V.sub.DD includes determining the value of x in In.sub.xGa.sub.1−xAs according to the BTBT leakage and the maximum V.sub.DD, and forming a channel utilizing In.sub.xGa.sub.1−xA.

[0064] The BTBT of a FET device including an InGaAs channel is influenced by a number of factors, for example, V.sub.DD, the In content in InGaAs, etc. When the V.sub.DD and BTBT of a device are determined, the value of x in In.sub.xGa.sub.1−xAs can be enhanced to deliver a device with the desired BTBT at the maximum V.sub.DD. Here, the optimization includes determining a range for the In content that satisfies the BTBT requirement at the maximum V.sub.DD, and choosing an In content from the range that also provides satisfactory injection velocity.

[0065] The BTBT values for a RVT device may be about 0.1 nA/μm, for an LVT device may be about 1 nA/μm, and for an SLVT device may be about 10 nA/μm. That is, the BTBT criterion is the lowest for a RVT device and highest for an SLVT device.

[0066] In a related art FET utilizing In.sub.0.53Ga.sub.0.47As, because the BTBT for a RVT device is at about 0.1 nA/μm for Weff, and because BTBT is exponentially sensitive to V.sub.DD, the V.sub.DD for such a related art device is limited to be about 0.7 V or lower. However, to be utilized for standard SOC applications, the designs at present technology nodes generally require maximum operating voltages to be in the 0.9-1.4 V range. Even designs at the cutting edge 5 nm technology node will generally require maximum operating voltages to be at least in the 0.85-0.9 V range (a V.sub.nom of 0.65-0.7V with a 200 mV overdrive for f.sub.max). As such, FETs with In.sub.0.53Ga.sub.0.47As channels are not suitable for standard SOC applications.

[0067] BTBT leakage is also affected by the gate length and the channel thickness. FIG. 3 is a graph illustrating the effect of channel thickness and gate length on BTBT leakage. In FIG. 3, I.sub.off indicates the thermionic current and IBTBT is the BTBT leakage. For a RVT device, both I.sub.off and IBTBT should be limited to be under 0.1 nA, as indicated in the shaded area in FIG. 3. As shown in FIG. 3, BTBT leakage has a strong dependence on the gate length (Lg).

[0068] In fact, at V.sub.DD of 0.75 V, the minimum gate length for a FET with a In.sub.0.53Ga.sub.0.47As channel is about 12.5 nm. On the other hand, due to the effect of channel thickness on BTBT, at V.sub.DD of 0.75 V, the maximum channel thickness is less than 5 nm. Such limitations on the minimum gate length and maximum channel thickness present great challenges to the manufacturing process. Also, it is impossible for such devices to support +200 mV V.sub.DD overdrive. Therefore, the related art FET utilizing In.sub.0.53Ga.sub.0.47As is not suitable for the standard SOC applications, such as mobile SOC applications, and not a suitable replacement for a silicon (Si) device, which has been utilized for such applications.

[0069] When a FET is manufactured according to embodiments of the present invention, because the In content in the InGaAs channel is enhanced based on the requirements on BTBT and the maximum V.sub.DD, it can satisfy both the low BTBT and high V.sub.DD requirement and therefore, be suitable for the standard SOC applications.

[0070] The In content impacts a number of performance factors in a FET. For example, including a larger Indium (In) fraction will lead to a smaller bandgap and higher mobility/injection velocity. On the other hand, including a smaller In fraction may lead to an increased bandgap and correspondingly (exponentially) smaller BTBT leakage current. That is, there is a tradeoff between mobility and BTBT leakage as a function of the In fraction.

[0071] The bandgap sets the tunneling barrier, and the bandgap is highly sensitive to the In fraction. That is, reducing the In fraction will increase the tunneling barrier and reduce the BTBT leakage accordingly. FIG. 4 is a graph showing the effect of In fraction on the bandgap at various gate lengths. As shown in FIG. 4, when In content is 0.53 as in the related art InGaAs devices, the bandgap is about 0.8 eV. However, when In content is about 0.3, the bandgap is close to that of Si at about 1.1 eV. FIG. 5 is a graph showing the effect of In content on BTBT at various gate lengths. As shown in FIG. 5, at 40% In, V.sub.DD up to 0.85 V can be supported in a RVT device.

[0072] Reducing the content of In may also lead to lower mobility and injection velocity. FIG. 6 is a graph showing the effect of In content on relative mobility at various gate lengths. As shown in FIG. 6, the relative mobility increases when the In content increases. FIG. 7 is a graph showing the effect of In content on relative injection velocity at channel thickness of 5 nm and V.sub.DD of 0.8 V. As shown in FIG. 7, the relative injection velocity increases when the In content increases. However, when reducing the In content from 53% to 35%, as shown in FIG. 7, the relative injection velocity reduces by less than 10%, which is still about 3 times that of Si.

[0073] Here, as shown in FIG. 7, when the In content is lower than 30%, there is a relatively greater loss in relative injection velocity when the In content is further reduced. This phenomenon is mostly due to the electron spillover from the Gamma valley to the L valley. According to an embodiment of the present disclosure, a tensile strain-inducing buffer layer may be utilized to suppress the electron spillover from the Gamma valley to the L valley. For example, the tensile strain-inducing buffer layer may include InGAP and/or InAlAs and may be located on the channel. Accordingly, the In content may be about 20% to about 30% and still have an acceptable relative injection velocity.

[0074] FIG. 8 is a graph illustrating the effect of In content in InGaAs channel on the effective drive current I.sub.eff at various gate lengths. Referring to FIG. 8, it is noted that InGaAs channels, even at an In content of 40%, still have an I.sub.eff comparable to that of strained Si for each of the RVT and SLVT devices. Also, the higher the In content, the greater the I.sub.eff for both RVT and SLVT devices.

[0075] FIG. 9 is a graph illustrating the effect of In content in InGaAs channel on total parasitic leakage (BTBT with Parasitic bipolar effect) at various gate lengths and a V.sub.DD of 0.85 V. Referring to FIG. 9, it is noted that in order to be utilized in the RVT region, In content of 40% or lower at a gate length of 25 nm or greater is needed. For example, an In content of 40% and a gate length of 30 nm may be utilized to make a RVT device. Here, for a RVT device, the In content is chosen for the best power, performance and area at low V.sub.DD, while supporting V.sub.DD overdrive.

[0076] As shown in FIG. 9, a device with In content of 50% does not appear to provide satisfactory total parasitic leakage within the gate length of 15 nm to 35 nm, and the leakage gets higher with greater In content. It is clear that the related art InGaAs channel with an In content of 53% would not be able to have the desired leakage performance.

[0077] On the other hand, if utilized in the SLVT region, In content of 60% at a gate length of about 20 is satisfactory. Therefore, for an SLVT device, an In content of 60% or greater may be utilized. That is, a greater In content may be utilized in an SLVT device relative to a RVT device, as an SLVT device is less prone to BTBT leakage. From FIG. 8, it can be seen that such an SLVT has an I.sub.eff significantly above that of a strained Si device.

[0078] Further, from FIG. 9, it can be observed that an InGaAs channel with about 40% In and about 30 nm gate length may be utilized for all Vt flavors, i.e., RVT, LVT and SLVT. That is, a single In faction may be utilized to have the best tradeoff in mobility, leakage and maximum V.sub.DD.

[0079] In more detail, when BTBT is lower as in a RVT (e.g., 0.1 nA/μm), the amount of In may be lower than 0.5, for example, 0.4 or less in order to support a V.sub.DD of 0.85 V or greater. When BTBT is higher as in an SLVT (e.g., 10 nA/μm), the amount of In may be higher than 0.53, for example, 0.6 or greater.

[0080] FIG. 10 is a schematic illustration of a FET manufactured according to an embodiment of the present disclosure. Referring to FIG. 10, a FET device includes a gate electrode 722, an In.sub.xGa.sub.1−xAs channel 710, wherein x is not 0.53, BTBT leakage is 0.1 nA/μm or lower, and the FET device is configured to operate with a maximum V.sub.DD of 0.75 V or greater. The FET further includes source and drain electrodes 740, high-K dielectric 724, and spacer 730.

[0081] In one embodiment, x may be about 0.3-0.4, and the FET device is configured to operate with a maximum V.sub.DD of 0.8 V or greater.

[0082] In one embodiment, x may be about 0.2-0.3, and the FET device is configured to operate with a maximum V.sub.DD is 0.8 V or greater.

[0083] FIG. 11 is a schematic illustration of a FET manufactured according to an embodiment of the present disclosure. Referring to FIG. 11, The FET device may further include a buffer layer 880 between the gate electrode and the channel, and the buffer layer may include InGaP and/or InAlAs.

[0084] The process of manufacturing the FET according to embodiments of the present disclosure may be any suitable process, such as the one disclosed in CA 1196111 A1, US 20060024874 and US 20080296622, the entire contents of all of which are incorporated herein by reference.

[0085] According to an embodiment of the present disclosure, a method of manufacturing a

[0086] FET device having a set BTBT leakage and a maximum V.sub.DD for a RVT device includes: determining the value of x in In.sub.xGa.sub.1−xAs according to the BTBT leakage and the maximum V.sub.DD, forming a first channel utilizing In.sub.xGa.sub.1−xA; determining BTBT leakage for an LVT and/or SLVT device; determining the value of y in In.sub.yGa.sub.1−yAs according to the BTBT leakage for the LVT and/or SLVT device, and forming a second channel utilizing In.sub.yGa.sub.1−yAs, wherein y is greater than x. For example, y may be the sum of x and 0.1, or greater. Here, the combination of a RVT with relatively lower In content to satisfy the BTBT and the maximum V.sub.DD requirements, and an LVT and/or SLVT with relatively higher In content provides better DC performance than just a single RVT device.

[0087] FIG. 12 is a schematic illustration of a FET manufactured according to the present embodiment. Referring to FIG. 12, a FET includes a first channel 511 that is formed of In.sub.xGa.sub.1−xA, and a second channel 512 that is formed of In.sub.yGa.sub.1−yAs. The FET further includes gate electrodes 522 surrounding the first and second channels 511 and 512, source and drain electrodes 540, high-K dielectric 524, spacer 530 and a substrate 550. Here, the In content in the first channel of In.sub.xGa.sub.1−xAs is selected to meet the BTBT leakage and the maximum V.sub.DD while the In content in the second channel of In.sub.yGa.sub.1−yAs is greater than that of the first channel to provide better DC performance. For example, x may be 0.4 and y may be 0.6; or x may be 0.3 and y may be 0.6.

[0088] Referring to FIG. 15, the FET device may further include a third FET including a third channel comprising In.sub.zGa.sub.1−zAs, wherein z is greater than or equal to y, and the third FET has a BTBT leakage of 10 nA/μm or lower.

[0089] In one embodiment, x<y<z.

[0090] In one embodiment, 0.2≦x<y≦z≦0.8.

[0091] According to another embodiment of the present disclosure, a method of manufacturing a FET device that includes a RVT device, an LVT device and an SLVT device includes: determining an x value in In.sub.xGa.sub.1−xAs for the RVT device; determining a y value in In.sub.yGa.sub.1−yAs for the LVT device; and determining a z value in In.sub.zGa.sub.1−zAs for the SLVT device, and forming a channel comprising In.sub.xGa.sub.1−xAs for the RVT device, a channel comprising In.sub.yGa.sub.1−yAs for the LVT device and a channel comprising In.sub.zGa.sub.1−zAs for the SLVT device. In one embodiment, x<y≦z. Here, the combination of a RVT with relatively lower In content to satisfy the BTBT and the maximum V.sub.DD requirements, and an LVT and an SLVT with relatively higher In content provides better DC performance than just a single RVT device.

[0092] The method may further include forming a gate electrode utilizing a same work function material for each of the SLVT, LVT and RVT devices. That is, a single work function material and thickness may be used for forming the gate electrode for each of the SLVT, LVT and RVT devices.

[0093] The related art methods of making a device with multiple different Vt values (i.e., Vt modulation) include selecting a metal material for forming the gate electrode, and then varying the thickness of the gate electrode to achieve a desired work function (WF) and therefore, the desired Vt values. However, for some of the Vt values, the gate thickness may need to be relatively high, for example, some of the gate electrodes may have a thickness of about 50 nm. Spacing between adjacent channels is accordingly increased due to the increased thickness of the gate electrode.

[0094] However, a device manufactured according to embodiments of the present disclosure may keep a same desired thickness for the gate electrode throughout all the Vt values. FIG. 13 is a schematic illustration of a hNS multi-Vt device. Referring to FIG. 13, the multi-Vt device includes four channels 811, 812, 813 and 814. As shown in the insert in more detail, each channel has a thickness Tsheet and is surrounded by a gate electrode 822. An internal spacer 830 is between the gate electrode 822 and its neighboring source or drain electrodes. The thickness of the gate electrode (VSP) is the same for each of the Vt devices. The length of the gate electrode is represented by Lg. By adjusting the In content, the conductive band (CB) energy of each channel is modulated, and therefore, enables tuning of the Vt according to the In content. That is, each of the channels 811-814 includes InGaAs but with a different In content to provide for four different Vt flavors.

[0095] FIG. 14 shows the conductive band of various materials. Referring to FIG. 14, by adjusting the content of In in InGaAs, the conductive band may be adjusted to have the suitable work function for the desired threshold voltage Vt.

[0096] For example, the In composition for an SLVT device may be first determined according to the BTBT criterion. The In content for an LVT region may be determined to increase the Vt by about 70 mV relative to the SLVT. Then the In content for a RVT region may be determined to increase the Vt by about 70 mV relative to the LVT.

[0097] FIG. 15 is a schematic illustrate of a FET manufactured according to the present embodiment. Referring to FIG. 15, a FET includes a first channel 611 that is formed of In.sub.xGa.sub.1−xA, a second channel 612 that is formed of In.sub.yGa.sub.1−yAs, and a third channel 613 formed of In.sub.zGa.sub.1−zAs. The FET further includes gate electrodes 622 surrounding the first and second channels 611 and 612, source and drain electrodes 640, high-K dielectric 624, spacer 630 and a substrate 650. Here, the In content in the first channel of In.sub.xGa.sub.1−xAs is selected to meet the BTBT leakage and the maximum V.sub.DD while the In content in the second and third channels is greater than that of the first channel to provide better DC performance. For example, x may be 0.4, and y and z may be 0.6; or x may be 0.3 and y and z may be 0.6.

[0098] FIG. 16 shows the composition required for a given Vt flavor. Referring to FIG. 16, for a given sheet thickness and a given gate length, an SLVT device may have a higher In content than a RVT device.

[0099] In one embodiment, the amount of In for an LVT region may be greater than that in a RVT region, and the amount of In for an SLVT region may be greater than that in an LVT region. For example, the amount of In for an LVT region may be that in a RVT region plus 0.1, and the amount of In for an SLVT region may be that in a RVT region plus 0.2.

[0100] FIG. 19 is a graph illustrating the effect of sheet thickness in InGaAs channel on BTBT leakage. FIG. 20 is a graph illustrating the effect of sheet thickness in InGaAs channel on I.sub.eff. As shown in FIGS. 19 and 20, different In content may be used for the RVT device (e.g., 0.42) and for the SLVT device (e.g., 0.5). For each device, the channel thickness may be enhanced (e.g., optimized) separately for each Vt flavor. Therefore, thinner sheet or fin spacing may be realized.

[0101] A thinner metal gate enables tighter nanosheet spacing (for example, vertically or horizontally) than the related art multiple work function metals. Further, smaller nanosheet spacing also reduces the parasitic capacitance, as shown in FIG. 17. FIG. 17 is a graph illustrating the effect of nanosheet spacing in InGaAs channel on gate capacitance at various gate lengths. FIG. 18 is a graph illustrating the effect of nanosheet spacing in InGaAs channel on gate parasitic capacitance. As shown in FIGS. 17 and 18, at smaller spacing, the parasitic capacitance (the intercept of the Cg vs Lg curve with the Cg axis) is smaller, and the gate capacitance is also smaller. For example, when the spacing is reduced from 15 nm to 6 nm, a reduction of about 25% in the gate capacitance may be realized. In one embodiment, the spacing may be about 15 nm. In another embodiment, the spacing may be about 6-9 nm. According to an embodiment, the In content varies from about 20% to about 80% across the range of Vts on a single chip.

[0102] According to an embodiment, a FET device includes an SLVT device, an LVT device and a RVT device, each of the SLVT, LVT and RVT devices includes a gate electrode and an InGaAs channel, wherein the gate electrode for each of the SLVT, LVT and RVT devices includes substantially the same work function material and same thickness, the InGaAs channel for the RVT device is represented by In.sub.xGa.sub.1−xAs, the InGaAs channel for the LVT device is represented by In.sub.yGa.sub.1−yAs, and the InGaAs channel for the SLVT device is represented by In.sub.zGa.sub.1−zAs, wherein x is not the same as y or z.

[0103] In one embodiment, z=y+0.1=x+0.2.

[0104] The FET device may further include a buffer layer between the gate electrode and the channel, wherein the buffer layer for the SLVT and LVT devices includes InP, and the buffer layer for the RVT device includes InGaP and/or InAlAs.

[0105] The FET device may be a horizontal nanosheet FET, and a vertical spacing between neighboring nanosheets is about 15 nm or less.

[0106] The width of the horizontal nanosheets may be about 40 nm or less and the thickness of the horizontal nanosheets may be about 10 nm or less.

[0107] The FET device may be a fin FET, hNS FET, vertical FET, or vNS FET.

[0108] In one embodiment, the FET is an nFET.

[0109] In view of the foregoing, embodiments of the present invention provide a method of enhancing the performance of a FET including an InGaAs channel, wherein the In fraction is enhanced (e.g., optimized) to meet the BTBT leakage criterion and the maximum V.sub.DD.

[0110] In view of the foregoing, embodiments of the present invention provide FETs having InGaAs channels, wherein the In fraction is enhanced to meet the BTBT leakage criterion and the maximum V.sub.DD.

[0111] While one or more embodiments of the present invention have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims, and equivalents thereof.