Low-dropout regulator

Abstract

A low-dropout voltage regulator comprises an output terminal for providing an output voltage regulated as a function of a reference voltage, and for providing an output current, and additionally comprising an output current limiting unit. The current limiting unit comprises a replicator for replicating the output current to provide a mirror current of the output current, a comparator circuit for comparing the mirror current with a reference current, and a feedback circuit for supplying feedback to the regulator in order to limit the output current when the mirror current is greater than the reference current. The mirror current is injected into the output terminal.

Claims

1. A low-dropout voltage regulator comprising: an output terminal to provide an output voltage regulated as a function of a reference voltage and to provide an output current; and an output current limiting unit comprising: an output current replication module to provide a mirror current of the output current, a comparison module to compare the mirror current with a reference current, the comparison module comprising: a first input coupled with a first electric potential which is a function of the output voltage and the intensity of the mirror current, and a second input coupled with a second electric potential which is a function of the output voltage and the intensity of the reference current; and a feedback module to limit the output current when the mirror current is greater than the reference current; wherein both the mirror current and the reference current are injected into the output terminal.

2. The regulator according to claim 1, wherein: the output terminal is the drain of a first PMOS power transistor, the output current replication module comprises a second PMOS transistor paired with the first transistor, the gate of the first transistor being connected to the gate of the second transistor and the source of the first transistor being connected to the source of the second transistor, the output of the comparator is coupled to the gates of the first and second transistors.

3. The regulator according to claim 2, further comprising: a first resistor arranged between the output terminal and the first input of the comparator, and a second resistor arranged between the output terminal and the second input of the comparator.

4. A device comprising: a low-dropout voltage regulator comprising: an output terminal to provide an output voltage regulated as a function of a reference voltage and to provide an output current; and an output current limiting unit comprising: an output current replication module to provide a mirror current of the output current, a comparison module to compare the mirror current with a reference current, the comparison module comprising: a first input coupled with a first electric potential which is a function of the output voltage and the intensity of the mirror current, and a second input coupled with a second electric potential which is a function of the output voltage and the intensity of the reference current, and a feedback module on the regulator to limit the output current when the mirror current is greater than the reference current; wherein both the mirror current and the reference current are injected into the output terminal.

5. A method for controlling a low-dropout voltage regulator comprising an output terminal for providing an output voltage regulated as a function of a reference voltage and for providing an output current, and an output current limiting unit, the method comprising: replicating the output current to provide a mirror current of the output current, comparing the mirror current with a reference current by: coupling a first input a comparison module with a first electric potential which is a function of the output voltage and the intensity of the mirror current, and coupling a second input of the comparison module with a second electric potential which is a function of the output voltage and the intensity of the reference current, providing feedback to the regulator to limit the output current when the mirror current is greater than the reference current, and injecting both the mirror current and the reference current into the output terminal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features and advantages of the invention will become apparent from the following description. This description is purely illustrative and is to be read in light of the attached drawings, in which, in addition to FIGS. 1 and 2:

(2) FIG. 3 illustrates an LDO regulator comprising a current-limiting loop according to an embodiment of the invention;

(3) FIG. 4 illustrates the gain in accuracy provided by a circuit according to an embodiment of the invention;

(4) FIG. 5 illustrates an embodiment of the comparators COMP31 and COMP32 of FIG. 3

(5) FIG. 6 is a flow chart of the steps for implementing the method according to an embodiment of the invention,

(6) FIG. 7 is a device comprising a regulator according to an embodiment of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS

(7) A circuit according to an embodiment of the invention is described below, first with reference to FIG. 3.

(8) The circuit is represented in this figure, in which a regulating loop REGUL3 and a current-limiting loop LIMIT3 can be recognized.

(9) The regulating loop comprises two resistors in series R31 and R32 connecting the output voltage Vout to the ground. The node between the resistors R31 and R32 is coupled to the inverting input of a comparator COMP33. The non-inverting input of this comparator is coupled with a reference voltage source Vref

(10) Thus the output voltage from the comparator COMP33 is a linear combination of the output voltage Vout and the reference voltage Vref. This is equivalent to comparing the output voltage to a reference voltage Vref′ whose value is a function of the reference voltage Vref and the value of the resistors R31 and R32. The output voltage of the comparator COMP33 can be written as:

(11) $V_{s33}=G_{33}.Math.\frac{R31}{R31+R32}.Math.\left(V_{\mathrm{OUT}}-\frac{R31+R32}{R31}.Math.V_{\mathrm{ref}}\right),$
where G.sub.33 is the gain of the comparator COMP33.

(12) The output voltage of the comparator COMP33 is coupled to the gate of a NMOS transistor T32. The drain of this transistor T32 is connected to the ground and the source of this transistor is connected to the gates of transistors T30 and T31 described below.

(13) The current-limiting loop comprises a PMOS power transistor T30, and a PMOS copy transistor T31.

(14) The transistors T30 and T31 are paired on silicon and arranged such that the gate of T30 is connected to the gate of T31, and the source of T30 is connected to the source of T31.

(15) Thus the drain current I.sub.mirror of the transistor T31 is proportional to the drain current of the transistor T30. In order to simplify the presentation, the drain current of the transistor T30 is considered to be equal to the output current I.sub.out. In fact, in practice, the other currents at the output node of the circuit are negligible compared to I.sub.out.

(16) The current I.sub.mirror is not lost because it is injected into the output via a resistor R33.

(17) In addition, the reference current Iref used for the limiting loop is also injected into the output via a resistor R34.

(18) The limiting loop comprises two comparators COMP31 and COMP32, associated such that the output of COMP31 is connected to the output of COMP32, the inverting input of COMP31 is connected to the inverting input of COMP32, and the non-inverting input of COMP31 is connected to the non-inverting input of COMP32.

(19) Unlike the comparator COMP1 of FIG. 1, the comparators COMP31 and COMP32 of FIG. 3 do not use the ground as a reference. Their reference is the output voltage. As this voltage is variable and not always close to 0 (varying for example between 0 Volts and 3.3 Volts), a larger working range must be allowed for, which is what the association of the two comparators COMP31 and COMP32 does.

(20) They are additionally arranged such that when the value of the voltage Va between the ground and the inverting input of the comparators is less than half of the supply voltage Vdd it is the comparator COMP31 which operates, and when this voltage Va is between Vdd/2 and Vdd, it is the comparator COMP32 which operates.

(21) As will be clear to a person skilled in the art, the association of these two comparators is equivalent to one comparator.

(22) The outputs from comparators COMP31 and COMP32 are coupled to the gates of transistors T30 and T31 and to a resistor R35 for switching between the regulating and current-limiting loops. The resistor R35 connects the output of the comparators COMP31 and COMP32 to the supply voltage potential Vdd.

(23) In what follows, simplified calculations are used to illustrate the savings in current and the gain in accuracy realized by the circuit described above.

(24) The following notations are used:

(25) Vb: drain potential of the transistor T31

(26) W.sub.31: Width of the gate of the transistor T31

(27) W.sub.30: Width of the gate of the transistor T30

(28) G.sub.mp30: gain of the transistor T30

(29) G31: gain of the comparator COMP31

(30) G32: gain of the comparator COMP32.

(31) The transistors T30 and T31 have the same physical characteristics. In particular, they have the same gate length. Using the linear model for transistors, one obtains:

(32) $I_{\mathrm{mirror}}=\frac{W_{31}}{W_{30}}.Math.I_{\mathrm{out}}.$

(33) In addition:

(34) $V_a=V_{\mathrm{out}}+R_{34}.Math.I_{\mathrm{ref}},\mathrm{and}$$\mathrm{Vb}=V_{\mathrm{out}}+R_{33}.Math.I_{\mathrm{mirror}},\mathrm{or}\mathrm{Vb}=V_{\mathrm{out}}+R_{33}.Math.\frac{W_{31}}{W_{30}}.Math.I_{\mathrm{out}}.$

(35) When

(36) $\frac{V_{\mathrm{dd}}}{2}\le V_a\le V_{\mathrm{dd}},$
the comparator COMP31 operates and one obtains:

(37) 0$\mathrm{Vs}=G_{31}.Math.\left(V_b-V_a\right)$$V_s=-\frac{I_{\mathrm{OUT}}}{G_{mp30}}.$

(38) Which leads to:

(39) $G_{31}.Math.\left(R_2\frac{W_{31}}{W_{30}}.Math.I_{\mathrm{OUT}}-R_{34}.Math.I_{\mathrm{ref}}\right)=-\frac{I_{\mathrm{OUT}}}{G_{mp30}}.$

(40) After simplification one obtains:

(41) $I_{\mathrm{out}}=\frac{R_{33}.Math.G_{31}.Math.G_{mp30}}{1+R_{33}.Math.G_{31}.Math.G_{mp30}}.Math.\frac{W_{30}}{W_{31}}.Math.\frac{R_{34}}{R_{33}}.Math.I_{\mathrm{ref}}.$

(42) As the open-loop gain R.sub.33.Math.G.sub.31.Math.G.sub.mp30 is very high, one arrives at the following approximation:

(43) $I_{\mathrm{out}}=\frac{W_{30}}{W_{31}}.Math.\frac{R_{34}}{R_{33}}.Math.I_{\mathrm{ref}}.$

(44) When

(45) $0\le V_a\le \frac{V_{\mathrm{dd}}}{2},$
the comparator COMP32 operates, and with the same type of reasoning as for the above case, the same result is reached.

(46) One can see that there is a set of three parameters W31, R33, R34 for setting the output current.

(47) In the current-limiting loop LIMIT3, the current consumed corresponds to the current consumed by the comparators COMP31 and COMP32. If these currents are considered to be equal, and comparable to the current consumed by the comparator COMP1 of FIG. 1, a savings of current corresponding to

(48) $I_{\mathrm{ref}}-I_{\mathrm{ad}}+\frac{W_{10}}{W_{11}}{I}_0$
is observed. Applying the numbers from Table 1, a consumption of 8 μA is found. This current consumption is to be compared with the 67.5 μA of the circuit in FIG. 1. A clear savings in current consumption is found.

(49) In addition, in this solution, the current consumed no longer depends on the width of the transistors T30 and T31 (only the currents of the comparators are consumed). It is therefore possible to increase the surface area of the gate of the transistor T31 which improves its pairing with the transistor T30, and which therefore improves the accuracy of the current loop. In fact, the accuracy of the copy transistor is inversely proportional to the square root of the surface area of this transistor (see the expression for acc given above).

(50) FIG. 4 illustrates the accuracy of circuits according to FIG. 1 as curve A, and the accuracy of circuits according to embodiments of the invention as curve B.

(51) For a same short-circuit current limit value I.sub.0, the y axis plots the number of circuits offering effective limiting to a given current limit value.

(52) The distribution of circuits is Gaussian, centered around I.sub.0. One can see that for circuits according to embodiments of the invention, the Gaussian curve is more narrow, which clearly illustrates the gain in accuracy in comparison to the limiting loops of FIG. 1.

(53) FIG. 5 illustrates an embodiment of the comparators COMP31 and COMP32 described above with reference to FIG. 3.

(54) The comparators are operational amplifiers. The comparator COMP32 operates for low voltages, and the comparator COMP31 operates for high voltages.

(55) V.sub.s represents their common output, V− their common inverting input, and V+ their common non-inverting input.

(56) A method for controlling a regulator is described with reference to FIG. 6. First the current I.sub.mirror is generated during a step of copying the output current S60. The mirror current is then compared to the reference current during the step S61. If during the step T62 it is determined that the mirror current is greater than the reference current, a means of supplying feedback to the regulator is brought into play during the step S63 in order to limit the output current.

(57) Lastly, in a final step S64, the mirror current is injected into the regulator output. During this step, the reference current can also be injected.

(58) A computer program comprising instructions for implementing the method can be deduced from the general flowchart in FIG. 6.

(59) A device is described with reference to FIG. 7, comprising a regulator of the invention. This device can be of various types. In fact it can be any device in which an LDO regulator is used.

(60) In this device DEV, there is a memory MEM, in particular for storing a computer program according to the invention, a processor PROC for implementing this program, a regulator REGUL, and a unit CIRC to which is supplied the regulated voltage provided by the regulator. The regulator comprises a regulating unit M.sub.REG and an output current limiting unit M.sub.LIM.

(61) Of course, the invention is not limited to the embodiments described above. It extends to all equivalent variations.