Electricity distribution networks

Abstract

An alternating current power electronic converter includes an alternating current chopper circuit including two pairs of switches, each switch of a pair connected in series and the two pairs of switches connected in parallel. Each switch of a pair is a uni-directional switch. The uni-directional switches of each pair are arranged in opposing directions, and the uni-directional switches of one pair of switches are arranged in an opposing configuration to the uni-directional switches of the other pair of switches. The circuit comprises a bridge connection between switches of each pair of switches. A controller is configured to control a sequence of operation of the switches, providing an overlap period whenever one of the switches of a pair changes from open to closed and the other switch of the pair changes from closed to open. During the overlap period the switch that is moving from closed to open remains closed.

Claims

1. An alternating current power electronic converter comprising: an alternating current chopper circuit including two pairs of switches, each switch of a pair connected in series, and the two pairs of switches connected in parallel, wherein each switch of a pair is a uni-directional switch and wherein the uni-directional switches of each pair are arranged in opposing directions; wherein the uni-directional switches of one pair of switches are arranged in an opposing configuration to the uni-directional switches of the other pair of switches; wherein the circuit comprises a bridge connection between the two pairs of switches, the bridge connection being between the uni-directional switches of each pair; and wherein the alternating current power electronic converter further comprises a controller configured to control a sequence of operation of the switches, the sequence providing an overlap period whenever one of the uni-directional switches of a pair changes from open to closed and the other uni-directional switch of the pair changes from closed to open, and wherein during the overlap period the uni-directional switch that is moving from closed to open remains closed.

2. The alternating current power electronic converter according to claim 1, wherein each of the uni-directional switches includes a transistor and a diode, wherein the diodes of each pair are arranged in opposing directions, and wherein the diodes of one pair of switches are arranged in an opposing configuration to the diodes of the other pair of switches.

3. The alternating current power electronic converter according to claim 1, further comprising an inter-phase transformer comprising two inductors that is connected to each pair of switches, wherein the connection to each pair of switches is between the switches of each pair.

4. The alternating current power electronic converter according to claim 3, further comprising an LC filter, wherein the LC filter is connected to the inter-phase transformer and ground.

5. The alternating current power electronic converter according to claim 3, further comprising a voltage clamp arranged to clamp a voltage across the inductors of the inter-phase transformer on shut-down of the alternating current electronic power converter.

6. The alternating current power electronic converter according to claim 5, wherein the voltage clamp is an active clamp or a passive clamp.

7. The alternating current power electronic converter according to claim 6, wherein the controller is configured to operate the switches of the pairs to provide dead-time when opening and closing switches of different pairs of switches, and to overlap when opening and closing switches of a pair.

8. The alternating current power electronic converter according to claim 3, wherein the inductors are configured in: a cumulatively coupled series configuration; or a differentially coupled series configuration.

9. The alternating current power electronic converter according to claim 1, wherein the controller: is configured to control the sequence of operation of the uni-directional switches such that the sequence provides a dead-time when switching switches of different pairs of switches between open and closed statuses; or includes at least one of: a pulse width modulator; a dead-time generator or a sequence multiplexer; or includes at least one of: a voltage polarity detector; a voltage controller; a current controller; or a voltage and/or current controller.

10. The alternating current power electronic converter according to claim 9, wherein the controller includes the voltage polarity detector, and the voltage polarity detector is an opto-isolator.

11. A power distribution network comprising: a local substation having a high voltage input in the order of thousands of volts and a low voltage output in the order of hundreds of volts; electricity distribution cabling connected to the low voltage output of the local substation; at least one electricity consumer connected to the cabling, the at least one electricity consumer operating at an operating voltage that is less than the low voltage output of the substation; and the alternating current power electronic converter according to claim 1 situated between the electricity distribution cabling and the electricity consumer, wherein an input voltage to the alternating current power electronic converter is the low voltage output voltage of the local substation and an output voltage of the alternating current power electronic converter corresponds to the operating voltage of the at least one electricity consumer.

12. The power distribution network according to claim 11, wherein an input line/phase voltage of the high voltage input to the local substation is 11/6.35 kV+10/−6%.

13. The power distribution network according to claim 11, wherein an output line/phase voltage of the low voltage output of the local substation is 600/346 V.

14. A power distribution network according to claim 13, wherein the controller: is configured to control the sequence of operation of the uni-directional switches such that the sequence provides a dead-time when switching switches of different pairs of switches between open and closed statuses; or includes at least one of: a pulse width modulator; a dead-time generator or a sequence multiplexer; and includes at least one of: a voltage polarity detector; a voltage controller; a current controller, or a voltage and/or current controller.

15. A power distribution network according to claim 14, wherein the controller includes the voltage polarity detector, and the voltage polarity detector is an opto-isolator.

16. The power distribution network according to claim 11, wherein the output voltage of the alternating current power electronic converter is 230V+10%/−6%.

17. The power distribution network according to claim 11, wherein each of the uni-directional switches includes a transistor and a diode, wherein the diodes of each pair are arranged in opposing directions, and wherein the diodes of one pair of switches are arranged in an opposing configuration to the diodes of the other pair of switches.

18. The power distribution network according to claim 11, further comprising an inter-phase transformer comprising two inductors that is connected to each pair of switches, wherein the connection to each pair of switches is between the switches of each pair.

19. The power distribution network according to claim 18, further comprising an LC filter, wherein the LC filter is connected to the inter-phase transformer and ground.

20. The power distribution network according to claim 18, further comprising a voltage clamp arranged to clamp a voltage across the inductors of the inter-phase transformer on shut-down of the alternating current electronic power converter.

21. A power distribution network according to claim 20, wherein the voltage clamp is an active clamp or a passive clamp.

22. A power distribution network according to claim 18, wherein the inductors are configured in: a cumulatively coupled series configuration; or a differentially coupled series configuration.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the Drawings, which illustrate preferred embodiments of the power electronic converter according to the present disclosure and circuits known in the art:

(2) FIG. 1 is a circuit diagram of the chopper circuit which forms part of the present disclosure;

(3) FIG. 2 illustrates a cumulatively coupled series connection of the inductors of the circuit illustrated in FIG. 1;

(4) FIG. 3 illustrates a differentially coupled series connection of the inductors of the circuit illustrated in FIG. 1;

(5) FIG. 4 illustrates the switching pattern for the transistors of the circuit illustrated in FIG. 1 when the input voltage is positive;

(6) FIG. 5 illustrates the switching pattern for the transistors of the circuit illustrated in FIG. 1 when the input voltage is negative;

(7) FIG. 6 is a schematic illustrating operating quadrants of the circuit illustrated in FIG. 1 based on polarity of input voltage and polarity of output current;

(8) FIGS. 7a to 7c illustrate the circuit shown in FIG. 1 in different states through a full switching cycle when the input voltage is positive and the output inductor current is positive;

(9) FIG. 8 illustrates the circuit's voltages and currents during a full switching cycle when the input voltage is positive and the output inductor current is positive;

(10) FIGS. 9a to 9c illustrate the circuit shown in FIG. 1 in different states through a full switching cycle when the input voltage is positive and the output inductor current is negative;

(11) FIG. 10 illustrates the circuit's voltages and currents during a full switching cycle when the input voltage is positive and the output inductor current is negative;

(12) FIG. 11 illustrates the chopper circuit shown in FIG. 1 with a passive over voltage clamp protection circuit;

(13) FIG. 12 illustrates the chopper circuit shown in FIG. 1 with an active over voltage clamp protection circuit;

(14) FIG. 12 is a circuit diagram illustrating a passive clamp;

(15) FIG. 13 is a circuit diagram illustrating an active clamp;

(16) FIG. 14 is a circuit diagram illustrating the power electronic converter located between the 346 V network and the 230 V consumer;

(17) FIG. 15 is a circuit diagram illustrating an opto-coupler based voltage polarity detector circuit;

(18) FIG. 16 is a schematic diagram illustrating an electricity distribution network including power electronic converters of the present disclosure;

(19) FIG. 17 is a circuit diagram of a traditional AC Chopper circuit; and

(20) FIG. 18 is a circuit diagram of an alternative AC Chopper circuit of prior art.

DETAILED DESCRIPTION

(21) Referring now to FIG. 1, the power electronics converter is in the form of a new AC chopper circuit 1. The circuit 1 includes an input power supply Vs which provides an alternating voltage. The circuit 1 comprises four uni-directional switch units 2a to 2d. The switch units operate in pairs 2a, 2b and 2c, 2d. Each uni-directional switch unit comprises a switch S.sub.1 to S.sub.4 and a diode D.sub.1 to D.sub.4. Each switch S.sub.1 to S.sub.4 is a transistor. Each transistor is connected in series with a respective diode D.sub.1 to D.sub.4. The switch units 2a, 2b and hence switches S.sub.1, S.sub.2 and their respective diodes D.sub.1, D.sub.2 are connected in series in a pair. The switch units 2c, 2d and hence switches S.sub.3 and S.sub.4 and their respective diodes D.sub.3, D.sub.4 are also connected in series in a pair.

(22) The switches S.sub.1 and S.sub.2 and their respective diodes D.sub.1, D.sub.2 are arranged to permit the flow of current in opposite directions. Current flowing in a direction permitted by diode D.sub.1 cannot flow through D.sub.2 and similarly, current flowing in the opposite direction is permitted by diode D.sub.2 but prevented by diode D.sub.1.

(23) The pairs of switch units are connected in parallel. An inductor circuit 3 connects the respective pairs of switches 2a, 2b to 2c, 2d, forming a bridge therebetween.

(24) An inductor circuit 3 comprises mutual inductors L.sub.11 and L.sub.22 which are connected together and to the two legs of the chopper circuit 1 between the diodes D.sub.1, D.sub.2 of the switch unties 2a, 2b and the diodes D.sub.3, D.sub.4 of the switch units 2c, 2d. The inductor circuit 3 includes an inductor capacitor filter which comprises an inductor L.sub.fo connected in series with a capacitor C.sub.fo and a load Z.sub.load. The capacitor C.sub.fo and load Z.sub.load are connected in parallel.

(25) FIG. 1 illustrates one possible configuration of the mutual inductors L.sub.11, L.sub.22, that being a cumulatively coupled series configuration. It is also possible for the inductors L.sub.11, L.sub.22 to be connected in a differentially coupled series.

(26) FIG. 2 illustrates an inductor circuit 3a having a cumulatively coupled series configuration of inductors L.sub.11, L.sub.22 in which the current flows through the inductors L.sub.11, L.sub.22 in the same direction. The equivalent blocking inductance from this arrangement across a-b is:
L.sub.ab=(L.sub.11+M)+(L.sub.22+M)=L.sub.11+L.sub.22+2M

(27) FIG. 3 illustrates a circuit 3a′ having differentially coupled series inductors L.sub.11, L.sub.22 in which the current flows through the inductors L.sub.11, L.sub.22 in opposing directions. In this arrangement the equivalent blocking inductance across a-b is:
L.sub.ab=(L.sub.11+M)+(L.sub.22+M)=L.sub.11+L.sub.22+2M

(28) FIGS. 4 to 12 all relate to the cumulative coupled series inductors illustrated in FIGS. 1 and 2.

(29) The diodes D.sub.1, D.sub.2 and D.sub.3, D.sub.4 are arranged for the passage of electrical current in opposing directions. Due to this arrangement each pair of uni-directional switches 2a, 2b and 2c, 2d are immune to shoot through. This means that no dead-time is required.

(30) The arrangement of a current carrying inductor between the two legs of the circuit means that an overlap in the switching of the transistors S.sub.1, S.sub.2 and S.sub.3, S.sub.4 respectively is required in order to remove the need for snubbers that are essential to the circuit shown in FIG. 18. This overlap of switching provides a free-wheeling path for the inductors L.sub.11, L.sub.22. The free-wheeling path prevents a floating current developing in the inductors L.sub.11, L.sub.22.

(31) Dead-time is required between the switching of switches 2a, 2d and 2c, 2b. Where the input voltage is positive (Vs>0), switch pairs 2a, 2d could short circuit the input source via inductors L.sub.11, L.sub.22 if they were on simultaneously. Hence, a blank time (dead-time) is required between switching on 2a and switching on 2d.

(32) Similarly, when the input voltage is negative (Vs<0), the switches 2b, 2c could short circuit the input source via inductors L.sub.11, L.sub.22 if they were on simultaneously. Hence, a dead-time is required between switching on 2b and switching on 2c.

(33) The circuit 1 avoids shoot-through when switching between legs by providing a voltage polarity based switching pattern which selects the priority of the switching legs and a dead-time between during which only one of the switches 2a, 2d or 2b, 2c is on.

(34) Suitable switching patterns for switches 2a-2d when the input voltage is positive (Vs>0) are shown in FIG. 4.

(35) Suitable switching patterns for switches 2a-2d when the input voltage is negative (Vs<0) are show in FIG. 5.

(36) FIGS. 4 and 5 show that for each commutation there are two overlap periods and one dead-time period. The overlap period must be long enough to ensure that the switching transition of the transistors S.sub.1 to S.sub.4 of switch 2a to 2d have been completed. The duration of overlap period is function of the switching speed of semiconductors and varies from tens of nanoseconds to a few microseconds.

(37) Referring now to FIG. 6, the circuit 1 is operated on a four quadrant (quadrants Q1 to Q4) methodology based on the polarity of the input voltage (V.sub.s) and direction of the output current (I.sub.Lfo). In quadrant Q1 the input voltage V.sub.s is positive (V.sub.s>0) and the output inductor current (I.sub.Lfo) is positive (I.sub.Lfo>0). In quadrant Q2 the input voltage (Vs) is positive (V.sub.s>0) and the output inductor current (I.sub.Lfo) is negative (I.sub.Lfo<0). In quadrant Q3 the input voltage (V.sub.s) is negative (V.sub.s<0) and the output inductor current (I.sub.Lfo) is negative (I.sub.Lfo<0) and in Q4 the input voltage is negative (V.sub.s<0) and the output inductor current (I.sub.Lfo) is positive (I.sub.Lfo>0).

(38) FIGS. 7a to 7c and 8 illustrate the operation of the circuit in Q1, that is positive input voltage (V.sub.s>0) and the positive output inductor current (I.sub.Lfo>0).

(39) Referring first to FIGS. 7a to 7c, the set of circuit configurations shown are labelled 0 to 8. FIG. 8 shows the switch status, switch current (I.sub.S1-S4), input voltage (V.sub.o1, o2) and output inductor current (I.sub.Lfo) for each numbered circuit configuration of FIGS. 7a to 7c.

(40) FIGS. 7a to 7c illustrate the status of the switches S.sub.1 to S.sub.4 in the circuit 1 during a full cycle of switching when the input voltage is positive and the output inductor current (I.sub.Lfo) is positive.

(41) In configuration 0 switches S.sub.1, S.sub.3 are open and S.sub.2, S.sub.4 are closed providing a conductive pathway through the inductor bridge.

(42) Configuration 1 provides an overlap period during which switch S.sub.4 remains closed whilst switch S.sub.3 moves from open to closed. The overlap period allows the closed and open switches in the leg S.sub.3, S.sub.4 to change. The overlap period provides the continuous free-wheeling path required by the inductors L.sub.11, L.sub.22 and output filter inductor L.sub.fo. Configuration 2 provides a period of time (a dead-time) in which S.sub.1D.sub.1 has not changed state (is remains open) whereas S.sub.4D.sub.4 has changed state (from closed to open).

(43) Configuration 3 provides another overlap period for switching S.sub.1D.sub.1 from open to closed and S.sub.2D.sub.2 from closed to open in which the status of S.sub.1D.sub.1, S.sub.2D.sub.2 overlap (they are both closed in configuration 3).

(44) Configurations 4 and 5 provide a circuit configuration in which current flows.

(45) Configurations 6, 7 and 8 correspond to configurations 4, 3 and 2 respectively.

(46) FIGS. 9a to 9c illustrate the configuration of the circuit 1 in quadrant 2 of FIG. 6, that is when the input voltage is positive (Vs>0) and the inductor current is negative (I.sub.Lfo<0).

(47) FIG. 10 shows the switch status, switch current (IS.sub.1-S.sub.4), input voltage (V.sub.01, 02) and output inductor current (I.sub.Lfo) for each numbered circuit configuration of FIGS. 9a to 9c.

(48) In configuration 0 switches S.sub.1, S.sub.3 are open and S.sub.2, S.sub.4 are closed providing a conductive pathway through the inductor bridge.

(49) Configuration 1 provides an overlap period during which switch S.sub.4 remains closed whilst switch S.sub.3 moves from open to closed. The overlap period allows the closed and open switches in the leg S.sub.3, S.sub.4 to change. The overlap period provides the continuous free-wheeling path required by the inductors L.sub.11, L.sub.22 and output filter inductor L.sub.fo.

(50) With a positive input voltage, switch pairs S.sub.1, S.sub.4 cannot be switched from their current states simultaneously, since to do so can short circuit the input source via L.sub.11 and L.sub.22.

(51) Configuration 2 provides a period of time (a dead-time) in which S.sub.1D.sub.1 has not changed state (is remains open) whereas S.sub.4D.sub.4 has changed state (from closed to open).

(52) Configuration 3 provides another overlap period for switching S.sub.1D.sub.1 from open to closed and S.sub.2D.sub.2 from closed to open in which the status of S.sub.1D.sub.1, S.sub.2D.sub.2 overlap (they are both closed in configuration 3).

(53) Configurations 4 and 5 provide a circuit configuration in which S.sub.1 and S.sub.3 are closed (current flowing) and S.sub.2 and S.sub.4 open.

(54) The status of switches S.sub.1 to S.sub.4 in configurations 6, 7 and 8 correspond to status of those switches in configurations 4, 3 and 2 respectively.

(55) Referring now to FIG. 11, the basic AC chopper circuit 1 is illustrated with an over voltage protection circuit 10 in the form of a diode clamp. When the transistors are disabled simultaneously, for example during an over-current fault the circuit may be shut down causing the transistors to be disabled simultaneously. This may result in a very high di/dt since the inductors' current has no path through which to circulate. Very high voltages may be generated across the switches. The function of the diode clamp is to protect the circuit against such high voltages that would otherwise be generated across the switches.

(56) The diode clamp circuit 10 comprises a capacitor 11 and four pairs of uni-directional diodes 12a, 12b; 12c, 12d; 12e, 12f; and 12g, 12h. The diode pair 12a, 12b is connected to the circuit 1 between switches 2c, 2d. Diode pair 12g, 12h is connected to circuit 1 between switches 2a, 2b. Diode pair 12c, 12d is connected to ground and diode pair 12e, 12f to Vs, the input voltage. In normal operation the capacitor 11 is charged to the peak input voltage. If a situation arises where all the switches 2a-2d shut down simultaneously, the capacitor 11 is charged above the peak voltage. The capacitor must be sized according to the voltage limit on the switches 2a-2d and the maximum amount of energy that may be trapped in the inductors L.sub.11, L.sub.22 and L.sub.fo.

(57) An alternative to the diode clamp circuit illustrated in FIG. 11 is an active clamp (illustrated in FIG. 13), which operates and dissipates excessive energy injected into the clamp capacitor only if the voltage on the clamp capacitor rises above a certain threshold. A suitable active voltage clamp circuit 15 is illustrated in FIG. 13. The circuit includes a capacitor 16. If the voltage across the capacitor rises above a reference value, the switch 18, which may be a MOSFET for example, is turned on and excess energy is dissipated through the resistor 22 in order to keep the voltage below the threshold. The circuit 15 induces pairs of diodes 17a, 17b; 17c, 17d; 17e, 17f and 17g, 17h. Diode pair 17g, 17h is connected to ground, diode pair 17a, 17b to Vs, diode pair 17c, 17d to V.sub.o1 and diode pair 17e, 17f to V.sub.o2.

(58) FIG. 12 illustrates a passive clamp similar to the clamp shown in FIG. 11, the difference being the presence of a resistor in parallel with the capacitor thereby providing for continuous power dissipation to keep the voltage across the inductors L.sub.11, L.sub.22 within safe limits in the case of a rise in voltage.

(59) FIG. 14 illustrates the AC chopper circuit 1 showing FIGS. 1 and 11 and its position between the 346 V network 30 and the 230 V consumer circuit 40. The AC chopper circuit 1 includes a voltage clamp circuit 11. A control unit 20 which includes a voltage polarity detector, a pulse width modulator, dead-time generator and sequence multiplier 22 and a voltage and current controller 23 is connected to the network 30, the switches of the AC chopper circuit 1 and the output of the AC chopper circuit 1.

(60) The voltage polarity detector 21 receives a voltage input signal from the network 30. The output of the voltage polarity detection circuit 21 is the input to the pulse width modulator, dead-time generator and sequence multiplexer 22, which receives another input from the voltage and current controller 23. The voltages and current controller 23 receive input signals representing the output current and output voltage fo the AC chopper circuit 1.

(61) Switches 2a to 2d are connected electrically to the pulse width modulator, dead-time generator and sequence multiplexer 22, which controls the sequencing of operation of the switches 2a to 2d.

(62) FIG. 15 illustrates a polarity detector circuit in the form of an opto-isolator. However, errors may occur in the detection of voltage polarity. This may cause the wrong switching sequence to be applied to the transistors of switches 2a-2d. For example, if transistors S.sub.1 and S.sub.4 are caused to be on during an overlap period shoot through will be caused. The magnitude of the shoot through current is limited by the mutually coupled inductor L.sub.11 and L.sub.22, which forms an inter-phase transformer. The shoot through current continues to rise whilst the polarity error exists, but decays back to zero once the error is cleared.

(63) The specification of the inter-phase transformer is a compromise between limiting the size of its magnetizing inductance, the magnitude of the corresponding shoot through current and the duration of voltage polarity errors.

(64) The AC chopper circuit of the present disclosure is very tolerant of errors in detection of voltage polarity. This is due to the inter-phase transformer L.sub.11, L.sub.22.

(65) FIG. 16 is a schematic representation of the local network of a mains electricity distribution network. The local network 30 comprises a substation 31 having a line/phase voltage of 11/6.35 kV input 50 and a 600/346 V output which is distributed along a cable 32. Electricity consuming units, in the form of houses 40 are each provided with a meter box 41. The meter box includes the components illustrated in FIG. 14 which are connected to the network 30 and electricity consuming units 40 in the manner illustrated in FIG. 14. As can be seen from FIG. 16, some of the houses 40 have solar panels 42 mounted on their roofs 43. Some of the houses 40 have electric vehicles 44 connected thereto. The distribution of electricity at 346 V, provides for greater efficiency of transmission, since the resistance losses are much lower than for distributing electricity along cable 32 at 230 V. This becomes more important as the use of electric vehicles and the presence of consumer level power generation increases.

(66) Whilst the AC chopper circuit of the present disclosure is described in relation to a power converter for use in a mains electricity distribution network, the circuit has other uses. The circuit has the functionality of an AC-AC autotransformer and hence would be useful in, but not limited to, the following applications: a voltage controller for an AC motor; a voltage level shifter for 110 V loads; in balancing transmission line loads; for providing a variable AC voltage power supply; providing a soft-start circuit for loads with high startup currents; as an electronic tap-changer for transformers.