Three phase power quality measurement using asynchronous, isolated single phase circuits

Abstract

A system and method utilize multiple, asynchronous, voltage isolated integrated power data circuits (IPDCs) to respectively determine one or more power parameters of a multi-phase power distribution system. In at least one embodiment, the power parameters represent differences between voltage phases of a multi-phase power distribution system. In at least one embodiment, the IPDCs each sense a voltage or current from a single phase of a three-phase power distribution system. Additionally, the IPDCs are electrically isolated from each other and, thus, in at least one embodiment, can utilize voltage divider or shunt resistor sensing without being subject to high voltages representative of the difference between voltage phases. Additionally, in at least one embodiment, each of the IPDCs utilizes a separate clock signal to determine phase sequence and phase angle deltas of one or more three phase voltages of the three-phase power distribution system.

Claims

1. A method of operating multiple, asynchronous, voltage isolated integrated power data circuits to acquire and process data for a three-phase power distribution system, the method comprising: providing a master processor in the three phase-power distribution system to operate the multiple, asynchronous, voltage isolated integrated power data circuits; providing a common start command, from the master processor and distinct from one or more clock signals, to the multiple, asynchronous, voltage isolated integrated power data circuits to initiate concurrent data acquisition by the multiple, asynchronous, voltage isolated integrated power data circuits to obtain respective data for respective voltages of the three-phase power distribution system to provide data distinct from the data obtained to allow determination of one or more power parameters for the voltages in the three-phase voltage distribution system; providing the data to the master processor; determining values of the one or more power parameters with the master processor; and providing access to the values of the one or more power parameters determined with the master processor for phase sequence detection and phase angle detection in the three-phase power distribution system.

2. The method of claim 1 wherein determining the one or more power parameters with the processor comprises determining a phase sequence of the voltages and phase angle deltas between at least two sets of the voltages.

3. The method of claim 1 wherein one of the integrated power data circuits includes the processor for determining the one or more power parameters with the processor.

4. The method of claim 1 wherein a voltage on each of the respective voltage lines is greater than a supply voltage to the multiple integrated power data circuits.

5. The method of claim 1 wherein each of the multiple, asynchronous, voltage isolated integrated power data circuits includes a phase angle data processor, the method further comprising: clocking each of the integrated power data circuits with respective asynchronous clock signals.

6. The method of claim 1 wherein each of the multiple, asynchronous, voltage isolated integrated power data circuits include respective input channels that are electrically isolated from each other.

7. The method of claim 1 further comprising: determining an occurrence of a common event after initiation of the concurrent data acquisition in each of the voltages in the three-phase voltage distribution system; and determining a difference in phases between the voltages based on elapsed time between receiving the start command and the common event.

8. The method of claim 7 wherein the common event is one of a positive-to-negative zero crossing of each of the voltages or a negative-to-positive zero crossing of each of the voltages.

9. The method of claim 7 further comprising: compensating for intra-sample timing differences between samples of the voltages and receipt of the start command and samples of the voltages and occurrence of the common event.

10. The method of claim 1 wherein determining the one or more power parameters with the processor comprises: determining root mean square values of the voltages and differences between the voltages; and processing the root means square voltages using a law of cosines to determine phase angles between the voltages.

11. An apparatus comprising: a power measurement system that includes a master processor that operates multiple, asynchronous, voltage isolated integrated power data circuits to acquire and process data for a three-phase power distribution system, wherein the master processor of the power measurement system is configured to: provide a common start command, distinct from one or more clock signals, to the multiple, asynchronous, voltage isolated integrated power data circuits to initiate concurrent data acquisition by the multiple, asynchronous, voltage isolated integrated power data circuits to obtain respective data for respective voltages of the three-phase power distribution system to provide data distinct from the data obtained to allow determination of one or more power parameters for the voltages in the three-phase voltage distribution system; determine values of the one or more power parameters with the master processor; and provide access to the values of the one or more power parameters determined with the master processor for phase sequence detection and phase angle detection in the three-phase power distribution system.

12. The apparatus of claim 11 wherein to determine the one or more power parameters with the processor comprises to determine a phase sequence of the voltages and phase angle deltas between at least two sets of the voltages.

13. The apparatus of claim 11 wherein one of the integrated power data circuits includes the processor for determining the one or more power parameters with the processor.

14. The apparatus of claim 11 wherein a voltage on each of the respective voltage lines is greater than a supply voltage to the multiple, asynchronous, voltage isolated integrated power data circuits.

15. The apparatus of claim 11 wherein each of the multiple, asynchronous, voltage isolated integrated power data circuits includes a phase angle data processor, the power measurement system is further configured to: clock each of the integrated power data circuits with respective asynchronous clock signals.

16. The apparatus of claim 11 wherein each of the multiple, asynchronous, voltage isolated integrated power data circuits include respective input channels that are electrically isolated from each other.

17. The apparatus of claim 11 wherein the power measurement system is further configured to: determine an occurrence of a common event after initiation of the concurrent data acquisition in each of the voltages in the three-phase voltage distribution system; and determine a difference in phases between the voltages based on elapsed time between receiving the start command and the common event.

18. The apparatus of claim 17 wherein the common event is one of a positive-to-negative zero crossing of each of the voltages or a negative-to-positive zero crossing of each of the voltages.

19. The apparatus of claim 17 wherein the power measurement system is further configured to: compensate for intra-sample timing differences between samples of the voltages and receipt of the start command and samples of the voltages and occurrence of the common event.

20. The apparatus of claim 11 wherein to determine the one or more power parameters with the processor comprises: to determine root mean square values of the voltages and differences between the voltages; and to process the root means square voltages using a law of cosines to determine phase angles between the voltages.

21. A power measurement system that operates multiple, asynchronous, voltage isolated integrated power data circuits to acquire and process data for a three-phase power distribution system, the power measurement system comprising: means for initiating concurrent data acquisition by the multiple, asynchronous, voltage isolated integrated power data circuits to obtain respective data for respective voltages of a three-phase power distribution system to determine one or more power parameters for the voltages in the three-phase voltage distribution system, wherein the means for initiating concurrent data acquisition comprises: means for providing a common start command, distinct from one or more clock signals, to the multiple, asynchronous, voltage isolated integrated power data circuits to initiate concurrent data acquisition by the multiple, asynchronous, voltage isolated integrated power data circuits to obtain respective data for the respective voltages in the three-phase power distribution system to provide data distinct from the data obtained to allow determination of one or more power parameters for the voltages in the three-phase voltage distribution system; means for determining values of the one or more power parameters; and means for providing access to the values of the one or more power parameters determined for phase sequence detection and phase angle detection in the three-phase power distribution system.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the several figures designates a like or similar element.

(2) FIG. 1 (labeled prior art) depicts a power distribution system that includes a power measurement system that measures various characteristics of the three phase power.

(3) FIG. 2 (labeled prior art) depicts ideal, three-phase voltage waveforms.

(4) FIG. 3 depicts an embodiment of a power distribution system having a power measurement system with isolated, asynchronous clocked integrated power data circuits for processing power parameters from a three-phase power distribution system.

(5) FIG. 4 depicts another embodiment of a power distribution system having a power measurement system with isolated, asynchronous clocked integrated power data circuits for processing power parameters from a three-phase power distribution system.

(6) FIG. 5 depicts an embodiment of a phase angle data processor.

(7) FIG. 6 depicts a phase angle data process.

(8) FIG. 7 depicts exemplary waveforms associated with the phase sequence and phase angle detection process of FIG. 6.

(9) FIG. 8 depicts an exemplary intra-sample START command.

(10) FIG. 9 depicts exemplary voltage samples before and after a zero crossing of the voltage.

(11) FIG. 10 depicts a zoomed view of a voltage near a zero crossing of the voltage.

(12) FIG. 11 depicts an exemplary master processor of the power measurement systems of FIGS. 3 and 4.

(13) FIG. 12 depicts a signal conditioning processing block.

(14) FIG. 13 depicts a power distribution system using shunt resistor sampling.

(15) FIG. 14 depicts a law of cosines based phase angle data processor.

(16) FIG. 15 depicts a conceptual three-phase relationship root mean square voltages of three voltages.

DETAILED DESCRIPTION

(17) A system and method utilize multiple, asynchronous, voltage isolated integrated power data circuits (IPDCs) to respectively determine one or more power parameters of a multi-phase power distribution system. In at least one embodiment, the power parameters represent differences between voltage phases of a multi-phase power distribution system. In at least one embodiment, the IPDCs each sense a voltage or current from a single phase of a three-phase power distribution system. Additionally, the IPDCs are electrically isolated from each other because, for example, the IPDCs include respective input channels that receive respective, isolated input voltages, and, thus, in at least one embodiment, can utilize low cost (relative to conventional three-phased monolithic integrated circuit based systems) voltage divider or shunt resistor sensing without being subject to high voltages representative of the difference between voltage phases. Additionally, in at least one embodiment, each of the IPDCs utilizes a separate clock signal to determine phase sequence and phase angle deltas of one or more three phase voltages of the three-phase power distribution system. A phase angle “delta” represents a difference between phases of two signals, such as the difference between a phase of a first voltage and a phase of a second voltage. The clock signal of each IPDC is asynchronous to the clock signals of the other ICs. The power measurement system utilizes a common start command to initiate power parameter data acquisition and a phase sequence and phase angle detection process to determine and/or provide highly accurate data for phase sequence detection and phase angle detection despite the asynchronous clock signals. In at least one embodiment, the power measurement system has a phase angle accuracy with a typical 0.1 degree or better relative phase angle accuracy.

(18) In at least one embodiment, utilizing multiple, asynchronous, voltage isolated IPDCs to determine one or more power parameters in a multi-phase power distribution system reduces system complexity and allows utilization of smaller and cheaper, single phase power measurement ICs. Furthermore, in at least one embodiment, the IPDCs detect the one or more power parameters with a relatively low frequency sampling, such as approximately 4 kHz, which reduces hardware costs and chip area for the ICs. Furthermore, in at least one embodiment, the power measurement system achieves approximately 0.1 degree phase accuracy without clock synchronization between the IPDCs and no isolation circuitry between the ICs.

(19) FIG. 3 depicts a three phase power distribution system 300 that includes a multi-IC power measurement system 302. The IPDCs 304, 306, and 308 respectively sense the phase A voltage V.sub.A, the phase B voltage V.sub.B, and the phase C voltage V.sub.C via respective channels 310, 312, and 314. In the embodiment of FIG. 3 and FIG. 4, the voltages V.sub.A, V.sub.B, and V.sub.C are configured in a wye configuration with a neutral line N. The subsequently described system and processes are equally applicable to other connection configurations, such as a delta connection configuration or mixed delta-wye connection configuration. In at least one embodiment, the power measurement system 302 is a fixed or portable power meter.

(20) Each of the IPDCs 304, 306, and 308 includes a separate, respective clock signal CLK_A, CLK_B, and CLK_C. The IPDCs 304, 306, and 308 are electrically isolated from each other because, for example, the respective input channels 310, 312, and 314 receive respective, isolated input voltages V.sub.A, V.sub.B, and V.sub.C, and, thus, the clock signals are asynchronous with respective each other. Each of the IPDCs 304, 306, and 308 includes a respective phase angle data processor 316, 318, and 320 to obtain the data for determination of the respective phase sequences and relative phase angles of the voltages V.sub.A, V.sub.B, and V.sub.C. A master processor 322 is electrically isolated from the IPDCs 304, 306, and 308 via an isolation path 324. The design of the isolation path 324 is a matter of choice and, for example, includes optical isolation circuits (not shown) to provide electrical isolation.

(21) The master processor 322 concurrently initiates concurrent data acquisition by the IPDCs 304, 306, and 308 to obtain respective data for respective voltages of the three-phase power distribution system 300 to determine one or more power parameters for the voltages in the three-phase voltage system. To initiate the concurrent data acquisition, the master processor 322 provides a START command data to each of the IPDCs 304, 306, and 308. The IPDCs 304, 306, and 308 begin concurrent data acquisition of respective sensed voltages V.sub.A, V.sub.B, and V.sub.C. In at least one embodiment, the IPDCs 304, 306, and 308 sense the voltages V.sub.A, V.sub.B, and V.sub.C via respective voltage dividers 118, 120, and 122 and provide respective phase sequence signals φ.sub.A.sub._.sub.SEQ, φ.sub.B.sub._.sub.SEQ, and φ.sub.C.sub._.sub.SEQ to the master processor 322. The phase sequence signals φ.sub.A.sub._.sub.SEQ, φ.sub.B.sub._.sub.SEQ, and φ.sub.C.sub._.sub.SEQ represent data that allows the master processor 322 to determine the phase sequence of the respective voltages V.sub.A, V.sub.B, and V.sub.C. The respective phase angle data processor 316, 318, and 320 also provide respective phase angle data φ.sub.A, φ.sub.B, and φ.sub.C from the sensed voltages V.sub.A, V.sub.B, and V.sub.C. As subsequently described in more detail, the master processor 322 receives and utilizes the phase sequence signals φ.sub.A.sub._.sub.SEQ, φ.sub.B.sub._.sub.SEQ, and φ.sub.C.sub._.sub.SEQ and phase angle data φ.sub.A, φ.sub.B, and φ.sub.C to determine the relative phase sequences and phase angles of the voltage V.sub.A, V.sub.B, and V.sub.C. The master processor 322 then makes the power parameter data 326 available for transmission, display, and/or subsequent access from a memory (not shown).

(22) FIG. 4 depicts a three phase power distribution system 400. The three phase power distribution system 400 includes a multi-IC power measurement system 402 that is identical to the power measurement system 302 except that the functions described for the master processor 322 are incorporated into the master processor 404 of the IPDC406. In at least one embodiment, including the master processor 404 in the IPDC406 eliminates the master processor 322 from the power measurement system 400. In at least one embodiment, the power measurement system 302 (FIGS. 3) and 402 include memory, a transmitter, and/or a display (not shown) to make the power parameter data 326 available for machine and/or human access.

(23) FIG. 5 depicts an exemplary phase angle data processor 500. The phase angle data processor 500 is an embodiment of each of the phase angle data processors 316, 318, and 320. The general principle of the phase angle data processor 500 is to determine an accurate measure of time between the START command and a common event among the three voltage phases V.sub.A, V.sub.B, and V.sub.C. The particular common event is a matter of design choice. In at least one embodiment, the common event is a zero crossing of each of the voltage phases during a positive-to-negative transition or a negative-to-positive transition. To determine the accurate measure of time between the START command and the common event, the phase angle data processor 500 determines several values, as, for example, described below, that are utilized by a master processor to determine phase angle deltas in a three-phase voltage distribution system.

(24) FIG. 6 depicts an exemplary phase sequence and phase angle detection process 600. FIG. 7 depicts exemplary waveforms 700 associated with the phase sequence and phase angle detection process 600. Referring to FIGS. 5, 6, and 7, the phase angle data processor 500 receives a single phase voltage V.sub.X through channel 504. The “X” subscripts in FIG. 5 are a generic representation for data processed by the respective phase angle data processors 316, 318, and 320. For example, the clock signal CLK_X represents the clock signal CLK_A for the phase angle data processor 316, the clock signal CLK_X represents the clock signal CLK_B for the phase angle data processor 318, and so on.

(25) The analog-to-digital converter 502 receives the sensed voltage V.sub.X, samples the sensed voltage V.sub.X at a sample rate f.sub.S.sub._.sub.X, and generates samples V.sub.x(n). “f.sub.S.sub._.sub.X” is a sub-multiple of the frequency of the clock signal CLK_X, and “n” is an integer index for the current sample. The processing block 506 performs, for example, general conditioning of the digital voltage sample V.sub.X(n) such as various filtering functions, as subsequently described, and generates a conditioned digital voltage sample V.sub.X(n)′. In operation 602, the phase angle data processor 500 receives a START command from master processor 322 (FIG. 3) or master processor 404 (FIG. 4). Since, in at least one embodiment, all the phase angle data processors 304, 306, and 308 receive the START command concurrently, the phase angle data process 600 begins at the same time for each of the phase angle data processors 304, 306, and 308. The START command initiates operation 604 to begin determination of phase sequence and phase angle data by the phase angle data processor 500, which occurs concurrently in the phase angle data processors 316, 318, and 320 (FIGS. 3 and 4). The digital comparator 508 determines a positive-to-negative transition of the voltage sample V.sub.X(n)′ at a zero crossing of the voltage sample V.sub.X(n)′ by comparing the voltage sample V.sub.X(n)′ with 0. When the voltage sample V.sub.X(n)′ falls below 0, the zero crossing value ZC.sub.X at the output of the comparator 508 transitions from a logical one to a logical 0 to indicate a positive-to-negative transition zero crossing such as the zero crossings ZC.sub.A, ZC.sub.B, and ZC.sub.C in FIG. 7. The comparator 508 is conceptual, and any digital technique can be used to determine when the voltage sample V.sub.X(n)′ reaches a zero crossing.

(26) The sample counter 510 begins counting the number of voltage samples V.sub.X(n)′ that occur from receipt of the START command until the zero crossing value ZC.sub.X indicates a positive-to-negative transition zero crossing. The sample counter 510 generates a sample count value N.sub.X that indicates the number of samples of voltage V.sub.X received by the phase angle data processor 500 from receipt of the START command until the positive-to-negative zero crossing ZC.sub.X occurred. In FIG. 7, N.sub.A represents the number of samples of phase A voltage V.sub.A from receipt of the START command, N.sub.B represents the number of samples of phase B voltage V.sub.B from receipt of the START command, and N.sub.C represents the number of samples of phase C voltage V.sub.C from receipt of the START command.

(27) In at least one embodiment, the START command is not synchronized with the clock signals CLK_A, CLK_B, or CLK_C, and the clock signals CLK_A, CLK_B, or CLK_C are not synchronized with each other, i.e. the clock signals CLK_A, CLK_B, or CLK_C are asynchronous and can have different respective frequencies f.sub.S.sub._.sub.A, f.sub.S.sub._.sub.B, and f.sub.S.sub._.sub.C. Circuits, such as the analog-to-digital converter 502 and the intra-sample counter 512, receive the clock signal CLK_X and may derive a separate sampling clock signal from the clock signal CLK_X that may have a higher or lower frequency. Thus, the START command may be received between pulses of any of the clock signals CLK_A, CLK_B, or CLK_C and between any sampling clock signals that are derived from the clock signals CLK_A, CLK_B, or CLK_C. FIG. 8 depicts an exemplary intra-sample START command 800. In at least one embodiment, the accuracy of the phase angle data depends on an accurate determination of the representation of time between when the START command is received and when the positive-to-negative zero crossing occurs. In at least one embodiment, the accuracy of the phase angle data depends on an accurate determination of the representation of time within a sample period that the START command is received. One way to increase the accuracy is to increase the sample rate frequency f.sub.S.sub._.sub.X. However, increasing the sample rate frequency f.sub.S.sub._.sub.X generally increases the cost of the IPDCs 304, 306, and 308. To maintain a lower sample rate frequency f.sub.S.sub._.sub.X, the intra-sample counter 512 receives the START command, the clock signal CLK_X, and a clock signal CLK_X.Math.M to generate an intra-sample count value NS.sub.X. “M” is a multiplier, and the particular value of M is a matter of design choice. Increasing the value of M increases the accuracy of the intra-sample count value NS.sub.X in representing the time between the last voltage sample V.sub.X(−1) before the first voltage sample V.sub.X(0) that occurs after the START command M is, for example 1/128. In at least one embodiment, the intra-sample counter 512 restarts the value of intra-sample count value NS.sub.X at each pulse of a sampling clock signal derived from the clock signal CLK_X. When the intra-sample counter 512 receives the START command, the intra-sample counter 512 generates the intra-sample count value NS.sub.X. Thus, the intra-sample counter 512 compensates for elapsed time that occurs between receipt of the START command and the next sample V.sub.X(0) of the voltage V.sub.X.

(28) The phase angle data processor 500 includes registers 514 that stores the values of V.sub.X(n). When the zero crossing value ZC.sub.X indicates a positive-to-negative zero crossing, the registers 514 provide the values of ZCD_OLD and ZCD_NEW to the interpolator 516. The interpolator compensates for elapsed time between the last sample of the voltage V.sub.X(n) and the zero crossing ZC.sub.X.

(29) FIG. 9 depicts exemplary voltage samples of the voltage V.sub.X before and after a zero crossing. More specifically, FIG. 9 depicts exemplary pre-zero crossing samples 902, 904, and 906 of the voltage V.sub.X as the voltage V.sub.X approaches the zero crossing ZC.sub.X and post-zero crossing samples 908, 910, and 912 of the voltage V.sub.X immediately after the voltage V.sub.X passed through the zero crossing ZC.sub.X. FIG. 10 depicts a zoomed view 1000 of the voltage V.sub.X from the pre-zero crossing sample 906 to the post zero crossing sample 908. The values of ZCD_OLD and ZCD_NEW respectively represent the values of the voltage V.sub.X at respective samples 906 and 908. In at least one embodiment, the sample rate frequency f.sub.S.sub._.sub.X is fast enough that the voltage V.sub.X between samples 906 and 908 is approximately linear. Accordingly, the time t.sub.e.sub._.sub.X between the zero crossing ZC.sub.X and the sample 908 is given by Equation 1:

(30) $\begin{array}{cc}{t}_{e\_X}=\frac{.Math.\mathrm{ZCD\_NEW}.Math.}{.Math.\mathrm{ZCD\_NEW}.Math.+.Math.\mathrm{ZCD\_OLD}.Math.}& \mathrm{Equation}1\end{array}$

(31) In at least one embodiment, rather than measuring the fundamental line frequency f.sub.L of the voltage V.sub.X and the sample rate frequency f.sub.S.sub._.sub.X, the phase angle data processor 500 determines a ratio, referred to as epsilon “ε”, of the line frequency f.sub.L to the sample rate frequency f.sub.S.sub._.sub.X as given by Equation 2:

(32) $\begin{array}{cc}{\mathrm{.Math.}}_X=\frac{f_L}{f_{S\_X}}& \mathrm{Equation}2\end{array}$

(33) To generate ε.sub.X, the epsilon generator 518 receives the positive-to-negative or, in another embodiment, a negative-to-positive, zero crossing value ZC.sub.X and the clock signal CLK_X and determines the number of pulses of the clock signal CLK_X that occur between two positive-to-negative zero crossing value ZC.sub.X indications. The two positive-to-negative zero crossing value ZC.sub.X indications represent one cycle of the line frequency f.sub.L, and, thus, a ratio of the number of samples in one cycle can be used to compute ε.

(34) Referring to FIG. 6, as each of the phase angle data processors 316, 318, and 320 reach a positive-to-negative transition zero crossing of respective voltages V.sub.A, V.sub.B, and V.sub.C, operations 606, 608, and 610 transition from NO to YES, and, in operation 612 provide their respective values of NS.sub.X, t.sub.e.sub._.sub.X, ε.sub.X, and N.sub.X to the master processor 322 (FIG. 3) or the master processor 404 (FIG. 4). In operation 614, the master processor 322 (FIG. 3) or the master processor 404 (FIG. 4) determines the phase angle deltas between at least two sets of the voltages V.sub.A, V.sub.B, and V.sub.C.

(35) FIG. 11 depicts master processor 1100, which represents one embodiment of the master processor 322 (FIG. 3) or the master processor 404 (FIG. 4). The master processor 1100 receives the respective values of NS.sub.X, t.sub.e.sub._.sub.X, ε.sub.X, and N.sub.X from each of the IPDCs 304, 306, and 308. The master processor 1100 determines the sequence of the phases from the order of the values of the sample count value N.sub.X from smallest to largest. As shown in exemplary waveforms 700, N.sub.A is smallest for the phase A voltage V.sub.A and largest for the phase C voltage V.sub.C. Thus, the phase sequence is V.sub.A, V.sub.B, V.sub.C.

(36) The master processor 1100 then determines angles ANGLE.sub.A, ANGLE.sub.B, and ANGLE.sub.C of each of the three phase voltages V.sub.A, V.sub.B, and V.sub.C from the START command to the respective positive-to-negative zero crossings ZC.sub.A, ZC.sub.B, and ZC.sub.C. In at least one embodiment, the master processor 1100 determines the value of each of the angles ANGLE.sub.A, ANGLE.sub.B, and ANGLE.sub.C in accordance with:

(37) $\begin{array}{cc}{\mathrm{ANGLE}}_X=\left\{\left[N_X-1-t_{e\_X}-\frac{N_{\mathrm{SX}}}{M}-\left\{PCD\right\}\right].Math.{\epsilon }_X.Math.360\right\}-\left\{PD\right\}& \mathrm{Equation}3\end{array}$
(N.sub.X−1) represents the number of samples of the voltage V.sub.X(n) from the START command to the positive-to-negative transition zero crossing ZC.sub.X. “N.sub.X−1” is used rather than “N.sub.X” because, in at least one embodiment, the last sample V.sub.X(N.sub.X)′ actually occurs immediately after the positive-to-negative transition zero crossing ZC.sub.X i.e. the zero crossing occurs in the same sample interval as the START command. t.sub.e.sub.X represents the interpolated time in terms of a fraction of a cycle of the clock signal CLK_X (or a fraction of a sampling clock signal derived from the clock signal CLK_X) between the last sample of the voltage V.sub.X(n)′ and the positive-to-negative transition zero crossing ZC.sub.X as set forth in Equation 1. NS.sub.X/M represents the fraction of a cycle of the clock signal CLK_X between the sample V.sub.X(−1) immediately preceding the START command and the first sample V.sub.X(0). ε.sub.X equals the ratio of the line frequency f.sub.L to the sample rate frequency f.sub.S.sub.X as set forth in Equation 2. PCD represents a phase compensation delay. The value of the PCD compensates for delays in the phase of the voltage V.sub.X due to, for example, parasitic impedances. In at least one embodiment, the PCD represents one or two cycles of the clock signal CLK_X or a sampling clock signal internally derived from the clock signal CLK_X by the analog-to-digital converter 502. The quantity

(38) $\left[N_X-1-t_{e\_X}-\frac{N_{SX}}{M}-\left\{PCD\right\}\right].Math.{\epsilon }_X$
is multiplied by 360, which represents the number of degrees in a full cycle of the voltage V.sub.X to give an angular fraction of the voltage V.sub.X that occurs between START command and the positive-to-negative transition zero crossing ZC.sub.X plus a processing delay PD. The processing delay PD represents the processing delay of the processing block 506. In at least one embodiment, the processing delay PD is determined in terms of ε as subsequently described with reference to FIG. 12. The master processor 1100 provides the determined phase angle data as the PHASE ANGLE DATA output.

(39) FIG. 12 depicts signal conditioning processing block 1200, which represents one embodiment of processing block 506. Processing block 1200 contains four successive well-known digital filter types to condition the digital voltage signal V.sub.X(n). The particular filter types are a matter of design choice and, in at least one embodiment, are comb filter 1202, anti-sinc filter 1204, high pass filter 1206, and zero-cross detection low pass filter 1208. The individual and aggregate processing delays attributable to the filters can be determined, for example, empirically or mathematically. In at least one embodiment, Equation 3 represents the processing delay PD due to the individual filters in the processing block 1200:
PD=COMB.sub.DELAY−ANTISINC.sub.DELAY−HPF.sub.DELAY+ZCD_LPF.sub.DELAY
COMB.sub.DELAY=539.4745.Math.ε−0.0085
ANTISINC.sub.DELAY=113.2172.Math.ε−0.0219
HPF.sub.DELAY=−28.006.Math.ε−0.7064
ZCD_LPF.sub.DELAY=2051.8.Math.ε+6.8
The values of the COMB.sub.DELAY, ANTISINC.sub.DELAY, HPF.sub.DELAY, and ZCD_LPF.sub.DELAY are exemplary and depend upon the particular implementation of the filters. In at least one embodiment, the processing delay PD can change with changes in the input line frequency as well as with changes to the clock signal CLK_X. Since e is a ratio of the sample rate frequency f.sub.S.sub.—X and the line frequency f.sub.L, ε maps an “error” in the clock signal CLK_X to an error in the line frequency f.sub.L and, thus, the foregoing estimates of the processing delay account for changes in the input line frequency as well as with changes to the clock signal CLK_X.

(40) Operation 614 then determines the phase angle deltas by subtracting the phase angles for each voltage V.sub.A, V.sub.B, and V.sub.C from each other in accordance with the phase sequence so that, in at least one embodiment, a trailing phase voltage is subtracted from a leading edge voltage. For example, in the embodiment of FIG. 7, voltage V.sub.A leads voltage V.sub.B, and voltage V.sub.B leads voltage V.sub.C. So the master processor 322 (FIG. 3) and the master processor 404 (FIG. 4) determine the DELTA ANGLE.sub.AB=ANGLE.sub.A−ANGLE.sub.B, DELTA ANGLE.sub.AC=ANGLE.sub.A−ANGLE.sub.C, and DELTA ANGLE.sub.BC=ANGLE.sub.B−ANGLE.sub.C. Experimental results indicate that the power measurement systems 302 (FIGS. 3) and 402 (FIG. 4) can achieve delta angle accuracies with an error of 0.1% or less.

(41) FIG. 13 depicts a power distribution system 1300 using shunt resistor sampling of the currents i.sub.A, i.sub.B, and i.sub.C in the three phase power system. The power measurement system 1302 can be configured in the same way as, for example, the power measurement system 302 (FIG. 3) or the power measurement system 402 with asynchronous, isolated IPDCs 1304, 1306, and 1308. The IPDCs 1304, 1306, and 1308 sample respective voltages across shunt resistors 1310, 1312, and 1314, which represent currents i.sub.A, i.sub.B, and i.sub.C. The power measurement system 1302 then determines the phase angle differences as discussed, for example, in connection with the phase angle data processor 500 (FIG. 5).

(42) FIG. 14 depicts a law of cosines based phase angle data processor 1400, which represents one embodiment of each of the phase angle data processors 316, 318, and 320. The phase angle data processor 1400 utilizes the law of cosines to determine the phase angle deltas between the phases of voltages V.sub.A, V.sub.B, and V.sub.C from FIGS. 3 and 4. In addition to sampling the voltage V.sub.X with analog-to-digital converter 504 and conditioning with processing block 506, analog-to-digital converter 1402 also samples voltage V.sub.XY. Voltage V.sub.XY represents a voltage between any two of the voltages V.sub.A, V.sub.B, and V.sub.C, such as V.sub.AB, V.sub.AC, and V.sub.BC. In at least one embodiment, the processing block 506A is identical to the processing block 506 and generates a conditioned output voltage V.sub.XY(n)′. The root mean square (RMS) calculator 1404 determines the root mean squares of the voltages V.sub.X(n)′ and V.sub.XY(n)′ for at least one period of the voltages as indicated by successive positive-to-negative or negative-to-positive zero crossings ZC.sub.X. The phase angle data processor 1406 then utilizes the law of cosines to determine at least two of the delta phase angles between phases A, B, and C of the respective voltages V.sub.A, V.sub.B, and V.sub.C.

(43) FIG. 15 depicts a conceptual three-phase relationship 1500 between the RMS voltage values of V.sub.A.sub._.sub.RMS, V.sub.B.sub._.sub.RMS, and V.sub.C.sub._.sub.RMS of respective voltages V.sub.A, V.sub.B, and V.sub.C. The angles Φ1, Φ2, and Φ3 represent the respective angles between the RMS voltage values of V.sub.A.sub._.sub.RMS, V.sub.B.sub._.sub.RMS, and V.sub.C.sub._.sub.RMS.

(44) Referring to FIGS. 14 and 15, the phase angle data processor 1400 calculates two of the phase angles Φ1, Φ2, and Φ3 in accordance with Equation 4:

(45) $\begin{array}{cc}{\Phi }_Z={\cos }^{-1}\left(\frac{V_X^2+V_Y^2-V_{\mathrm{XY}}^2}{2.Math.V_X.Math.V_Y}\right)& \mathrm{Equation}4\end{array}$
ΦZ represents any of Φ1, Φ2, and Φ3. For the calculation of Φ1, V.sub.X represents the voltage V.sub.A.sub._.sub.RMS, voltage V.sub.Y represents the voltage V.sub.C.sub._.sub.RMS, and V.sub.XY represents the voltage V.sub.AC.sub._.sub.RMS. For the calculation of Φ2, V.sub.X represents the voltage V.sub.C.sub.RMS, voltage V.sub.Y represents the voltage V.sub.B.sub._.sub.RMS, and V.sub.XY represents the voltage V.sub.BC.sub._.sub.RMS. The sum of the angles Φ1, Φ2, and Φ3 equal 360°, so calculation of two angles in accordance with Equation 4 allows the master processor 322 (FIG. 3) or master processor 404 (FIG. 4) to calculate the third angle by subtracting the two calculated angles from 360 or by calculating the third angle and verifying that all three angles add to 360.

(46) Thus, system and method utilize multiple, asynchronous, voltage isolated IPDCs to respectively determine one or more power parameters of a multi-phase power distribution system, such as differences between voltage phases of a multi-phase power distribution system.

(47) Although embodiments have been described in detail, it should be understood that various changes, substitutions, and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims. For example, the foregoing technique of using isolated, asynchronous circuits do determine the phase angle parameters of a three phase power distribution system utilizing a common START command can also be applied to determination of other parameters by the isolated, asynchronous circuits.