Arithmetic operation in a data processing system

Abstract

An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.

Claims

1. A method for performing an arithmetic operation in a data processing unit, the method comprising: the data processing unit iteratively computing an approximate result of the arithmetic operation; concurrently with the iteratively computing, the data processing unit computing at least two supplementary values of the approximate result of the arithmetic operation; and the data processing unit selecting a final result of the arithmetic operation from among a set including the approximate result and the at least two supplementary values depending on a result of a last iteration of the iteratively computing.

2. The method according to claim 1, wherein the arithmetic operation is an SRT (Sweeney, Robertson, and Tocher) computation process.

3. The method according to claim 1, wherein the arithmetic operation is a division operation.

4. The method according to claim 1, wherein the arithmetic operation is a square-root operation.

5. The method according to claim 1, wherein the arithmetic operation is one of an addition, a subtraction, or a multiplication operation.

6. The method according to claim 1, wherein: the iteratively computing the approximate result comprises iteratively computing an approximate result Q of the arithmetic operation by accumulating digit values q concatenated to a previous approximate result Q using a given radix r; computing at least two supplementary values comprises computing iteratively the at least two supplementary values of the approximate result, Q−1 and Q−2, by accumulating digit values q−1 and q−2, respectively, concatenated to previous supplementary values Q−1 and Q−2 using the given radix r; the method further comprises computing concurrently a remainder value P of the arithmetic operation; the selecting the final result comprises: in response to P being greater than or equal to zero and Q being greater than or equal to zero, selecting as the final result a value of Q for the last iteration; in response to P being less than zero and Q being greater than or equal to zero, selecting as the final result a value of Q−1 for the last iteration; in response to P being greater than or equal to zero and Q being less than zero, a negation of a value of Q−1 for the last iteration; and in response to P being less than zero and Q being less than zero, selecting as the final result a negation of a value of Q−2 for the last iteration.

7. The method according to claim 6, and further comprising selecting the digit values q from a lookup table.

8. The method according to claim 6, wherein an absolute value of the digit values q is less than the radix r.

9. The method according to claim 1, wherein selecting the final result comprises selecting the final result using a multiplexing unit having the approximate result and the at least two supplementary values as inputs.

10. The method according to claim 9, wherein the selecting the final result includes the multiplexing unit selecting the final result in response to at least two hardware lines indicating operand signs.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) The present invention together with the above-mentioned and other objects and advantages may best be understood from the following detailed description of the embodiments, but not restricted to the embodiments, wherein is shown in:

(2) FIG. 1 a generalized process flow of an SRT division process according to the state of the art;

(3) FIG. 2 an example embodiment of an SRT division process with extended carry-less digit-wise accumulation according to the invention;

(4) FIG. 3 an implementation with two data registers of an SRT division process according to the exemplary embodiment of FIG. 2;

(5) FIG. 4 depicts an exemplary embodiment according to FIG. 2 with three data registers;

(6) FIG. 5 depicts an exemplary embodiment according to FIG. 3 with only two data registers; and

(7) FIG. 6 depicts an exemplary embodiment of a data processing system for carrying out a method according to the invention.

DETAILED DESCRIPTION

(8) In the drawings, like elements are referred to with like reference numerals. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. Moreover, the drawings are intended to depict only typical embodiments of the invention and therefore should not be considered as limiting the scope of the invention.

(9) In FIG. 1 a generalized process flow of an SRT division process according to the state of the art is shown. The example depicts a fixed-point division process for determining a quotient Q as well as a remainder R by calculating a value A divided by a value B. First a pre-processing process 30 is done to determine the absolute values of both input values A and B. Then a normalizing process 32 takes place before the iterative SRT division process 34 starts with the absolute values |A| and |B|.

(10) Iterative algorithms such as an SRT division process can be described according to the following formulas for iterated quotient values Q.sub.i, which are expressed for the example of a fixed-point right aligned division process as:
∀i≧0,Q.sub.i+1=r*Q.sub.i+q.sub.i+1=Σ.sub.n=0.sup.i+1q.sub.n*r.sup.i+1−n,Q.sub.0=0,q.sub.0=0  (3)
and for the example of a floating point left aligned division process:
∀i≧0,Q.sub.i+1=Q.sub.i+q.sub.i+1*r.sup.−(i+1)=Σ.sub.n=0.sup.i+1q.sub.n*r.sup.−n,Q.sub.0=0,q.sub.0=0  (4)
where i is an iteration step, r a radix (usually 4, 8, 10 or 16), P.sub.i is a partial remainder, D a constant denominator and q.sub.i a guessed quotient digit value. Equation (4) thereby corresponds to the already shown equation (2) and exhibits a more detailed description.

(11) Quotient digit values q.sub.i can be determined according:
∀i≧0,q.sub.min≦q.sub.i≦q.sub.max  (5)
with usually, but not necessarily
−q.sub.min=q.sub.max<r
whereby the partial remainder value P.sub.i may be determined according already shown equation (1):
∀i≧0,P.sub.i+1=r*P.sub.i−q.sub.i+1*D  (1)

(12) After having the result of the division process 34 a denormalizing process 36 delivers absolute values of the last iteration step for a quotient |Q.sub.last| and a partial remainder |P.sub.last|. A final post-processing step 38 corrects and/or negates the result according to the signs of A and B, which are transferred from the pre-processing step 30, and delivers the final results for the quotient Q and the remainder R. One advantage of the invention is that the final post-processing step 38 may be eliminated because the determination of the final results Q and R can be selected directly from the last iteration step values.

(13) FIG. 2 shows an example embodiment of an SRT division process with extended carry-less digit-wise accumulation according to the invention. The iterative computation of the different quotient values Q, Q−1 and Q−2 specific for the innovative process is performed according to the following formulas.

(14) An iterative value for the guessed quotient value Q, is computed according equation (3), because a fixed point right aligned division process is described here:

(15) $\begin{array}{cc}\forall q_{i+1},Q_{i+1}=r*Q_i+q_{i+1}=\underset{n=0}{\overset{i+1}{.Math.}}{q}_n*r^{i+1-n}\{\begin{array}{cc}\forall q_{i+1}\ge 0,& Q_{i+1}=r*Q_i||q_{i+1}\\ \forall q_{i+1}<0,& Q_{i+1}=r*\left(Q_i-1\right)||\left(q_{i+1}+r\right)\end{array}& \left(3\right)\end{array}$
where the symbol ∥ characterizes a concatenation step with a left shift by log.sub.2(r) bits, e.g. for radix 4, a left shift by 2 bits.

(16) The quotient value Qi−1 is computed like this:

(17) $\begin{array}{cc}\forall q_{i+1},Q_{i+1}-1=r*Q_i+\left(q_{i+1}-1\right)=\underset{n=0}{\overset{i+1}{.Math.}}{q}_n*r^{i+1-n}-1\{\begin{array}{cc}\forall q_{i+1}\ge 1,& Q_{i+1}-1=r*Q_i||\left(q_{i+1}-1\right)\\ \forall q_{i+1}<1,& Q_{i+1}-1=r*\left(Q_i-1\right)||\left(q_{i+1}+r-1\right)\end{array}& \left(6\right)\end{array}$
whereas for the quotient values Q.sub.i−2 the following formula applies:

(18) $\begin{array}{cc}\forall q_{i+1},Q_{i+1}-2=r*Q_i+\left(q_{i+1}-2\right)=\underset{n=0}{\overset{i+1}{.Math.}}{q}_n*r^{i+1-n}-2\{\begin{array}{cc}\forall 2\le q_{i+1}<2+r,& Q_{i+1}-2-r*Q_i||\left(q_{i+1}-2\right)\\ \forall 2-r\le q_{i+1}<2,& Q_{i+1}-2=r*\left(Q_i-1\right)||\left(q_{i+1}+r-2\right)\\ \forall 2-2r\le q_{i+1}<2-r,& Q_{i+1}-2=r*\left(Q_i-2\right)||\left(q_{i+1}+2r-2\right)\end{array}& \left(7\right)\end{array}$

(19) In FIG. 2 mainly three data registers 50, 51, 52 are shown for the computation of the different quotient values Q, Q−1 and Q−2. For simplicity the indices of the different Q values are omitted in the description, where appropriate. The input to these registers 50, 51, 52 is done by appropriate multiplexing units 40, 41, 42, respectively. As the SRT process is a recursive process the output of the different registers 50, 51, 52 is fed back via data lines 63, 64, 65 to the input of the multiplexing units 40, 41, 42 in order to compute a new iteration step. Additionally Q−1 is an input to multiplexing unit 40 via data line 70, whereas Q is an input to multiplexing unit 41 via data line 71, and both Q and Q−1 are an input to multiplexing unit 42 via data lines 73 and 72, respectively. Additionally quotient digit values q, q+r, q−1, q+r−1, q−2, q+r−2, q+2r−2, which are results from guesses from a lookup table 20, are fed to multiplexing units 43, 44, 45 via data lines 74, 75, 76, 77, 78, 79, 80, respectively. The q values are stored in data registers 53, 54, 55 for starting a concatenating process. The selection of the appropriate values in the multiplexing units 40 to 45 is performed according to the formulas for the computation of Q, Q−1, Q−2 given above. In order to proceed the iteration process to the next step, for example, the q value form register 53 is concatenated with the output of register 50, i.e. left shifted by log.sub.2(2) bits via data line 60, and the result fed back as an input to multiplexing units 40, 41 42. Similarly the concatenation processes are performed with the other two register units 51 and 54 via data line 61 and 52 and 55 via data line 62. The results of the iteration process finally after the last iteration step are fed to multiplexing unit 46 via data lines 66 for Q and data lines 67 and 68 for Q−1. Data lines 68 and 69 delivers Q−1 and Q−2 to negated input ports of multiplexing unit 46. The final result of the quotient Q can then be determined by multiplexing unit 46 selecting from the results of the last iteration step according to the following formulas:
P.sub.last>0Q.sub.last>0,Q=Q.sub.last
P.sub.last>0Q.sub.last≧0,Q=(Q.sub.last−1)
P.sub.last>0Q.sub.last<0,Q=−(Q.sub.last)=(Q.sub.last−1)
P.sub.last>0Q.sub.last<0,Q=−(Q.sub.last)=(Q.sub.last−1)=(Q.sub.last−2)  (8)

(20) In case P is greater or equal to zero and Q is greater or equal zero, the last iterated value of Q will be selected. In case P is less than zero and Q is greater or equal zero, the last iterated value of Q−1 will be selected. In case P is greater or equal zero and Q is less than zero, the negated last iterated value of Q−1 will be selected; and in case P is less than zero and Q is less than zero, the negated last iterated value of Q−2 will be selected as the final result. In such a manner the final correction and/or negation steps of a usual SRT division process may be neglected, because the final result may be directly selected from already computed values Q, Q−1, or Q−2 of the last iteration step.

(21) Besides the inputs from the data lines 66 to 69 for Q, Q−1, −(Q−1), and −(Q−2), multiplexing unit 46 additionally has at least two hardware input lines 100 which feed an input signal for P.sub.last<0 and the exclusive-or input of sign(A)⊕sign(B), where A and B are the dividend and divisor of the SRT division process as defined above. The partial remainder values P are computed in a parallel process according to the formula given above. By this method the final result correction and/or negation step can be eliminated and can be replaced by a simple and fast selection step in the multiplexing unit 46.

(22) In FIG. 3 an implementation of an SRT division process according to the example embodiment of FIG. 2 is described. A further advantage of the described method is that only two data registers 50 and 52 are sufficient to handle the iteration process. The data register for the Q−1 computation may be eliminated because this value is available either in data register 50 from the last Q value or in data register 52 from the last Q−2 value respectively. Therefore, an additional data line 82 from data register 50 as well as an additional data line 84 from data register 52 are fed to a multiplexing unit 56 which selects the appropriate value Q−1 for input to the multiplexing unit 46. In this way, only two full data registers 50 and 52 are sufficient to cover the iteration process, in addition to the small register 54 with a bit length of log.sub.2(r) and an additional multiplexing unit 56, which is a very hardware-efficient implementation of such a process. For simplicity not all data lines are shown compared to FIG. 2, but all other functions are meant as described in FIG. 2.

(23) The embodiment shown in FIGS. 2 and 3 is the example of an SRT division process. Yet the method is not restricted to such a process, but instead is applicable to any iterative method for computation of a number with digit-wise accumulations, e.g., computation of square-roots or generally other processes including addition, subtraction, or multiplication.

(24) In FIG. 4 a numeric example of an embodiment according to FIG. 2 with three data registers is shown in order to explain the method in more detail with real numbers. Column 110 shows different q.sub.1+1 quotient digit values according to an implementation of the inventive method with an SRT division process with radix 4. As given above q.sub.1+1 may be determined according to −r<q.sub.1+1<r, which means that q.sub.i+1 can range from −3 to 3 (−3 is not used in the example shown). Column 111 shows a data register with the computed quotient values for Q, column 114 shows a data register for Q′=Q−1, and column 117 shows a data register for Q″=Q−2. The values are determined according to the equations
Q.sub.i+1=r*Q.sub.i+q.sub.i
Q′.sub.i+1=r*Q′.sub.i+q′.sub.i
Q″.sub.i+1=r*Q″.sub.i+q″.sub.i
where q′.sub.i+1=q.sub.i+1−1 and q″.sub.i+1=q.sub.i+1−2. The columns 112, 115, 118 represent the data registers with the values of q, q′, q″, respectively, in digits (indices are omitted). Columns 113, 116, 119 show the respective values of Q, Q′, Q″ in decimal representation. As a starting point, Q value 111 and q value 112 are set to zero. Then according to the first q.sub.i+1 value 110 of 2, a new set of quotient values are computed according to equation (9). Afterwards the iteration proceeds with the next q.sub.i+1 value 110 and so on, until an appropriate accuracy is achieved. In FIG. 4 the quotient values that are derived from the previous Q values 111 are boxed with a continuous line, whereas the quotient values that are derived from the previous Q′ values 114 are boxed with a dashed line.

(25) FIG. 5 shows the same numeric example of an embodiment with a preferred implementation according to FIG. 3 with only two data registers. In FIG. 5, the data register with the Q′ values 114 is omitted. As can be seen in the example the same result can be obtained with feeding the data registers for Q 111 and Q″ 117 with the appropriate value for Q′, which is available either in a previous Q 111 or a Q″ 117 data register. Only the two-bit data register 115 for the q′ values is needed for implementation of the described method. The same notation for continuous and dashed boxes as in FIG. 4 are employed, continuous lines for quotient values derived from previous Q values and dashed lines for quotient values derived from previous Q′ values. As can be seen in the end the same values for the quotient values may be obtained by this implementation.

(26) Referring now to FIG. 6, a schematic of an example of a data processing system 210 is shown. Data processing system 210 is only one example of a suitable data processing system and is not intended to suggest any limitation as to the scope of use or functionality of embodiments of the invention described herein. Regardless, data processing system 210 is capable of being implemented and/or performing any of the functionality set forth herein above.

(27) In data processing system 210 there is a computer system/server 212, which is operational with numerous other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments, and/or configurations that may be suitable for use with computer system/server 212 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and the like.

(28) Computer system/server 212 may be described in the general context of computer system executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, and so on that perform particular tasks or implement particular abstract data types. Computer system/server 212 may be practiced in distributed cloud computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

(29) As shown in FIG. 6, computer system/server 212 in data processing system 210 is shown in the form of a general-purpose computing device. The components of computer system/server 212 may include, but are not limited to, one or more processors or processing units 216, a system memory 228, and a bus 218 that couples various system components including system memory 228 to processor 216.

(30) Bus 218 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

(31) Computer system/server 212 typically includes a variety of computer system readable media. Such media may be any available media that is accessible by computer system/server 212, and it includes both volatile and non-volatile media, removable and non-removable media.

(32) System memory 228 can include computer system readable media in the form of volatile memory, such as random access memory (RAM) 230 and/or cache memory 232. Computer system/server 212 may further include other removable/non-removable, volatile/non-volatile computer system storage media. By way of example only, storage system 234 can be provided for reading from and writing to a non-removable, non-volatile magnetic media (not shown and typically called a “hard drive”). Although not shown, a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a “floppy disk”), and an optical disk drive for reading from or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM or other optical media can be provided. In such instances, each can be connected to bus 218 by one or more data media interfaces. As will be further depicted and described below, memory 228 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention.

(33) Program/utility 240, having a set (at least one) of program modules 242, may be stored in memory 228 by way of example, and not limitation, as well as an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data or some combination thereof, may include an implementation of a networking environment. Program modules 242 generally carry out the functions and/or methodologies of embodiments of the invention as described herein. Computer system/server 212 may also communicate with one or more external devices 214 such as a keyboard, a pointing device, a display 224, etc.; one or more devices that enable a user to interact with computer system/server 212; and/or any devices (e.g., network card, modem, etc.) that enable computer system/server 212 to communicate with one or more other computing devices. Such communication can occur via Input/Output (I10) interfaces 222. Still yet, computer system/server 212 can communicate with one or more networks such as a local area network (LAN), a general wide area network (WAN), and/or a public network (e.g., the Internet) via network adapter 220. As depicted, network adapter 220 communicates with the other components of computer system/server 212 via bus 218. It should be understood that although not shown, other hardware and/or software components could be used in conjunction with computer system/server 212. Examples, include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

(34) The block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical functions. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams, and combinations of blocks in the block diagrams, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.