Efficient power amplification over large operating average power range

Abstract

Embodiments of a Doherty power amplifier that maintain efficiency over a large operating average power range are disclosed. In one embodiment, the Doherty power amplifier includes reconfigurable main and auxiliary output matching networks and a fixed combining network. The reconfigurable main and auxiliary output matching networks can be reconfigured such that together the reconfigurable main output matching network, the reconfigurable auxiliary output matching network, and the fixed combining network provide proper load modulation for multiple different back-off power levels. As a result, the Doherty power amplifier maintains high efficiency over an extended back-off power level range.

Claims

1. A Doherty power amplifier comprising: a main power amplifier; an auxiliary power amplifier; a variable voltage source reconfigurable to apply a variable gate bias voltage to the auxiliary power amplifier for each of a plurality of average operating power levels for the Doherty power amplifier; and a reconfigurable main input matching network coupled to an input of the main power amplifier, wherein the reconfigurable main input matching network is reconfigurable for the plurality of average operating power levels for the Doherty power amplifier.

2. The Doherty power amplifier of claim 1 wherein each of the plurality of average operating power levels is based on an input power of an input signal provided to the Doherty power amplifier.

3. The Doherty power amplifier of claim 1 wherein the variable voltage source is dynamically reconfigured during operation based on an input power of an input signal provided to the Doherty power amplifier.

4. The Doherty power amplifier of claim 1 further comprising: a reconfigurable main output matching network coupled to an output of the main power amplifier; and a reconfigurable auxiliary output matching network coupled to an output of the auxiliary power amplifier; wherein each of the reconfigurable main output matching network and the reconfigurable auxiliary output matching network are reconfigurable for the plurality of average operating power levels for the Doherty power amplifier.

5. The Doherty power amplifier of claim 4 wherein each of the reconfigurable main output matching network and the reconfigurable auxiliary output matching network comprises a Microelectromechanical, MEM, switch and a respective capacitor bank to enable the reconfiguration of the reconfigurable main output matching network and the reconfigurable auxiliary output matching network by connecting to different capacitors comprised in each respective capacitor bank.

6. The Doherty power amplifier of claim 4 further comprising: a fixed combining network having a first input coupled to an output of the reconfigurable main output matching network and a second input coupled to an output of the reconfigurable auxiliary output matching network; wherein, for each average operating power level of the plurality of average operating power levels, the reconfigurable main output matching network and the reconfigurable auxiliary output matching network are reconfigurable such that a combination of the reconfigurable main output matching network, the reconfigurable auxiliary output matching network, and the fixed combining network is equivalent to an optimal combining network for the average operating power level.

7. The Doherty power amplifier of claim 1 wherein the reconfigurable main input matching network is reconfigurable to maintain phase balance between a main power amplifier branch comprising the main power amplifier and an auxiliary power amplifier branch comprising the auxiliary power amplifier for the plurality of average operating power levels for the Doherty power amplifier.

8. The Doherty power amplifier of claim 1 further comprising: a reconfigurable main output matching network coupled to an output of the main power amplifier; a reconfigurable auxiliary output matching network coupled to an output of the auxiliary power amplifier; and wherein a combination of the reconfigurable main output matching network, the reconfigurable auxiliary output matching network, and the reconfigurable main input matching network is reconfigurable for the plurality of average operating power levels for the Doherty power amplifier.

9. The Doherty power amplifier of claim 8 further comprising: a controller configured to adaptively configure the reconfigurable main output matching network, the reconfigurable auxiliary output matching network, the reconfigurable main input matching network, and the variable voltage source of the auxiliary power amplifier based on an input signal provided to the Doherty power amplifier.

10. The Doherty power amplifier of claim 1 wherein, for each average operating power level of the plurality of average operating power levels, the variable voltage source is reconfigurable to provide proper load modulation for the average operating power level.

11. A method of configuring a Doherty power amplifier comprising a main power amplifier, an auxiliary power amplifier, a variable voltage source reconfigurable to apply a plurality of variable gate bias voltages to the auxiliary power amplifier, and reconfigurable main input matching network coupled to an input of the main power amplifier, comprising: configuring the variable voltage source to apply one of the plurality of variable gate bias voltages for the auxiliary power amplifier for a selected one of a plurality of average operating power levels for the Doherty power amplifier; and configuring the reconfigurable main output matching network and the reconfigurable auxiliary output matching network for the selected one of the plurality of average operating power levels for the Doherty power amplifier.

12. The method of claim 11 further comprising: detecting an input power of an input signal provided to an input of the Doherty power amplifier; and selecting one of the plurality of average operating power levels based on the input power of the input signal to thereby provide the selected one of the plurality of average operating power levels for the Doherty power amplifier.

13. The method of claim 11 wherein the Doherty power amplifier further comprises a fixed combining network having a first input coupled to an output of the reconfigurable main output matching network and a second input coupled to an output of the reconfigurable auxiliary output matching network, and configuring the reconfigurable main output matching network and the reconfigurable auxiliary output matching network comprises: configuring the reconfigurable main output matching network and the reconfigurable auxiliary output matching network such that a combination of the reconfigurable main output matching network, the reconfigurable auxiliary output matching network, and the fixed combining network is equivalent to an optimal combining network for the selected one of the plurality of average operating power levels for the Doherty power amplifier.

14. The method of claim 11, wherein the Doherty power amplifier further comprises a reconfigurable main input matching network coupled to an input of the main power amplifier, the method further comprises: configuring the reconfigurable main input matching network for the selected one of the plurality of average operating power levels for the Doherty power amplifier.

15. The method of claim 14 further comprising configuring the reconfigurable main input matching network of the Doherty power amplifier to phase balance a main power amplifier branch and an auxiliary power amplifier branch of the Doherty power amplifier.

16. The method of claim 11 wherein configuring the variable voltage source to apply the one of the plurality of variable gate bias voltages for the auxiliary power amplifier of the Doherty power amplifier comprises configuring the variable voltage source to provide proper load modulation for the selected one of the plurality of average operating power levels for the Doherty power amplifier.

17. A Doherty power amplifier comprising: a main power amplifier; an auxiliary power amplifier; a variable voltage source reconfigurable to apply a variable gate bias voltage to the auxiliary power amplifier for each of a plurality of average operating power levels for the Doherty power amplifier; and a reconfigurable main output matching network coupled to an output of the main power amplifier where the reconfigurable main output matching network is reconfigurable for the plurality of average operating power levels for the Doherty power amplifier.

18. A Doherty power amplifier comprising: a main power amplifier; an auxiliary power amplifier; a variable voltage source reconfigurable to apply a variable gate bias voltage to the auxiliary power amplifier for each of a plurality of average operating power levels for the Doherty power amplifier; and a reconfigurable auxiliary output matching network coupled to an output of the auxiliary power amplifier where the reconfigurable auxiliary output matching network is reconfigurable for the plurality of average operating power levels for the Doherty power amplifier.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

(1) The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

(2) FIG. 1 illustrates a conventional Doherty power amplifier;

(3) FIG. 2 graphically illustrates drain efficiency versus average input power level for a Doherty power amplifier having an extended back-off power level according to one embodiment of the present disclosure as compared to that of the conventional Doherty power amplifier of FIG. 1 and that of a modified version of the conventional Doherty power amplifier of FIG. 1 having an equivalent back-off power level;

(4) FIG. 3 illustrates a Doherty power amplifier that maintains efficiency over a large average operating power level range according to one embodiment of the present disclosure;

(5) FIG. 4 graphically illustrates current profiles of the main and auxiliary power amplifiers of the Doherty power amplifier of FIG. 3 for different average input power levels according to one embodiment of the present disclosure;

(6) FIG. 5 illustrates an output impedance profile for the main amplifier of the Doherty power amplifier of FIG. 3 according to one embodiment of the present disclosure;

(7) FIGS. 6A and 6B graphically illustrate a process by which the main and auxiliary output matching networks of the Doherty power amplifier of FIG. 3 can be designed to provide proper load modulation for a number of different average input power levels according to one embodiment of the present disclosure;

(8) FIG. 7 illustrates an efficiency enhancement of the Doherty power amplifier of FIG. 3 according to one embodiment of the present disclosure;

(9) FIG. 8 is a flow chart that illustrates a process for dynamically configuring the Doherty power amplifier of FIG. 3 during operation according to one embodiment of the present disclosure; and

(10) FIG. 9 is a flow chart that illustrates a process for designing the Doherty power amplifier of FIG. 3 according to one embodiment of the present disclosure.

DETAILED DESCRIPTION

(11) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(12) Embodiments of a Doherty power amplifier that maintain efficiency over a large operating average power range are disclosed. However, before discussing these embodiments, a discussion of a conventional Doherty power amplifier 10, as illustrated in FIG. 1, is beneficial. The conventional Doherty power amplifier 10 includes an input power divider 12, a main power amplifier (PA) branch 14, an auxiliary power amplifier branch 16, and an output combining network 18 connected as shown. The input power divider 12 is illustrated as having an input 20, two outputs 22 and 24, and a resistor 26 connected between the two outputs 22 and 24. The main power amplifier branch 14 includes a main input matching network (IMN.sub.MAIN) 28 having an input 30 coupled to the first output 22 of the input power divider 12 and an output 32; a main power amplifier 34, which in this embodiment is a single transistor which may be referred to herein as a main transistor, having a control input 36 and an output 38; and a main output matching network (OMN.sub.MAIN) 40 having an input 42 coupled to the output 38 of the main power amplifier 34 and an output 44. In a similar manner, the auxiliary power amplifier branch 16 includes an auxiliary input matching network (IMN.sub.AUX) 46 having an input 48 coupled to the second output 24 of the input power divider 12 and an output 50; an auxiliary power amplifier 52, which in this embodiment is a single transistor which may be referred to herein as an auxiliary transistor, having a control input 54 and an output 56; and an auxiliary output matching network (OMN.sub.AUX) 58 having an input 60 coupled to the output 56 of the auxiliary power amplifier 52 and an output 62.

(13) The output combining network 18 includes a first impedance inverter 64, which in the illustrated embodiment is a quarter-wave transmission line, having a first terminal 66 coupled to the output 44 of the main output matching network (OMN.sub.MAIN) 40 and a second terminal 68; a second impedance inverter 70, which in the illustrated embodiment is a quarter-wave transmission line, having a first terminal 72 coupled to the output 62 of the auxiliary output matching network (OMN.sub.AUX) 58 and the second terminal 68 of the first impedance inverter 64 and a second terminal 74; and a resistor 76 having a first terminal 78 coupled to the second terminal 74 of the second impedance inverter 70 and a second terminal 80 coupled to ground.

(14) In the main power amplifier branch 14, the main power amplifier 34 is Class AB biased and matched to ensure peak efficiency at a predetermined ρ dB back-off that corresponds to a Peak-to-Average Power Ratio (PAPR) of the input signal (input voltage

(15) $V_{\mathrm{in}}=\frac{V_{\mathrm{in},\max }}{p})$
where ρ(dB)=20 log (p). In the auxiliary power amplifier branch 16, the auxiliary power amplifier 52 is Class C biased and starts conducting at

(16) $V_{\mathrm{in}}=\frac{V_{\mathrm{in},\max }}{p}.$
The conventional Doherty power amplifier 10, which is referred to herein as a reference Doherty power amplifier, is designed to maintain high efficiency for input power levels between a peak input power P.sub.in,max and a reference average power level

(17) $P_{\mathrm{in},\mathrm{avg}}^{\mathrm{ref}}=\frac{P_{\mathrm{in},\max }}{p^2}\left(\mathrm{Watts}\right),$
which is equivalent to P.sub.in,avg.sup.ref=P.sub.in,max−ρ when expressed in dBm. Circuit parameters R.sub.T and Z.sub.T1 of the conventional Doherty power amplifier 10 are given as follows:

(18) $\begin{array}{cc}{R}_T=R_T^{\mathrm{ref}}=R_{\mathrm{opt}}^{\mathrm{ref}},Z_{T1}=Z_{T1}^{\mathrm{ref}}=\frac{R_{\mathrm{opt}}^{\mathrm{ref}}}{\sqrt{p}}\mathrm{where}& \left(1\right)\\ R_{\mathrm{opt}}^{\mathrm{ref}}=\frac{V_{\mathrm{DS},\max }}{I_{l,\max }}& \left(2\right)\end{array}$
is selected to achieve a maximum voltage swing at the drain of the main power amplifier 34, which is Class AB biased, and V.sub.DS,max and I.sub.1,max represent a maximum drain bias of the main power amplifier 34 and a maximum drain current of the main power amplifier 34.

(19) As is well understood in the art, the conventional Doherty power amplifier 10 maintains high efficiency over a range of input power levels from P.sub.in,max to P.sub.in,max−ρ(dB) using load modulation of an impedance seen by the main power amplifier 34 as a function of the input signal that follows the expression below:

(20) $\begin{array}{cc}{Z}_{\mathrm{main}}^{\mathrm{ref}}=\{\begin{array}{cc}2R_T^{\mathrm{ref}}& 0\le V_{\mathrm{in}}\le \frac{V_{\mathrm{in},\max }}{p}\\ R_T^{\mathrm{ref}}\left(2-\frac{1}{1+\sigma }\right)& \frac{V_{\mathrm{in},\max }}{p}\le V_{\mathrm{in}}\le V_{\mathrm{in},\max }\end{array}\mathrm{where}& \left(3\right)\\ \sigma =\frac{V_{\mathrm{in}}}{V_{\mathrm{in},\max }}& \left(4\right)\end{array}$

(21) If the average input power of the input signal decreases as a result of, for example, network load change, the conventional Doherty power amplifier 10 will yield low average efficiency since load modulation is only maintained in the ρ(dB) back-off range (i.e., in the input power range from P.sub.in,max−ρ(dB) to P.sub.in,max). This efficiency degradation is illustrated in FIG. 2 by the curve labeled “Reference Doherty PA with Average Power=P.sub.in,avg.sup.ref.” To improve the average efficiency, when the average input power is lower than P.sub.in,avg.sup.ref, proper load modulation has to be maintained over an extended back-off power range. One conceivable way to do this is to design the conventional Doherty power amplifier 10 for an extended back-off power level (i.e., increasing the back-off power level from ρ to ρ+2γ). However, as also illustrated in FIG. 2, the conventional Doherty power amplifier 10 designed for the extended power back-off level of ρ+2γ has substantially lower efficiency than the conventional Doherty power amplifier 10 designed for the conventional back-off level of ρ for average input power levels greater than P.sub.in,avg.sup.ref.

(22) Embodiments of a Doherty power amplifier that maintains high efficiency over an extended back-off power level range are disclosed. As discussed below in detail, in one embodiment, the Doherty power amplifier effectively adapts the circuit parameters R.sub.T and Z.sub.T1 of the Doherty power amplifier as a function of an average input power of the input signal of the Doherty power amplifier. As illustrated in FIG. 2 by the curve labeled “Composite Doherty PA operating at Variable Average Power Levels,” the Doherty power amplifier yields high efficiency over the entire range from the extended power back-off level (P.sub.in,max−(ρ+nγ) where in the example of FIG. 2 n=2) to P.sub.in,max.

(23) In this regard, FIG. 3 illustrates a Doherty power amplifier 82 according to one embodiment of the present disclosure. The Doherty power amplifier 82 includes an input power divider 84, a main power amplifier (PA) branch 86, an auxiliary power amplifier branch 88, and a fixed combining network 90 connected as shown. The input power divider 84 is illustrated as having an input 92, two outputs 94 and 96, and a resistor 98 connected between the two outputs 94 and 96. The main power amplifier branch 86 includes a reconfigurable main input matching network (IMN.sub.MAIN) 100 having an input 102 coupled to the first output 94 of the input power divider 84 and an output 104; a main power amplifier 106, which in this embodiment is a single transistor which may be referred to herein as a main transistor, having a control input 108 and an output 110; and a reconfigurable main output matching network (OMN.sub.MAIN) 112 having an input 114 coupled to the output 110 of the main power amplifier 106 and an output 116. In addition, the main power amplifier branch 86 includes a bias circuit 118 that couples a drain bias voltage (V.sub.DS,MAIN) to the main power amplifier 106.

(24) The reconfigurable main input matching network (IMN.sub.MAIN) 100 includes transmission lines 120 and 122 and variable capacitance circuitry 124 connected as shown. In one embodiment, the transmission lines 120 and 122 are designed to provide proper input matching for the reference average input power level P.sub.in,avg.sup.ref. The variable capacitance circuitry 124 provides a variable capacitance to enable reconfiguration of the reconfigurable main input matching network (IMN.sub.MAIN) 100 to provide proper phase matching between the main and auxiliary power amplifier branches 86 and 88 for the average input power levels. In one embodiment, the variable capacitance circuitry 124 is implemented as a fixed capacitor bank and a Radio Frequency (RF) Microelectromechanical (MEM) switch, where the MEM switch is controlled to vary the capacitance of the variable capacitance circuitry 124 by connecting to different capacitors in the fixed capacitor bank.

(25) Similarly, the reconfigurable main output matching network (OMN.sub.MAIN) 112 includes transmission lines 126, 128, and 130 and variable capacitance circuitry 132 connected as shown. In one embodiment, the transmission lines 126 through 130 are designed to provide proper output matching for the reference average input power level P.sub.in,avg.sup.ref. The variable capacitance circuitry 132 provides a variable capacitance to enable reconfiguration of the reconfigurable main output matching network (OMN.sub.MAIN) 112. In one embodiment, the variable capacitance circuitry 132 is implemented as a fixed capacitor bank and a MEM switch, where the MEM switch is controlled to vary the capacitance of the variable capacitance circuitry 132 by connecting to different capacitors in the fixed capacitor bank. In this embodiment, the main power amplifier branch 86 also includes a harmonic tuning stub connected between the drain bias voltage V.sub.DS,MAIN and the transmission line 126 as shown.

(26) In a similar manner, the auxiliary power amplifier branch 88 includes a fixed auxiliary input matching network (IMN.sub.AUX) 134 having an input 136 coupled to the second output 96 of the input power divider 84 and an output 138; an auxiliary power amplifier 140, which in this embodiment is a single transistor which may be referred to herein as an auxiliary transistor, having a control input 142 and an output 144; and a reconfigurable auxiliary output matching network (OMN.sub.AUX) 146 having an input 148 coupled to the output 144 of the auxiliary power amplifier 140 and an output 150. In addition, the auxiliary power amplifier branch 88 includes a bias circuit 152 that couples a drain bias voltage (V.sub.DS,AUX) to the auxiliary power amplifier 140, and a variable voltage source 154 that provides a variable gate bias (V.sub.GS,AUX) to the control input 142, which in this case is a gate, of the auxiliary power amplifier 140. Preferably, the auxiliary power amplifier 140 is Class C biased, whereas the main power amplifier 106 is Class AB biased.

(27) The fixed auxiliary input matching network (IMN.sub.AUX) 134 includes a transmission line 156 connected as shown. The reconfigurable auxiliary output matching network (OMN.sub.AUX) 146 includes transmission lines 158, 160, and 162 and variable capacitance circuitry 164 connected as shown. In one embodiment, the transmission lines 158 through 162 are designed to provide proper output matching for the reference average input power level P.sub.in,avg.sup.ref. The variable capacitance circuitry 164 provides a variable capacitance to enable reconfiguration of the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146. In one embodiment, the variable capacitance circuitry 164 is implemented as a fixed capacitor bank and a MEM switch, where the MEM switch is controlled to vary the capacitance of the variable capacitance circuitry 164 by connecting to different capacitors in the fixed capacitor bank.

(28) The fixed combining network 90 includes a first impedance inverter 166, which in the illustrated embodiment is a quarter-wave transmission line, having a first terminal 168 coupled to the output 116 of the reconfigurable main output matching network (OMN.sub.MAIN) 112 and a second terminal 170; a second impedance inverter 172, which in the illustrated embodiment is a quarter-wave transmission line, having a first terminal 174 coupled to the output 150 of the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146 and the second terminal 170 of the first impedance inverter 166 and a second terminal 176; and a resistor 178 having a first terminal 180 coupled to the second terminal 176 of the second impedance inverter 172 and a second terminal 182 coupled to ground.

(29) Lastly, the Doherty power amplifier 82 includes a controller 184 that adaptively configures the reconfigurable main input matching network (IMN.sub.MAIN) 100, the reconfigurable main output matching network (OMN.sub.MAIN) 112, the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146, and the variable voltage source 154 (and thus the variable gate bias (V.sub.GS,AUX) of the auxiliary power amplifier 140) based on an input signal or, more particularly, an input power (P.sub.IN) of the input signal, provided to the Doherty power amplifier 82. The controller 184 is implemented in hardware (e.g., an Application Specific Integrated Circuit (ASIC)) or a combination of hardware and software (e.g., a processor such as a Central Processing Unit (CPU) that executes software including instructions to control the processor to perform a predetermined algorithm for adaptively configuring the reconfigurable main input matching network (IMN.sub.MAIN) 100, the reconfigurable main output matching network (OMN.sub.MAIN) 112, the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146, and the variable voltage source 154 based on an input signal or, more particularly, an input power (P.sub.IN) of the input signal).

(30) In order to maintain high efficiency over an extended range of back-off power levels, the reconfigurable main output matching network (OMN.sub.MAIN) 112 and the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146 are reconfigurable to provide proper load modulation for a number of back-off power levels P.sub.in,avg.sup.i=P.sub.in,max−(ρ+iγ)=P.sub.in,avg.sup.ref−iγ dB for i=0, 1, . . . , n, where n≧1 and, more preferably, n≧2. The average power reduction step γ corresponds to a reduction of the input signal V.sub.in by a ratio α, where γ(dB)=−20 log α. The ratio α is also referred to herein as a power reduction ratio. Specifically, circuit parameters R.sub.T and Z.sub.T1 for the fixed combining network 90 are fixed values designed, in this embodiment, to provide proper load modulation (and thus maximum efficiency) for the back-off power level P.sub.in,avg.sup.ref=P.sub.in,max−ρ dB, which is referred to herein as the reference back-off power level P.sub.in,avg.sup.ref=P.sub.in,avg.sup.0. Thus, the circuit parameters R.sub.T and Z.sub.T1 for the fixed combining network 90 are given by Equations (1) and (2) above. However, each back-off power level P.sub.in,avg.sup.i has corresponding optimal circuit parameters R.sub.opt.sup.i and Z.sub.opt.sup.i that provide proper load modulation for that back-off power level P.sub.in,avg.sup.i defined as:

(31) $\begin{array}{cc}{R}_{\mathrm{opt}}^i=\frac{R_{\mathrm{opt}}^{\mathrm{ref}}}{{\alpha }^i},Z_{\mathrm{opt}}^i=\frac{R_{\mathrm{opt}}^i}{\sqrt{p}}.& \left(5\right)\end{array}$

(32) For instance, using P.sub.in,avg.sup.1=P.sub.in,avg.sup.ref −γ as an example, the drain current (I.sub.1) of the main power amplifier 106 follows the input signal V.sub.in according to the equation:
I.sub.1=g.sub.mV.sub.in
assuming that the main power amplifier 106 has linear transconductance (g.sub.m). At the back-off power level of P.sub.in,avg.sup.1, the drain current (I.sub.1) of the main power amplifier 106 will be decreased by the ratio, or factor, α, hence I.sub.1=αI.sub.1,max. In this case, the auxiliary power amplifier 140 will be required to start conducting at a new threshold that is directly related to the back-off power level of P.sub.in,avg.sup.1. FIG. 4 demonstrates the desired current profiles for the main and auxiliary amplifiers 106 and 140 for proper load modulation at different operating power levels. In order to restore efficiency for the back-off power level of P.sub.in,avg.sup.1, the optimal load impedance to be seen by the main power amplifier 106 must vary from the reference value R.sub.opt.sup.ref to

(33) $\frac{R_{\mathrm{opt}}^{\mathrm{ref}}}{\alpha }.$

(34) Hence, based on Equation (5), proper load modulation is provided by, for each back-off power level P.sub.in,avg.sup.i, configuring the reconfigurable main output matching network (OMN.sub.MAIN) 112 and the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146 such that the combination of the reconfigurable main output matching network (OMN.sub.MAIN) 112, the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146, and the fixed combining network 90 provide the optimal load impedance to the main power amplifier 106. In other words, proper load modulation is provided by, for each back-off power level P.sub.in,avg.sup.i, configuring the reconfigurable main output matching network (OMN.sub.MAIN) 112 and the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146 such that the combination of the reconfigurable main output matching network (OMN.sub.MAIN) 112, the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146, and the fixed combining network 90 is equivalent to an optimal combining network for that back-off power level P.sub.in,avg.sup.i where R.sub.T=R.sub.opt.sup.i and Z.sub.T1=Z.sub.opt.sup.i. In addition, the variable voltage source 154 is controlled to provide the proper gate bias for the auxiliary power amplifier 140 to turn on at the appropriate input power level for the given back-off power level P.sub.in,avg.sup.i. The appropriate input power level at which the auxiliary power amplifier 140 turn on can be defined as:
V.sub.in=α.sup.iV.sub.in,ref=α.sup.i(V.sub.in,max/p).
As a result, the Doherty power amplifier 82 maintains high efficiency at an average back-off power level up to nγ dB greater than the average back-off power level (P.sub.in,avg.sup.ref=P.sub.in,max−ρ dB) of the conventional, or reference, Doherty power amplifier 10 of FIG. 1. Hence, a high drain efficiency of the Doherty power amplifier 82 is maintained over a wider range of back-off power levels.

(35) In addition to reconfiguring the reconfigurable main output matching network (OMN.sub.MAIN) 112, the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146, and the variable voltage source 154, the controller 184 also reconfigures the reconfigurable main input matching network (IMN.sub.MAIN) 100 to provide phase balancing between the main and auxiliary power amplifier branches 86 and 88. More specifically, the controller 184 reconfigures the reconfigurable main input matching network (IMN.sub.MAIN) 100 for each back-off power level to provide the proper phase correction for that back-off power level.

(36) FIG. 5 illustrates an impedance profile for the output impedance of the Doherty power amplifier 82 of FIG. 3 according to one embodiment of the present disclosure. As illustrated, by reconfiguring the reconfigurable main output matching network (OMN.sub.MAIN) 112 and the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146, the load impedance of the main power amplifier 106 is controlled to provide proper load modulation and, as a result, the Doherty power amplifier 82 maintains high efficiency over the extended back-off power level range. Specifically, reconfiguration of the main and auxiliary output matching networks (OMN.sub.MAIN and OMN.sub.AUX) 112 and 146 ensures proper main transistor impedance and current profiles as illustrated in FIGS. 3 and 4 and, consequently, proper load modulation. By providing proper load modulation, the Doherty power amplifier 82 maintains high efficiency over the extended back-off power level range.

(37) FIGS. 6A and 6B graphically illustrate a process for designing the reconfigurable main and auxiliary output matching networks (OMN.sub.MAIN and OMN.sub.AUX) 112 and 146 according to one embodiment of the present disclosure. In general, a set of close form equations allows the determination of ABCD parameters of the reconfigurable main and auxiliary output matching networks (OMN.sub.MAIN and OMN.sub.AUX) 112 and 146 given the reference value of the average input power (represented by p) and the desired power reduction ratio α that, in turn, determines the set of values of the optimal load impedance R.sub.opt.sup.i with respect to the reference load impedance R.sub.opt.sup.ref.Math.P.sub.in,avg.sup.ref=P.sub.in,avg.sup.0

(38) In this analysis, the set of R.sub.opt.sup.i values that correspond to the different back-off power levels P.sub.in,avg.sup.i is described in terms of R.sub.opt.sup.ref following Equation (5). Notably, the index i is an index of the back-off power level P.sub.in,avg.sup.i relative to the reference back-off power level P.sub.in,avg.sup.ref=P.sub.in,avg.sup.0. First, FIG. 6A is an illustration from which a number of expressions are derived to deduce the ABCD parameters of the reconfigurable main output matching network (OMN.sub.MAIN) 112 according to one embodiment of the present disclosure. In general, for low power levels, the cascade of the reconfigurable main output matching network (OMN.sub.MAIN) 112 and the fixed combining network 90 is designed to be equivalent to the optimal combining network for the given back-off power levels P.sub.in,avg.sup.i. More specifically, for low power levels, the auxiliary power amplifier 140 is off (i.e., is not conducting) such that the output impedance seen by the main power amplifier 106 is the cascade of the reconfigurable main output matching network (OMN.sub.MAIN) 112 and the fixed combining network 90. As such, for low power level compensation, the ABCD parameters for the optimal combining stage for the Doherty power amplifier 82 targeting the average power P.sub.in,avg.sup.i can be expressed, in terms of the index i, as follows:

(39) $\begin{array}{cc}\begin{array}{c}{\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{\mathrm{Low}\mathrm{Power}\mathrm{Combining}\mathrm{Stage}{P}_{\mathrm{in},\mathrm{avg}}^i}=\left[\begin{array}{cc}0& j{R}_{\mathrm{opt}}^i\\ \frac{-1}{j{R}_{\mathrm{opt}}^i}& 0\end{array}\right]\left[\begin{array}{cc}0& j\frac{R_{\mathrm{opt}}^i}{\sqrt{p}}\\ \frac{-\sqrt{p}}{j{R}_{\mathrm{opt}}^i}& 0\end{array}\right]\left[\begin{array}{cc}1& R_{\mathrm{opt}}^i\\ 0& 1\end{array}\right]\\ =\left[\begin{array}{cc}-\sqrt{p}& 0\\ 0& -\frac{1}{\sqrt{p}}\end{array}\right]\left[\begin{array}{cc}1& R_{\mathrm{opt}}^i\\ 0& 1\end{array}\right]\\ =\left[\begin{array}{cc}-\sqrt{p}& -\sqrt{p}{R}_{\mathrm{opt}}^i\\ 0& \frac{-1}{\sqrt{p}}\end{array}\right]\end{array}\mathrm{where}\left[\begin{array}{cc}0& j{R}_{\mathrm{opt}}^i\\ \frac{-1}{j{R}_{\mathrm{opt}}^i}& 0\end{array}\right]& \left(6\right)\end{array}$
is an ABCD matrix for the optimal impedance inverter (R.sub.T=R.sub.opt.sup.i, 90°),

(40) $\hspace{1em}\left[\begin{array}{cc}0& j\frac{R_{\mathrm{opt}}^i}{\sqrt{p}}\\ \frac{-\sqrt{p}}{j{R}_{\mathrm{opt}}^i}& 0\end{array}\right]$
is an ABCD matrix for the optimal impedance inverter (Z.sub.T1=Z.sub.opt.sup.i, 90°), and

(41) 0$\hspace{1em}\left[\begin{array}{cc}1& R_{\mathrm{opt}}^i\\ 0& 1\end{array}\right]$
is an ABCD matrix for the optimal resistance R.sub.T=R.sub.opt.sup.i for the optimal combining network for the back-off power levels P.sub.in,avg.sup.i.

(42) To maintain proper load modulation, the ABCD matrix of the cascade output stage, composed of the reconfigurable main output matching network (OMN.sub.MAIN) 112 and the fixed combining network 90, should be kept equal to those presented in Equation (6), which gives:

(43) $\begin{array}{cc}\left[\begin{array}{cc}-\sqrt{p}& -\sqrt{p}{R}_{\mathrm{opt}}^i\\ 0& \frac{-1}{\sqrt{p}}\end{array}\right]={\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{\mathrm{Main}\mathrm{OMN}}\left[\begin{array}{cc}-\sqrt{p}& -\sqrt{p}{R}_{\mathrm{opt}}^{\mathrm{ref}}\\ 0& \frac{-1}{\sqrt{p}}\end{array}\right]& \left(7\right)\\ \begin{array}{c}{\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{\mathrm{Main}\mathrm{OMN}}=\left[\begin{array}{cc}-\sqrt{p}& -\sqrt{p}{R}_{\mathrm{opt}}^i\\ 0& \frac{-1}{\sqrt{p}}\end{array}\right]\left[\begin{array}{cc}-\sqrt{p}& -\sqrt{p}{R}_{\mathrm{opt}}^{\mathrm{ref}}\\ 0& \frac{-1}{\sqrt{p}}\end{array}\right]\\ =\left[\begin{array}{cc}-\sqrt{p}& -\sqrt{p}{R}_{\mathrm{opt}}^i\\ 0& \frac{-1}{\sqrt{p}}\end{array}\right]\left[\begin{array}{cc}\frac{-1}{\sqrt{p}}& -\sqrt{p}{R}_{\mathrm{opt}}^{\mathrm{ref}}\\ 0& -\sqrt{p}\end{array}\right]\end{array}\mathrm{where}\left[\begin{array}{cc}-\sqrt{p}& -\sqrt{p}{R}_{\mathrm{opt}}^i\\ 0& \frac{-1}{\sqrt{p}}\end{array}\right]& \left(8\right)\end{array}$
is the ABCD matrix of the optimal combining network for the back-off power levels P.sub.in,avg.sup.i given by Equation (6) and

(44) $\hspace{1em}\left[\begin{array}{cc}-\sqrt{p}& -\sqrt{p}{R}_{\mathrm{opt}}^{\mathrm{ref}}\\ 0& \frac{-1}{\sqrt{p}}\end{array}\right]$
is an ABCD matrix for the fixed combining network 90.

(45) Hence, from Equation (8), one can deduce the circuit parameters of the reconfigurable main output matching network (OMN.sub.MAIN) 112 for the back-off power level P.sub.in,avg.sup.i using the following equation:

(46) $\begin{array}{cc}{\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{\mathrm{Main}\mathrm{OMN}}=\left[\begin{array}{cc}1& p\left[R_{\mathrm{opt}}^i-R_{\mathrm{opt}}^{\mathrm{ref}}\right]\\ 0& 1\end{array}\right]=\left[\begin{array}{cc}1& {\mathrm{pR}}_{\mathrm{opt}}^{\mathrm{ref}}\left[\frac{1}{{\alpha }^i}-1\right]\\ 0& 1\end{array}\right]& \left(9\right)\end{array}$

(47) Next, FIG. 6B is an illustration from which a number of expressions are derived to deduce the ABCD parameters of the reconfigurable auxiliary output matching network (OMN.sub.AUX) according to one embodiment of the present disclosure. In general, for high power levels (i.e., power levels at which the auxiliary power amplifier 140 is conducting), the combination of the reconfigurable main output matching network (OMN.sub.MAIN) 112, the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146, and the fixed combining network 90 is designed to be equivalent to the optimal combining network for the given back-off power levels P.sub.in,avg.sup.i. More specifically, at high power levels, the ABCD parameters for the optimal combining network for the Doherty power amplifier 82 targeting the average power P.sub.in,avg.sup.i, in terms of the index i, are as follows:

(48) $\begin{array}{cc}\begin{array}{c}{\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{\mathrm{High}\mathrm{Power}\mathrm{Combining}\mathrm{Stage}{P}_{\mathrm{in},\mathrm{avg}}^i}=\left[\begin{array}{cc}0& j{R}_{\mathrm{opt}}^i\\ \frac{-1}{j{R}_{\mathrm{opt}}^i}& 0\end{array}\right]\left[\begin{array}{cc}1& 0\\ \frac{p}{R_{\mathrm{opt}}^i}& 1\end{array}\right]\\ =\left[\begin{array}{cc}jp& j{R}_{\mathrm{opt}}^i\\ \frac{-1}{j{R}_{\mathrm{opt}}^i}& 0\end{array}\right]\end{array}\mathrm{where}\left[\begin{array}{cc}0& j{R}_{\mathrm{opt}}^i\\ \frac{-1}{j{R}_{\mathrm{opt}}^i}& 0\end{array}\right]& \left(10\right)\end{array}$
is an ABCD matrix for the optimal impedance inverter (R.sub.T=R.sub.opt.sup.i, 90°),

(49) $\hspace{1em}\left[\begin{array}{cc}1& 0\\ \frac{p}{R_{\mathrm{opt}}^i}& 1\end{array}\right]$
is an ABCD matrix for the combination of the optimal impedance inverter (R.sub.T=R.sup.i.sub.opt/√p,90°) and the load impedance R.sup.i.sub.opt (i.e., the branch including the vertical impedance inverter in FIG. 6B).

(50) To maintain proper load modulation, the ABCD matrix of the cascade output stage, composed of the reconfigurable main and auxiliary output matching networks (OMN.sub.MAIN and OMN.sub.AUX) 112 and 146 and the fixed combining network 90, should be kept equal to those presented in Equation (10) such that:

(51) $\begin{array}{cc}\left[\begin{array}{cc}jp& j{R}_{\mathrm{opt}}^i\\ \frac{-1}{j{R}_{\mathrm{opt}}^i}& 0\end{array}\right]={{\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{\mathrm{Main}\mathrm{OMN}}\left[\begin{array}{cc}jp& j{R}_{\mathrm{opt}}^{\mathrm{ref}}\\ \frac{-1}{j{R}_{\mathrm{opt}}^{\mathrm{ref}}}& 0\end{array}\right]\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{\mathrm{Aux}\mathrm{OMN}}& \left(11\right)\end{array}$
Substituting Equation (9) into Equation (11) yields:

(52) $\begin{array}{cc}\begin{array}{c}\left[\begin{array}{cc}jp& j{R}_{\mathrm{opt}}^i\\ \frac{-1}{j{R}_{\mathrm{opt}}^i}& 0\end{array}\right]={\left[\begin{array}{cc}1& p\left[R_{\mathrm{opt}}^i-R_{\mathrm{opt}}^{\mathrm{ref}}\right]\\ 0& 1\end{array}\right]\left[\begin{array}{cc}jp& j{R}_{\mathrm{opt}}^{\mathrm{ref}}\\ \frac{-1}{j{R}_{\mathrm{opt}}^{\mathrm{ref}}}& 0\end{array}\right]\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{\mathrm{Aux}\mathrm{OMN}}\\ ={\left[\begin{array}{cc}jp\left(\frac{R_{\mathrm{opt}}^i}{R_{\mathrm{opt}}^{\mathrm{ref}}}\right)& j{R}_{\mathrm{opt}}^{\mathrm{ref}}\\ \frac{-1}{j{R}_{\mathrm{opt}}^{\mathrm{ref}}}& 0\end{array}\right]\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{\mathrm{Aux}\mathrm{OMN}}\end{array}& \left(12\right)\end{array}$
Then, solving for the ABCD matrix for the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146 gives:

(53) $\begin{array}{cc}\begin{array}{c}{\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{\mathrm{Aux}\mathrm{OMN}}=\left[\begin{array}{cc}jp\left(\frac{R_{\mathrm{opt}}^i}{R_{\mathrm{opt}}^{\mathrm{ref}}}\right)& j{R}_{\mathrm{opt}}^{\mathrm{ref}}\\ \frac{-1}{j{R}_{\mathrm{opt}}^{\mathrm{ref}}}& 0\end{array}\right]\left[\begin{array}{cc}jp& j{R}_{\mathrm{opt}}^i\\ \frac{-1}{j{R}_{\mathrm{opt}}^i}& 0\end{array}\right]\\ =\left[\begin{array}{cc}0& -j{R}_{\mathrm{opt}}^{\mathrm{ref}}\\ \frac{1}{j{R}_{\mathrm{opt}}^{\mathrm{ref}}}& jp\left(\frac{R_{\mathrm{opt}}^i}{R_{\mathrm{opt}}^{\mathrm{ref}}}\right)\end{array}\right]\left[\begin{array}{cc}jp& j{R}_{\mathrm{opt}}^i\\ \frac{-1}{j{R}_{\mathrm{opt}}^i}& 0\end{array}\right]\end{array}& \left(13\right)\end{array}$
Hence, the circuit parameters for the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146 can be determined using the following equation:

(54) $\begin{array}{cc}\begin{array}{c}{\left[\begin{array}{cc}A& B\\ C& D\end{array}\right]}_{\mathrm{Aux}\mathrm{OMN}}=\left[\begin{array}{cc}\frac{R_{\mathrm{opt}}^{\mathrm{ref}}}{R_{\mathrm{opt}}^i}& 0\\ \frac{p}{R_{\mathrm{opt}}^{\mathrm{ref}}}-\frac{p}{R_{\mathrm{opt}}^i}& \frac{R_{\mathrm{opt}}^i}{R_{\mathrm{opt}}^{\mathrm{ref}}}\end{array}\right]\\ =\left[\begin{array}{cc}{\alpha }^{i-1}& 0\\ \frac{p}{R_{\mathrm{opt}}^{\mathrm{ref}}}\left[1-{\alpha }^i\right]& \frac{1}{{\alpha }^i}\end{array}\right]\end{array}& \left(14\right)\end{array}$
Equations (9) and (14) are closed form equations for obtaining the circuit parameters for the reconfigurable main output matching network (OMN.sub.MAIN) 112 and the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146, respectively, to maintain proper load modulation for each back-off power level P.sub.in,avg.sup.i (for i=0, 1, . . . , n). The circuit parameters are represented by the corresponding power decrement 1/α.sup.i corresponding to the back-off power level P.sub.in,avg.sup.i, the reference average power level (p), and the reference optimal load resistance (R.sub.opt.sup.ref).

(55) FIG. 7 graphically illustrates drain efficiency improvement of one embodiment of the Doherty power amplifier 82 of FIG. 3. As illustrated, in this example, the reference back-off power level is approximately 21 decibel-milliwatts (dBm), the first extended back-off power level is approximately 16 dBm, and the second extended back-off power level is approximately 11 dBm. At the first extended back-off power level, the Doherty power amplifier 82 has a 24% drain efficiency improvement over the conventional, or reference, Doherty power amplifier 10 of FIG. 1. At the second extended back-off power level, the Doherty power amplifier 82 has a 39% drain efficiency improvement over the conventional, or reference, Doherty power amplifier 10.

(56) FIG. 8 is a flow chart that illustrates the operation of the controller 184 to dynamically configure the Doherty power amplifier 82 according to one embodiment of the present disclosure. First, the controller 184 detects an average input power of the input signal V.sub.in of the Doherty power amplifier 82 (step 1000). Next, the controller 184 selects an appropriate average input power level P.sub.in,avg.sup.i based on the detected average input power of the input signal V.sub.in (step 1002). More specifically, if the average input power of the input signal V.sub.in is less than P.sub.in,avg.sup.n, then the controller 184 selects P.sub.in,avg.sup.n as the appropriate average input power level. Otherwise, the controller 184 selects the highest average input power level P.sub.in,avg.sup.i that is less than or equal to the average input power of the input signal V.sub.in. The selection of the appropriate average input power level (P.sub.in,avg.sup.selected) can be expressed as: if P.sub.in,avg<P.sub.in,avg.sup.n, then P.sub.in,avg.sup.selected=P.sub.in,avg.sup.n, and otherwise, if P.sub.in,avg≧P.sub.in,avg.sup.n, then P.sub.in,avg.sup.selected=max(P.sub.in,avg.sup.i) that is ≦P.sub.in,avg.

(57) Once the appropriate average input power level is selected, the controller 184 configures the Doherty power amplifier 82 according to the selected average input power level (step 1004). More specifically, the controller 184 configures the reconfigurable main output matching network (OMN.sub.MAIN) 112 and the reconfigurable auxiliary output matching network (OMN.sub.AUX) 146 to provide proper load modulation for the selected average input power level, as described above. In addition, the controller 184 configures the variable voltage source 154 to provide the proper gate bias to the auxiliary power amplifier 140 for the selected average input power level. Still further, the controller 184 configures the reconfigurable main input matching network (IMN.sub.MAIN) 100 to provide phase balancing between the main and auxiliary power amplifier branches 86 and 88 for the selected average input power level. The process then repeats such that the controller 184 dynamically reconfigures the Doherty power amplifier 82 based on the average input power of the input signal V.sub.in. In this manner, the Doherty power amplifier 82 maintains high efficiency over the entire back-off power level range from P.sub.in,avg.sup.n to P.sub.in,max.

(58) FIG. 9 is a flow chart that illustrates a process for designing the Doherty power amplifier 82 according to one embodiment of the present disclosure. First, a desired set of average input power levels P.sub.in,avg.sup.i for i=1, 2, . . . , n are selected, and corresponding α.sup.i values are deduced (step 2000). Next, the optimal load resistance R.sub.opt.sup.i for each average input power level P.sub.in,avg.sup.i is deduced (step 2002). Next, the proper gate bias voltage for the auxiliary power amplifier 140 is determined for each average input power level P.sub.in,avg.sup.i (step 2004). The reconfigurable main and auxiliary output matching networks (OMN.sub.MAIN and OMN.sub.AUX) 112 and 146 are then designed according to Equations (9) and (14) to thereby account for the variations of the optimal values of R.sub.T and Z.sub.T1 for the average input power levels P.sub.in,avg.sup.i (step 2006). Note that while Equations (9) and (14) represent one preferred embodiment for determining the circuit parameters for the reconfigurable main and auxiliary output matching networks (OMN.sub.MAIN and OMN.sub.AUX) 112 and 146, the present disclosure is not limited thereto. Lastly, the reconfigurable main input matching network (IMN.sub.MAIN) is designed to maintain the phase balance between the main and auxiliary power amplifier branches 86 and 88 for the different average input power levels P.sub.in,avg.sup.i (step 2008).

(59) While not being limited by or to any particular advantage, the Doherty power amplifier 82 disclosed herein has several advantages. As one example, in one implementation, the Doherty power amplifier 82 employs a minimum number of electronically tunable devices (i.e., the RF MEMS switches). As another example, the Doherty power amplifier 82 uses a fixed, or non-configurable, combining network 90, which enhances power handling capabilities and reduces the size of the tunable part of the power amplifier circuitry. This is particularly beneficial when the Doherty power amplifier 82 is implemented using integrated circuitry technologies. For example, in one embodiment, the reconfigurable input and output matching networks 100, 112, and 146 are implemented together with the main and auxiliary power amplifiers 106 and 140 in an integrated circuit. By implementing the tunable part of the Doherty power amplifier 82 on the integrated circuit rather than in the fixed combining network 90, the size of the fixed combining network 90 is substantially reduced.

(60) The following acronyms are used throughout this disclosure.

(61) TABLE-US-00001 ASIC Application Specific Integrated Circuit dB Decibel dBm Decibel-Milliwatt CPU Central Processing Unit MEM Microelectromechanical PA Power Amplifier PAPR Peak-to-Average Power Ratio RF Radio Frequency

(62) Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.