Compensation circuit, commutation cell and power converter controlling turn-on and turn-off of a power electronic switch

Abstract

The present disclosure relates to a compensation circuit for independently controlling turn-on and turn-off of a power electronic switch through a gate driver. The compensation circuit includes a circuit path sampling a first portion of a voltage induced across an inductance of the power electronic switch at turn-on. Another circuit path samples a second portion of the voltage induced across the inductance of the power electronic switch at turn-off. The compensation circuit further includes a gate driver reference connection configured to respectively supply the sampled portions of the voltage during turn-on and turn-off of the power electronic switch. A compensation circuit controlling a first power electronic switch in parallel with a second power electronic switch, a commutation cell and a power converter having a pair of parallel legs, in which each power electronic switch is provided with the compensation circuit, are also disclosed.

Claims

1. A compensation circuit for independently controlling turn-on and turn-off of a power electronic switch through a gate driver having a gate driver reference connection the compensation circuit comprising: a first circuit path configured to sample a first portion of a voltage induced across an inductance of the power electronic switch at turn-on of the power electronic switch, the first circuit path including first and second resistors connected in series and across the inductance, and a turn-on diode connected between a junction of the first and second resistors and the gate driver reference connection the turn-on diode being non-conductive during turn-off; and a second circuit path configured to sample a second portion of the voltage induced across the inductance of the power electronic switch at turn-off of the power electronic switch, the second circuit path including third and fourth resistors connected in series and across the inductance and a turn-off diode connected between a junction of the third and fourth resistors and the gate driver reference connection the turn-off diode being non-conductive during turn-on, wherein the gate driver reference connection is configured to respectively supply the first and second portions of the voltage during turn-on and turn-off of the power electronic switch.

2. The compensation circuit of claim 1, wherein the inductance is a parasitic inductance of the power electronic switch.

3. A compensation circuit for independently controlling turn-on and turn-off of a first power electronic switch that is placed in parallel with a second power electronic switch, the control being done through a gate driver having a gate driver reference connection the compensation circuit comprising: a first circuit path configured to sample a first portion of a voltage induced across an inductance of the first power electronic switch at turn-on of the first power electronic switch, the first circuit path including first and second resistors connected in series and across the inductance, and a turn-on diode connected between a junction of the first and second resistors and the gate driver reference connection the turn-on diode being non-conductive during turn-off; and a second circuit path configured to sample a second portion of the voltage induced across the inductance of the first power electronic switch at turn-off of the first power electronic switch, the second circuit path including third and fourth resistors connected in series and across the inductance, and a turn-off diode connected between a junction of the third and fourth resistors and the gate driver reference connection, the turn-off diode being non-conductive during turn-on wherein the gate driver reference connection is configured to respectively supply the first and second portions of the voltage during turn-on and turn-off of the first power electronic switch.

4. The compensation circuit of claim 3, wherein the inductance is a parasitic inductance of the first power electronic switch.

5. A commutation cell configured for limiting switching overvoltage, comprising: a power electronic switch having a parasitic inductance through which a voltage is generated upon turning on and off of the power electronic switch; and a compensation circuit for independently controlling turn-on and turn-off of the power electronic switch through a gate driver having a reference connection, the compensation circuit comprising: a first circuit path configured to sample a first portion of a voltage induced across an inductance of the power electronic switch at turn-on of the power electronic switch the first circuit path including first and second resistors connected in series and across the inductance and a turn-on diode connected between a junction of the first and second resistors and the gate driver reference connection the turn-on diode being non-conductive during turn-off; and a second circuit path configured to sample a second portion of the voltage induced across the inductance of the power electronic switch at turn-off of the power electronic switch the second circuit path including third and fourth resistors connected in series and across the inductance and a turn-off diode connected between a junction of the third and fourth resistors and the gate driver reference connection the turn-off diode being non-conductive during turn-on, wherein the gate driver reference connection configured to respectively supply the first and second portions of the voltage during turn-on and turn-off of the power electronic switch, and wherein the compensation circuit is connected to the parasitic inductance.

6. The commutation cell of claim 5, wherein the compensation circuit applies samples of the voltage generated through the parasitic inductance using different gains at turn-on and at turn-off of the power electronic switch.

7. The commutation cell of claim 5, wherein the power electronic switch is selected from an isolated gate bipolar transistor a metal-oxide-semiconductor field-effect transistor and a bipolar transistor.

8. The commutation cell of claim 5, comprising a freewheel diode operating in tandem with the power electronic switch.

9. The commutation cell of claim 5, wherein the gate driver is connected to the compensation circuit at the gate driver reference connection and wherein the gate driver is also connected to a gate of the power electronic switch the gate driver controlling a gate to emitter voltage applied to the power electronic switch.

10. The commutation cell of claim 9, comprising a turn-on resistor and a turn-off resistor separately connecting the gate driver to the gate of the power electronic switch.

11. The commutation cell of claim 9, wherein the parasitic inductance is a parasitic emitter inductance.

12. The commutation cell of claim 9, wherein the power electronic switch is placed in parallel with another power electronic switch.

13. The commutation cell of claim 5, wherein the parasitic inductance is a parasitic emitter inductance.

14. The commutation cell of claim 5, wherein the power electronic switch is placed in parallel with another power electronic switch.

15. A power converter, comprising: a pair of parallel legs, each leg having a pair of power electronic switches connected in series, each power electronic switch being provided with a compensation circuit for independently controlling turn-on and turn-off of each power electronic switch each compensation circuit comprising: a first circuit path configured to sample a first portion of a voltage induced across an inductance of the power electronic switch at turn-on of the power electronic switch the first circuit path including first and second resistors connected in series and across the inductance and a turn-on diode connected between a junction of the first and second resistors and a gate driver reference connection the turn-on diode being non-conductive during turn-off; and a second circuit path configured to sample a second portion of the voltage induced across the inductance of the power electronic switch at turn-off of the power electronic switch the second circuit path including third and fourth resistors connected in series and across the inductance, and a turn-off diode connected between a junction of the third and fourth resistors and the gate driver reference connection, the turn-off diode being non-conductive during turn-on; and a gate driver having the gate driver reference connection configured to respectively supply the first and second portions of the voltage during turn-on and turn-off of the power electronic switch.

16. The power converter of claim 15, wherein each of the compensation circuits is configured to control turn-on and turn-off of a corresponding power electronic switch.

17. The power converter of claim 15, wherein the compensation circuit is connected to a parasitic inductance.

18. The power converter of claim 15, wherein each pair of parallelized power electronic switches are selected from a same manufacturing batch.

19. The power converter of claim 15, wherein all power electronic switches are selected from a same manufacturing batch.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the disclosure will be described by way of example only with reference to the accompanying drawings, in which:

(2) FIG. 1 is an idealized circuit diagram of a conventional commutation cell such as those used in conventional power converter circuits;

(3) FIG. 2 is another circuit diagram of the conventional commutation cell of FIG. 1 showing parasitic (stray) inductances;

(4) FIG. 3 is a circuit diagram of a conventional commutation cell further showing a gate driver;

(5) FIG. 4 is a circuit diagram of a conventional IGBT leg formed of two conventional commutation cells;

(6) FIG. 5 is a circuit diagram of a power converter including two parallelized IGBT legs;

(7) FIG. 6 is a detailed view of a portion of FIG. 5 illustrating a compensation circuit according to a first illustrative embodiment; and

(8) FIG. 7 is a detailed view of a portion of FIG. 5 illustrating a compensation circuit according to a second illustrative embodiment.

(9) Like numerals represent like features on the various drawings.

DETAILED DESCRIPTION

(10) Various aspects of the present disclosure generally address one or more of the problems related to variable characteristics of power electronic switches.

(11) Circuits operable to limit overvoltage in commutation cells, especially at turn-off of IGBTs, are described in international patent publication no WO 2013/082705 A1, in international patent application no PCT/CA2013/000805, in U.S. provisional applications No. 61/808,254, No. 61/898,502, No. 61/904,038, No. 61/905,045, and No. 61/904,050, and in “Reducing switching losses and increasing IGBT drive efficiency with Reflex™ gate driver technology”, available at http://www.advbe.com/docs/DeciElec2013-Jean Marc Cyr-TM4.pdf, all of which are authored by Jean-Marc Cyr et al. the disclosure of these being incorporated by reference herein.

(12) The present technology provides control of overvoltage and switching losses at turn-off and turn-on of a power electronic switch of a commutation cell. Circuits and methods presented herein are generally compatible with other solutions to limit overvoltage at turn-off and/or turn-on of parallelized power electronic switches. Without limitation, the disclosed technology may be used in a single commutation cell, in a leg having two (2) cascaded commutation cells, and in parallelized legs.

(13) In a commutation cell, di/dt at turn-off of a power electronic switch generates a voltage across parasitic (stray) inductances of a high frequency loop of the commutation cell. This voltage is applied across the power electronic switch in addition to a bus voltage providing power to the commutation cell. A solution based on the injection of a sample of the overvoltage present across the power electronic switch to a gate driver of the power electronic switch has been proposed. A commutation cell built according to the present disclosure comprises a pair of circuit paths that respectively select a different portion of a voltage induced across an inductance of a power electronic switch at turn-on and at turn-off of the power electronic switch so that these portions are selectively applied to control the turn-on and turn-off of the power electronic switch.

(14) The techniques disclosed herein will mainly be described in relation to power converters including pairs of commutation cells forming IGBT legs, a pair of IGBT legs being further placed in parallel for high power applications. The same teachings are however applicable to single commutation cells or to single IGBT legs. Additionally, the following description will mainly relate to the use of isolated gate bipolar transistors (IGBT). Mentions of IGBTs in the following description are made for illustration purposes and are not meant to limit the present disclosure. The same techniques may equally be applied to commutation cells constructed using metal-oxide-semiconductor field-effect transistors (MOSFET), bipolar transistors and like power electronic switches.

(15) Generally stated, the disclosed compensation circuit facilitates parallel operation of power electronic switches described herein by the reduction of dynamic unbalance between parallelized power electronic switches having distinct characteristics. This is accomplished by balancing the switched currents at turn-on and turn-off. A compensation circuit is provided to inject a feedback of a drop voltage across the parasitic inductance of the high frequency loop of each individual power electronic switch to its respective gate driver circuit. This allows to selectively adjust the speed at turn-on and turn-off of the parallelized switches. This compensation circuit separately adjusts the current variation (di/dt) in the commutation cell by dynamically decreasing a voltage applied at the gate of the power electronic switch during the turn-on and by increasing it during turn-off. Of course, the disclosed compensation circuit may be used in single power electronic switch configurations, or in single leg configurations as it offers an alternative solution to the general problem of overvoltage control during switching.

(16) FIG. 5 is a circuit diagram of a power converter including two parallelized IGBT legs. FIG. 5 also illustrates the parasitic inductances caused by the components interconnections as well as individual feedback loops to the gate driver of each power electronic switch. In the example of FIG. 5 the two legs could be constructed from discrete parts or from switches of a same module or of different modules. In the context of the present disclosure, a ‘module’ is a package containing chips including several IGBTs and diodes made from a common wafer. The two parallelized switches could be also discrete parts to be parallelized to increase the available phase current at the output.

(17) The first leg 100 includes a bottom IGBT Q.sub.1, its associated freewheel diode D.sub.2 and parasite inductances L.sub.c1-low and L.sub.e1-low, as well as a top IGBT Q.sub.2, its associated diode freewheel D.sub.1 and parasite inductances L.sub.c2-high and L.sub.e2-high. First and second gate drivers G.sub.D1 and G.sub.D2 are respectively associated with the gate of the bottom and top IGBTs Q.sub.1 and Q.sub.2. The gate drivers G.sub.D1 and G.sub.D2 receive signals from a controller (not shown) and turn-on or off their connected IGBTs Q.sub.1 and Q.sub.2. Gate driver references (return path) of each gate driver G.sub.D1 and G.sub.D2 are respectively connected to compensation circuits 112 and 114 that are also connected across the parasitic emitter inductances L.sub.e1-low and L.sub.e2-high of their respective IGBTs Q.sub.1 and Q.sub.2.

(18) A second leg 200 includes bottom and top IGBTs Q.sub.3 and Q.sub.4 and corresponding freewheel diodes D.sub.3 and D.sub.4. Both top IGBTs Q.sub.2 and Q.sub.4 are turned on in parallel (at the same time) by respective gate drivers G.sub.D2 and G.sub.D4, connected to respective compensation circuits 114 and 118, to provide current from a positive V.sub.bus tab to a load connected to a port 300, the load being for example one phase of a three-phase motor. Both top IGBTs Q.sub.2 and Q.sub.4 are turned off in parallel while both bottom IGBTs Q.sub.1 and Q.sub.3 are turned on by respective gate drivers G.sub.D1 and G.sub.D3 to provide current path from the load to the negative V.sub.bus tab.

(19) The second leg 200 is identical to the first leg 100 and will not be further described herein. It may be observed that additional legs may be used in parallel to the first and second legs 100 and 200, if it is desired to provide even more power to the load connected to the port 300. A number of parallel legs will be selected according to the power requirements of the load and according to the power ratings of the IGBTs in the power converter.

(20) When the IGBTs Q.sub.2 and Q.sub.4 are turned on or off, the rate of change of current (di/dt) is higher in the one of the legs 100 or 200 that has a lower total parasitic inductance, assuming that the respective gate circuits of the IGBTs Q.sub.2 and Q.sub.4 provide similar timing in terms of minimal delay and like gate circuit parameters. For example, if a sum of L.sub.e1-low+L.sub.c1-low+L.sub.e2-high+L.sub.c2-high is lower than a sum of L.sub.e3-low+L.sub.c3-low+L.sub.e4-high+L.sub.c4-high, the lower total inductance in the leg 100 opposes less resistance to the di/dt. In that case, the IGBT Q.sub.2 commutates higher current than the IGBT Q.sub.4, therefore dissipating more losses at turn-on. In such a case the IGBT Q.sub.2 may be expected to suffer from higher thermal stress than the IGBT Q.sub.4.

(21) When the IGBT Q.sub.2 and Q.sub.4 are turned off, they must be able to withstand the overvoltage created by the di/dt across the various parasitic inductances, including L.sub.−Vbus, L.sub.e1-low, L.sub.c1-low, L.sub.e2-high, L.sub.c2-high and L.sub.+Vbus for Q.sub.2 and L.sub.−Vbus, L.sub.e3-low, L.sub.c3-low, L.sub.e4-high, L.sub.c4-high and L.sub.+Vbus for Q.sub.4 that are respectively present in legs 100 and 200 of the power converter. Indeed, since the inductances resist change of current therein, additive voltages develop in the circuit of each leg 100 and 200. For reliability reasons these voltages added to the voltage between the positive and negative V.sub.bus tabs must be kept below the maximum rating voltage of each IGBT. Different turn-off di/dt between the IGBTs Q.sub.2 and Q.sub.4 creates different voltage overshoots as well as unbalance in turn-off losses.

(22) Generally stated, by adding a compensation circuit connected to the gate driver of each power electronic switch, in the present case in the gate drivers of the IGBTs, samples of the voltage induced in the parasitic emitter inductance each IGBT are fed back in the gate driver to control rate of change of the current (di/dt) passing through the IGBT both during turn-on and turn-off, independently for each IGBT.

(23) A controlled portion of the voltage across the parasitic emitter inductance of each IGBT is thus injected in the gate driver to create a negative voltage (feedback) from the power circuit to the gate circuit of the IGBT, resulting in slowing down a variation of the gate-emitter voltage (V.sub.ge). The outcome is a direct action on the gate voltage without significantly causing delay or additional gate current.

(24) Because there is no optimal emitter inductance between the logical and power connections of the emitter in a conventional commercial IGBT module, a compensation circuit has been developed to optimize the sample of the voltage injected in the gate drive circuit separately during the turn-on and turn-off phases. FIG. 6 is a detailed view of a portion of FIG. 5 illustrating a compensation circuit according to a first illustrative embodiment. FIG. 6 shows the bottom portion of the parallelized legs 100 and 200 with an embodiment of the compensation circuit 112.

(25) For concision purpose, only the compensation circuit 112 and its connection to the IGBT Q.sub.1 and its gate drive G.sub.D1 will be described in detail hereinbelow; it is to be understood that the compensation circuits 114, 116 and 118 are similarly constructed.

(26) As shown on FIG. 6 the compensation circuit 112 includes a turn-on resistive divider circuit comprising resistors R.sub.1 and R.sub.2 connected in series and across the parasitic inductance L.sub.e1-low. A diode D.sub.on interconnects a junction of the resistors R.sub.1 and R.sub.2 to a reference 113 of the gate driver G.sub.D1.

(27) Similarly, the compensation circuit 112 includes a turn-off resistive divider circuit comprising resistors R.sub.3 and R.sub.4 connected in series and across the parasitic inductance L.sub.e1-low. A diode D.sub.off interconnects a junction of the resistors R.sub.3 and R.sub.4 to the reference 113 of the gate driver G.sub.D1.

(28) The turn-on and turn-off resistive divider circuits allow a separate adjustment of a level of the induced voltage that is fed back to the gate driver G.sub.D1. Upon turn-off of the IGBT Q.sub.1 a negative variation of the current passing through Q.sub.1 causes a drop voltage across the parasitic inductance (this will be best understood by reference to FIG. 2, which shows the polarity of the voltage generated on the parasitic emitter inductance at turn-off). The emitter voltage is lower than voltage at the reference 113. The turn-off diode D.sub.on is at that time non-conductive while the turn-off diode D.sub.off becomes conductive. The opposite is true at turn-on of the IGBT Q.sub.1. The turn-on and turn-off diodes D.sub.on and D.sub.off therefore ensure that the correct resistive divider is used at the appropriate switching phases of the IGBT Q.sub.1.

(29) It is to be noted that the gate drivers have separate control for the turn-on and the turn-off of the gate of their respective power electronic switches. Accordingly gate resistors R.sub.on and R.sub.off interconnect the output of the gate driver G.sub.D1 and the gate of the IGBT Q.sub.1 playing the role of the gate resistor R.sub.g of FIGS. 3 and 4 at the distinct switching phases. Increasing values of the gate resistors R.sub.on and R.sub.off slows down the rate of change of the current at turn-on and turn-off while decreasing their values speeds up this rate of change at turn-on and turn-off. This is open loop action does not take into account the differences in parasitic inductances of the power circuit that has a great impact on the commutation.

(30) Accordingly, for the turn-off the ratio of R.sub.3 over R.sub.4 combined with R.sub.off sets the rate of current fall in the IGBT Q.sub.1. The values of the two gate resistors R.sub.3 and R.sub.4 determine the feedback portion of the voltage sampled across the parasitic emitter inductance that is injected in the gate circuit of the IGBT Q.sub.1. Values of gate resistors are adjusted to control the turn-off loss, thereby controlling the thermal stress on the IGBT Q.sub.1 and keeping the overvoltage on the IGBT Q.sub.1 below its maximum rating.

(31) For the turn-on, the ratio of R.sub.1 over R.sub.2 combined with R.sub.on sets the current rise rate the IGBT Q.sub.1. The values of the gate two resistors R.sub.1 and R.sub.2, determine the feedback portion of the voltage sampled across the parasitic emitter inductance that is injected in the gate circuit of the IGBT Q.sub.1. Values of these resistors and of the corresponding resistors of the compensation circuit 116 are adjusted to balance the turn-on losses between the parallelized IGBTs Q.sub.1 and Q.sub.3, controlling their thermal stress while also maintaining the recovery current of the opposite freewheel diodes within their maximum ratings.

(32) The present technology separately adjusts, by a closing loop action, the rates of current rise and fall times of each IGBT placed in parallel with another IGBT (or more generally between each power electronic switch placed in parallel with another power electronic switch) according to parasitic inductances of their respective legs. It therefore allows balancing their switching losses while also controlling their overvoltage at turn-off as well as the recovery current at turn-on. This technology equalizes stresses applied to the power electronic switches.

(33) FIG. 7 is a detailed view of a portion of FIG. 5 illustrating a compensation circuit according to a second illustrative embodiment. The second embodiment of FIG. 7 discloses a compensation circuit 122 that differs from the compensation circuit 112 in that the resistor R.sub.2 and the turn-off diode D.sub.off have been removed.

(34) The compensation circuit 122 thus includes the resistor R.sub.1 that is so connected as to be parallel with resistor R.sub.3 during turn-on, when the emitter voltage of the IGBT Q.sub.1 is higher than the reference 113. The diode D.sub.on interconnects the resistor R.sub.1 to the reference 113 of the gate driver G.sub.D1. Accordingly, the values of R.sub.1 in parallel with R.sub.3 and the value of R.sub.4 are selected to feed back the adequate portion of signal to the gate driver during turn-on.

(35) The compensation circuit 122 forms a turn-off resistive divider circuit comprising resistors R.sub.3 and R.sub.4 connected in series and across the parasitic emitter inductance L.sub.e1-low. The diode D.sub.off is not required in the configuration of the compensation circuit 122 since the configuration of the diode D.sub.on ensures that the resistor R.sub.1 is not in play at turn-off.

(36) During turn-off, a ratio of R.sub.3 over R.sub.4 combined with R.sub.off sets the current fall rate to adjust the overvoltage limit in the IGBT Q.sub.1. Values of the two resistors R.sub.3 and R.sub.4 determine the feedback portion of the voltage induced in the parasitic emitter inductance that is injected in the gate circuit of the IGBT Q.sub.1. The values of these resistors are adjusted to keep the overvoltage on the IGBT Q.sub.1 under its rated limit and to balance turn-off losses between the IGBTs Q.sub.1 and Q.sub.3, the latter benefiting from the use of a similar compensation circuit 124.

(37) It may be noted that while the compensation circuit 122 has less elements than the compensation circuit 112 of FIG. 6, the resistor R.sub.2 and the diode D.sub.off being absent, this compensation circuit provides less adjustment flexibility.

(38) In the foregoing, the voltage induced across the parasitic emitter inductance L.sub.e1-low was selected to be fed back to the gate driver G.sub.D1 to improve the behavior of the IGBT Q.sub.1 at turn-on and turn-off and to reduce the dynamic unbalance that may occur in the case of parallelized power electronic switches by balancing their switching currents at turn-on and turn-off. Alternatively, voltages induced in other parasitic inductances may also be used to provide such feedback, inasmuch as the sample voltage is obtained from a parasitic inductance of the same leg as the power electronic switch that is being controlled.

(39) The present description of the compensation circuits 112 and 122, which also applies to the other compensation circuits have been shown and described referring to resistive circuits used to select the portion of the voltage induced in the parasitic emitter inductances. Use of other types of circuits to select a portion of the induced voltage such as for example circuits including transformers or other voltage adaptors is also contemplated.

(40) The foregoing describes solutions applicable to DC-DC converters and to DC-AC power converters for example to commutation cells using a full leg of semiconductors, opposite pairs of power electronic switches and freewheel diodes or to parallel semiconductor legs, to provide alternative current to a connected load such as a motor of an electric vehicle.

(41) Those of ordinary skill in the art will realize that the description of the commutation cell, power converter and compensation circuit are illustrative only and are not intended to be in any way limiting. Other embodiments will readily suggest themselves to such persons with ordinary skill in the art having the benefit of the present disclosure. Furthermore, the commutation cell, power converter and compensation circuit may be customized to offer valuable solutions to existing needs and problems related to variable characteristics of power electronic switches used in commutation cells and in power converters.

(42) In the interest of clarity, not all of the routine features of the implementations of the commutation cell power converter and compensation circuit are shown and described herein. It will of course be appreciated that in the development of any such actual implementation of the commutation cell power converter and compensation circuit numerous implementation-specific decisions may need to be made in order to achieve the developer's specific goals, such as compliance with application-, system-, and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the field of power electronics having the benefit of the present disclosure.

(43) It is to be understood that the commutation cell, power converter and compensation circuit are not limited in their application to the details of construction and parts illustrated in the accompanying drawings and described hereinabove. The proposed commutation cell power converter and compensation circuit are capable of other embodiments and of being practiced in various ways. It is also to be understood that the phraseology or terminology used herein is for the purpose of description and not limitation. Hence, although the commutation cell power converter and compensation circuit have been described hereinabove by way of illustrative embodiments thereof, they can be modified, without departing from the spirit, scope and nature of the subject invention.