Abstract
The present invention relates to a resistive random access memory device having a nano-scale tip, memory array using the same and fabrication method thereof. Especially, the present invention provides a technique forming a bottom electrode having an upwardly protruding tapered tip structure through etching a semiconductor substrate in order that an electric field is focused on the tip of the bottom electrode across a top electrode and that a region where conductive filaments are formed is maximally minimized or localized.
Claims
1. A resistive random access memory device comprising: a bottom electrode formed on a semiconductor line, the bottom electrode being formed by etching an upper portion of the semiconductor line to have an upwardly protruding tapered tip structure, the semiconductor line being etched from an upper portion of the semiconductor substrate such that the bottom electrode and the semiconductor substrate form one body with the unetched portion of the semiconductor substrate, the bottom electrode and the semiconductor line extending in a first direction and being oppositely doped to form a pn junction; an interlayer insulating film formed on the bottom electrode, the interlayer insulating film wrapping around the tip structure except for an upper part of the tip structure; a resistance change layer formed on the upper part of the tip structure and the interlayer insulating film; and a top electrode formed on the resistance change layer in a second direction across the bottom electrode over the tip structure.
2. The resistive random access memory device of claim 1, wherein the tip structure has a polygonal cone shape, a conical cone shape or a wedge shape, the wedge shape being configured to have a predetermined length in the first direction and a triangular cross-section in the second direction.
3. The resistive random access memory device of claim 2, wherein the resistance change layer is upwardly protruded along the upper part of the tip structure, and wherein the top electrode is formed to wrap the protruding part of the resistance change layer.
4. The resistive random access memory device of claim 1, wherein the tip structure has an upper end size of 10 nm or less in the second direction.
5. The resistive random access memory device of claim 2, wherein the tip structure has an upper end size of 10 nm or less in the second direction.
6. The resistive random access memory device of claim 3, wherein the tip structure has an upper end size of 10 nm or less in the second direction.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) FIG. 1 is an electrical characteristic diagram showing the relationship of voltage Vg and current Jg between a bottom electrode and a top electrode in the conventional resistive random access memory device structure.
(2) FIG. 2 is a v.sub.SET and v.sub.RESET distribution diagram showing v.sub.SET and v.sub.RESET caught and drawn each time when a current is rapidly changed in the conventional resistive random access memory device structure.
(3) FIG. 3 is a cross sectional view illustrating the structure of a resistive random access memory device according to an embodiment of the present invention.
(4) FIGS. 4 to 13 are process perspective views and cross sectional views taken along line AA′ showing a fabricating process of a memory array according to an embodiment of the present invention.
(5) FIG. 14(a) is cross sectional view taken along line AA in FIG. 13 and FIG. 14(b) is a cross sectional view taken along line BB in FIG. 13.
(6) FIGS. 15 to 17 are process perspective views showing a fabricating process of a memory array according to other embodiment of the present invention. Instead of FIG. 7, FIG. 15 is embodied. When it is carried out with FIG. 15, FIGS. 16 and 17 are process perspective views showing a memory array embodied instead of FIGS. 8 and 13, respectively.
(7) FIGS. 18(a) and 18(b) show an implementable structure by a fabricating process of a memory array according to an embodiment of the present invention. FIGS. 18(a) and 18(b) are showing a nano-cone shaped tip structure and its enlarged view, respectively.
(8) FIGS. 19(a) and 19(b) show an implementable structure by a fabricating process of a memory array according to other embodiment of the present invention. FIGS. 19(a) and 19(b) are showing a nano-wedge shaped tip structure and its enlarged view, respectively.
(9) In these drawings, the following reference numbers are used throughout: reference number 10 indicates a semiconductor substrate, 20 a semiconductor line, 22 a bottom electrode or a bit line, 30 an isolation insulating film, 40 a protruding pattern, 50 a tip structure, 52 an upper part of the exposed tip structure, 60 a wedge shaped tip structure, 70 an interlayer insulating film, 80 a resistance change layer, 82 and 84 a protruding part of a resistance change layer, 90 a contact hole and 100 and 110 a top electrode or a word line.
DETAILED DESCRIPTION
(10) Detailed descriptions of preferred embodiments of the present invention are provided below with reference to accompanying drawings.
(11) First, a detailed description of a resistive random memory device according to an embodiment of the present invention is provided with reference to FIGS. 3 to 17.
(12) A resistive random access memory device according to an embodiment of the present invention, as exemplarily shown in FIG. 3, comprises: a bottom electrode 22 formed in a first direction by etching a semiconductor substrate 10, the bottom electrode 22 having an upwardly protruding tapered tip structure 50; an interlayer insulating film 70 formed on the bottom electrode 22, the interlayer insulating film 70 wrapping around the tip structure 50 except for an upper part 52 of the tip structure; a resistance change layer 80 formed on the upper part 52 of the tip structure 50 and the interlayer insulating film 70; and a top electrode 100 formed on the resistance change layer 80 in a second direction across the bottom electrode 22 over the tip structure 50.
(13) Here, the semiconductor substrate 10 may be silicon or other semiconductor such as germanium, etc. And, referring to FIGS. 4 to 10, the bottom electrode 22, as described later, may be formed of a conductive line having an opposite conductivity type to the semiconductor substrate 10 by an ion implantation process on a semiconductor line 20 formed from the semiconductor substrate 10 by etching it. Thus, if the semiconductor substrate 10 is a P-type substrate, the bottom electrode 22 can be formed of an N-type conductive line. Of cause, the opposite can be also formed.
(14) The bottom electrode 22, as shown in FIG. 3, has an upwardly protruding tapered tip structure 50.
(15) The tip structure 50 may have a polygonal cone shape, a conical cone shape or a wedge shape. In case that the tip structure 50 has the wedge shape, it may be configured to have a predetermined length in the first direction and a triangular cross-section in the second direction.
(16) Although FIG. 8 shows, as an example, that a tip structure 50 of each resistive random access memory device is formed as a pyramidal shaped tetragonal-cone, the tip structure 50 is not limited to the tetragonal-cone and it is possible to be formed as a polygonal-cone. Further, it is possible to have a conical-cone shape as shown in FIG. 18 or a wedge shape having a predetermined length and a triangular cross-section as shown in FIGS. 15 to 17, 19(a) and 19(b).
(17) Because the tip structure 50 is formed to be tapered upwardly and to have a sharp upper end, the upper end size (i.e., minimum width) in the second direction (i.e., the direction of the top electrode 100) can be less than a few nanometer, as an example, 10 nm or less.
(18) Thus, it is possible to maximally minimize or localize a region where conductive filaments are formed in a resistance change layer 80 by concentrating an electric field to the upper end of the tip structure 50 of a bottom electrode 22 across a top electrode 100.
(19) Because the interlayer insulating film 70 enables the exposed range of the upper part 52 of the tip structure 50 to be determined by adjusting the stacking thickness of the insulating film, it is possible to secondarily and more effectively restrict a region where conductive filaments are formed. The interlayer insulating film 70 may be a known insulating film such as a silicon oxide film when the semiconductor substrate is a silicon substrate, but as described later, it is preferable that the interlayer insulating film 70 is formed of an isolation insulating film used to isolate semiconductor lines.
(20) And the resistance change layer 80 may be also formed of a known resistance change material by depositing to the thickness more than the height of the tip structure 50 exposed on the interlayer insulating film 70 and planarizing the upper part by the planarization process, etc. and then the top electrode 100 may be formed (not shown). But it is preferable that the resistance change layer 80 is formed to be upwardly protruded on the tip structure 50 as shown in FIG. 3 and the top electrode 100 is formed to wrap the protruding part 82 of the resistance change layer 80.
(21) Next, a detailed description of a memory array according to an embodiment of the present invention is provided.
(22) A memory array according to an embodiment of the present invention is using the above mentioned resistive random access memory device of the present invention as a unit cell device and, as shown in FIGS. 13 and 14(a), 14(b) or 17, and comprises: a semiconductor substrate 10; a plurality of bit lines 22 formed in a first direction on the semiconductor substrate 10; and a plurality of word lines 100 formed in a second direction across the bit lines 22, a resistance change layer 80 being located between the word lines 100 and the bit lines 22, wherein the bit lines 22 are formed in one body with the semiconductor substrate 10, each of the bit lines 22 being a bottom electrode line doped with an impurity and electrically insulated from adjacent lines with an isolation insulating film 30, the bottom electrode line having upwardly protruding tapered tip structures 50 along the first direction, wherein an interlayer insulating film 70 is further formed between the bit lines 22 and the resistance change layer 80, the interlayer insulating film 70 wrapping around the tip structures 50 except for upper parts 52 of the tip structures 50, wherein the resistance change layer 80 is formed on the upper parts 52 of the tip structures 50 of the each bit line 22, the interlayer insulating film 70 and the isolation insulating film 30, and wherein each of the word lines 100 is formed of a top electrode line passing over the tip structures 50 of the bit lines 22 along the second direction.
(23) Here, as mentioned above, the tip structure 50 may have a polygonal cone shape, a conical cone shape or a wedge shape. In case that the tip structure 50 has the wedge shape, it may be configured to have a predetermined length in the first direction and a triangular cross-section in the second direction.
(24) Although FIG. 8 shows, as an example, that a plurality of tetragonal-cone tip structures 50 are formed along each semiconductor line 20 at a predetermined interval, the tip structure 50 is not limited to the tetragonal-cone and it is possible to be formed as a polygonal-cone. Further, it is possible to have a conical-cone shape as shown in FIG. 18 or a single wedge shape 60 having a predetermined length and a triangular cross-section as shown in FIGS. 15 to 17 and 19.
(25) Because the tip structure 50 is formed to be tapered upwardly and to have a sharp upper end, the upper end size (i.e., minimum width) in the second direction (i.e., the direction of the word line 100) can be less than a few nanometer, as an example, 10 nm or less.
(26) Thus, it is possible to maximally minimize or localize a region where conductive filaments are formed in a resistance change layer 80 by concentrating an electric field to the end of the tip structure 50 of each bit line 22 across each word line 100.
(27) Because the interlayer insulating film 70 and the resistance change layer 80 according to this embodiment are the same as those in the embodiment of a resistive random access memory device, each detailed explanation is omitted.
(28) In FIGS. 13 and 17, the reference numbers 92, 102 and 110 indicate a bit line contact plug, a word line contact plug and a word line having a small width, respectively.
(29) Next, a detailed description of a fabrication method of a memory array according to an embodiment of the present invention is provided with reference to FIGS. 4 to 14.
(30) A fabrication method of a memory array according to an embodiment of the present invention is to fabricate the above mentioned memory array of the present invention.
(31) First, after a semiconductor substrate 10 for fabricating a memory array is prepared, as shown in FIG. 4, a plurality of semiconductor lines 20 for forming a plurality of contacts and bit lines is protruded by etching the semiconductor substrate 10 (a first step). The semiconductor substrate 10 may be a silicon substrate, but it can be other semiconductor substrate such as a germanium substrate and the like.
(32) Then, as shown in FIG. 6, an isolation insulating film 30 is formed by depositing a first insulating material on the semiconductor substrate 10 and etching the first insulating material to expose upper parts of the semiconductor lines 20 and to be insulated from each other (a second step). The first insulating material may be an oxide film. After depositing the first insulating material, it is preferable that the first insulating material is planarized by the known CMP process, etc. and etched to be exposed the upper parts of the semiconductor lines 20.
(33) Next, as shown in FIG. 7, protruding patterns 40 are formed on the upper parts of the semiconductor lines 20 (a third step). The protruding patterns 40 can be formed by one of the following two processes. One process is to form tip structures by etching the protruding pattern itself 40. In this case, the protruding pattern 40 is formed of a semiconductor material such as the same or similar to the semiconductor substrate 10. The other is that the protruding patterns 40 are used as etching masks and the tip structures are formed by etching semiconductor lines exposed around the etching masks. In the latter case, although the etching masks may be used as dry masks, it is preferable to be used as wet masks formed of oxide or nitride. Specifically, for forming the etching masks, it is possible to use one process selected from photolithography, sidewall patterning and e-beam processes.
(34) And the shape of the tip structures can be determined according to that of the protruding patterns 40. Thus, the protruding patterns 40 may have a shape selected from a regular polygon such as a square, etc., a circle, an ellipse and a rectangle and be formed with a single or a plurality at a predetermined interval in a longitudinal direction of each semiconductor line 20.
(35) Although, in an embodiment shown in FIG. 7, the protruding patterns 40 are a square and are formed with a plurality in a longitudinal direction of each semiconductor line 20, in other embodiment shown in FIG. 15, the protruding patterns 40 can be a rectangle 42 and be formed with a single in each semiconductor line 20.
(36) Next, as shown in FIG. 8, an upwardly protruding tapered tip structures 50 are formed on the upper part of a portion that forms each bit line by using the protruding patterns 40 (a fourth step). Namely, in case that the protruding patterns 40 are formed of a semiconductor material, the tip structures 50 are formed by etching the protruding patterns 40 and the exposed semiconductor lines 20. While when the protruding patterns 40 are formed to be used as etching masks, the tip structures 50 are formed by etching the semiconductor lines exposed around the etching masks.
(37) Although FIG. 8 shows, as an example, that a plurality of tetragonal-cone tip structures 50 are formed along each semiconductor line 20 at a predetermined interval, according to an embodiment shown in FIG. 15, the tip structures 50 can be formed with a single wedge shape having a predetermined length and a triangular cross-section on each semiconductor line 20 as shown in FIG. 16.
(38) In the fourth step, when the etching of the semiconductor lines 20 and/or the protruding patterns 40 is performed to form the tip structures 50, it is preferable to use an anisotropic etching. Here, the anisotropic etching means to have different etching rates according to the crystal planes of a semiconductor. It is different from non-isotropic etching to etch vertically in a clear direction such as a dry etching and also different from an isotropic etching to etch uniformly in all areas contacted with etchant. Among the anisotropic etchings, an anisotropic wet etching is more preferred. When the semiconductor lines 20 and/or the protruding patterns 40 are formed of a silicon, referring to FIGS. 18 and 19, it is possible to embody a very sharp peak-type tip structure 50 having an upper end size (at a cross-section in the second direction, namely, minimum width) of a few nanometer nm, as an example, 10 nm or less by performing an anisotropic wet etching with etchant such as TMAH, KOH, etc.
(39) Next, as shown in FIG. 9, a plurality of contacts and bit lines are formed on the upper parts of the semiconductor lines 20 by performing an ion implantation process (a fifth step). Here, the ion implantation process is used to raise the electric conductivity of not only the protruding tip structures 50, but also the upper parts of the semiconductor lines 20 for forming the plurality of contacts and bit lines as conductive lines (namely, bottom electrodes). And to be insulated from the lower parts of semiconductor lines 20 and the semiconductor substrate 10, the plurality of contacts and bit lines may be formed of an N-type when the semiconductor substrate 10 is a P-type substrate. Of course, the opposite can be formed.
(40) Then, as shown in FIGS. 10(a) and 10(b), a second insulating material is deposited on the upper parts of the plurality of contacts and bits lines 22 and the isolation insulating film 30, and the second insulating material and the isolation insulating film 30 are etched to form an interlayer insulating film 70 with the second insulating material, the interlayer insulating film 70 wrapping around the tip structures except for upper parts 52 of the tip structures 50 (a sixth step).
(41) FIG. 10B is a cross sectional views taken along line AA′ in FIG. 10(a). As shown in FIG. 10(b), because the exposed range of the upper part 52 of the tip structure 50 is determined by adjusting the thickness of the interlayer insulating film 70, it is possible to secondarily and more effectively restrict a region where conductive filaments are formed.
(42) And it is preferred that the second insulating material is the same as the first insulating material forming the isolation insulating film 30. At this time, the etching process of the second insulating material and the isolation insulating film 30 can be carried out after depositing and further planarizing the second insulating material. By doing so, as shown in FIG. 10(b), because the interlayer insulting film 70 and the isolation insulating film 30 can be etched in a same horizontal plane, it is easy to protrude the upper parts 52 of the tip structures 50 of the each bit line 22.
(43) Next, as shown in FIG. 11, a resistance change layer 80 or 82 is formed on the exposed upper parts 52 of the tip structures 50 of the each bit line 22, the interlayer insulating film 70 and the isolation insulating film 30 by depositing a resistance change material and, as shown in FIG. 12, a plurality of contact holes 90 that reach the each contact are formed (a seventh step).
(44) Here, the resistance change layer 80 or 82 may be formed of a known resistance change material. The resistance change material can be deposited with a thickness more than the height of the tip structures 50 exposed from the interlayer insulating film 70 and planarized by a planarization process, CMP etc. and then a following process for forming the top electrodes (word lines) 100 can be carried out (not shown). As other embodiment, the resistance change layer 80 or 82 can be upwardly protruded on the tip structure 50 as shown in FIG. 3 and be formed with a predetermined thickness, as shown in FIGS. 11(b) and 12(b), and the protruding parts 82 of the resistance change layer 80 can be formed on the tip structures 50 exposed from the interlayer insulating film 70. In a following process, as shown in FIG. 14, the top electrodes (word lines) 100 can be formed to wrap the protruding parts 82 of the resistance change layer 80.
(45) Then, as shown in FIGS. 14(a) and 14(b), a plurality of word lines 100 and word line contacts 101 and a plurality of bit line contacts 91 filled in the plurality of contact holes 90 are formed by depositing and etching a conductive material on the resistance change layer 80 or 82 (an eighth step).
(46) FIGS. 13, 14(a) and 14(b) show an example that the protruding patterns 40 of the third step can have a square shape and be formed with a plurality at a determined interval in a longitudinal direction of each semiconductor line 20 and the each word line 100 of the eighth step can be intersected with the each bit line 22 at a location of a singe pyramidal tip structure 50.
(47) On the other hand, FIGS. 15 to 17 show another example that the protruding patterns 40 of the third step can have a rectangular shape 42 and be formed with a single in a longitudinal direction of each semiconductor line 20 and the each word line 110 of the eighth step can be intersected with the each bit line 22 at a location of a wedge shaped tip structure 60 as shown in FIGS. 16, 19(a) and 19(b).
(48) This work was supported by the Center for Integrated Smart Sensors funded by the Korean Ministry of Science, ICT & Future Planning as Global Frontier Project (CISS-2012M3A6A6054186).
