MOTOR DRIVE CIRCUITRY

Abstract

A motor drive circuit for use in driving a motor having two or more phases comprising a motor bridge having, for each phase of the motor, a bridge arm comprising an upper switch and a lower switch that in normal operation may be opened and closed to modulate the voltage applied to the respective phases in response to drive signals from a motor control circuit, at least one solid state phase isolation relay that is provided in series in an electrical path connecting a respective phase of the motor to a respective bridge arm, the relay being closed in normal operation so that current can flow in the phase and is held open in a fault mode of operation to prevent the flow of current in the phase. The circuit also includes monitoring means for monitoring the current waveform in the phase to provide, at least in a fault mode of operation, an output indicative of when it is safe to open the SSPIR without causing damage due to the SSPIR due to an avalanche mode, and a control circuit that during normal operation applies a voltage to each device that is sufficient to hold the SSPIR closed and which, in the fault mode of operation, responds to the output of the monitoring means to reduce the voltage applied to each SSPIR to a level that causes the SSPIR to open at the safe time.

Claims

1.-19. (canceled)

20. A motor drive circuit for use in driving a motor having two or more phases, the motor drive circuit comprising: a motor bridge having, for each phase of the motor, a bridge arm comprising an upper switch and a lower switch that in normal operation may be opened and closed to modulate the voltage applied to the respective phases in response to drive signals from a motor control circuit; at least one solid state phase isolation relay (SSPIR) that is provided in series in an electrical path connecting a respective phase of the motor to a respective bridge arm, the SSPIR being closed in normal operation so that current can flow in the phase and is held open in a fault mode of operation to prevent the flow of current in the phase, a monitoring means for monitoring the current waveform in the phase to provide, at least in a fault mode of operation, an output indicative of a safe time when it is safe to open the SSPIR without causing damage due to the SSPIR due to an avalanche mode; and a control circuit that during normal operation applies a voltage to each device that is sufficient to hold the SSPIR closed and which, in the fault mode of operation, responds to the output of the monitoring means to reduce the voltage applied to each SSPIR to a level that causes the SSPIR to open at the safe time.

21. A motor drive circuit according to claim 20 in which each phase is provided with a respective SSPIR, and the monitoring means monitors the current waveform in each phase independently, so that the timing of opening of each SSPIR is independent of other SSPIRs.

22. A motor drive circuit according to claim 20 in which the current monitoring circuit that monitors the current flowing in each phase monitors the rate of change of current, either directly or indirectly.

23. A motor drive circuit according to claim 22 in which the monitoring means determines when the signal dependent on the rate of change of current in a respective phase is negative.

24. A motor drive circuit according to claim 23 in which the monitoring means has a threshold rate of change of the signal it is monitoring which must be exceed before the output indicates it is safe to open the switches.

25. A motor drive circuit according to claim 20 in which the monitoring circuit monitors the current waveform by monitoring a signal indicative of the voltage dropped across the SSPIR.

26. A motor drive circuit according to claim 25 in which the monitoring means includes a low pass filter through which the voltage signal is passed as a filtered signal, the monitoring means monitoring the filtered signal.

27. A motor drive circuit according to claim 26 in which the low pass filter comprises an RC filter in which the resistance (R) is at least in part dependent on the SSPIR resistance.

28. A motor drive circuit according to claim 20 in which the control circuit is configured so that after initiation of a fault mode, one of the voltage applied to a gate or current applied to a base for a bipolar device is dropped gradually over time so that prior to reaching the respective voltage or current at which the SSPIR is opened it gradually passes through a threshold region in which one of a drain-source resistance and a collector-emitter resistance varies highly for small changes in one of the respective gate voltage and the base current.

29. A motor drive circuit according to claim 28 in which the control circuit is arranged to slowly drop the respective voltage or base current from a respective first voltage or first base current above one of a respective threshold voltage or threshold base current, to a second voltage or second base current that is below the value at which the SSPIR opens.

30. A motor drive circuit according to claim 28 in which a rate of fall of the respective gate voltage or base current is chosen as a function of a rate of rotation of the motor, so that it takes at least two cycles of the current waveform to drop through the threshold region when the motor is at its maximum rated speed.

31. A motor drive circuit according to claim 28 in which the control circuit is configured, following the initiation of a fault mode of operation, to rapidly drop the gate voltage or base current applied to the gate or base of each SSPIR to a level closer to the threshold of the SSPIR but above the device opening value, and subsequently to more slowly reduce the value over time to pass though the threshold.

32. A motor drive circuit according to claim 20 in which the control circuit for the SSPIR includes a reservoir capacitor that is connected to the gate or base of the SSPIR that following the start of a fault event provides a voltage or current of which a full or reduced proportion is applied to the gate or base prior to opening the SSPIR at or just above the threshold.

33. A motor drive circuit according to claim 32 in which the control circuit is configured to provide a path through which current is drawn from the reservoir capacitor to cause the gate voltage to drop gradually towards the SSPIR opening voltage through the threshold.

34. A motor drive circuit according to claim 20 in which the SSPIR control circuit includes a clamp circuit associated with each SSPIR that rapidly opens the SSPIR at the safe time by rapidly dropping the voltage/current applied to the gate or base of the SSPIR.

35. A method of driving a motor of the kind having multiple phases, each phase being connected to a bridge driver through a respective solid state phase isolation relay (SSPIR), the method comprising, in the event of a fault event being initiated, performing the following steps in order: determining a time when the current flowing in each phase is at a level where it is safe to open the SSPIRs without causing damage due to the SSPIR entering an avalanche mode, and in the event that a safe time is identified opening the SSPIRs.

36. A method according to claim 35 which further comprises the step of monitoring the current waveform flowing in each phase, or monitoring a signal that is a function of the current waveform, to detect when the current has passed a peak, and opening the SSPIR once the peak has been passed.

37. A method according claim 35 which further comprises the step of monitoring the current waveform indirectly by monitoring a signal dependent on the voltage dropped across the SSPIR.

38. A method according to claim 35 which comprises, the step of following initiation of a fault event, dropping the gate voltage or base current for a bipolar device of the SSPIR to a threshold level where the device resistance varies steeply with changes in voltage, and monitoring the voltage dropped across the device at that time as the signal indicative of the current waveform.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0074] FIG. 1 is a general schematic representation of a prior art motor circuit for use in an automotive electric power assisted steering system.

[0075] FIG. 2 is a schematic corresponding to FIG. 1 showing the potential path of current flowing round the motor when one of the switches is faulty.

[0076] FIG. 3 is a schematic illustration corresponding to FIG. 1 showing an alternative path for current to flow even after the bridge has been closed caused by inductive decay of current in the motor associated with the motor inductance.

[0077] FIG. 4 is a schematic illustration also corresponding to FIG. 1 showing a further source of current flow due to back emf in the motor as it is rotated at speed.

[0078] FIG. 5 is a schematic illustration of an alternative circuit in which each phase of the motor is protected by a serially connected switch between the motor phase and the bridge.

[0079] FIG. 6 is a schematic illustration corresponding to FIG. 5 showing a path for current flow due to back emf in the motor even when the bridge is closed.

[0080] FIG. 7 is a schematic illustration of an embodiment of a motor drive circuit according to a first aspect of the present invention connected to a motor.

[0081] FIG. 8 is a schematic illustration of the control circuit associated with a single SSPIR.

[0082] FIG. 9 is a plot of the power dissipated across a single SSPIR against time following opening of the bridge switches that initiates a fault event at time t=50 mseconds when the motor is rotating at, in this example, a maximum expected speed of 5000 rpm.

[0083] FIG. 10 is a plot of the voltages and current in the device over time for the event plotted in FIG. 9.

[0084] FIG. 11 is a plot of the gate-source voltage, Vgs, drain-source voltage Vds, and drain source current Ids, against time, for a test operation of a test rig in which a fault event is triggered and the motor is idle.

[0085] FIG. 12 is a similar set of plots to FIG. 11 for a repeat test in which the motor is spinning freely.

[0086] FIG. 13 is a similar set of plots to FIG. 11 for a repeat test in which the motor is being forcibly turned at high speed by a driver.

[0087] FIG. 14 is an enlarged view of the plots of FIG. 13.

[0088] FIG. 15 is an alternative enlarged view of the plots of FIG. 13.

[0089] FIG. 16 is graph showing SSPIR drain-source resistance varying with the gate voltage (voltage gate-source) and showing the threshold at which the resistance rapidly starts to rise as voltage drops below about 5 volts.

[0090] FIG. 17 is an exemplary control circuit and monitoring circuit for one SSPIR of the motor drive circuit, as used in the tests of FIGS. 11 to 15.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0091] As shown in FIG. 7 a motor drive circuit 100 for use in an electric power assisted steering system is shown. The motor 101 comprise a three phase motor, having three phase U, V and W connected together at a common star point 102. The ends of each phase, not connected at the star point, are connected to respective branches of a motor bridge circuit 103 via a plurality of solid state phase isolation relays (SSPIRs) 104,105,106, one in series with each phase. The schematic shows for each SSPIR the internal diode and the Miller capacitance (associated with MOSFET devices) as separate elements.

[0092] The motor bridge circuit is not shown in detail but will typically be in line with that shown in FIG. 1. Each arm or branch comprises an upper portion which connects the motor to a positive side of a battery supply through a top MOSFET switch, and a lower portion which connects the motor phases to a negative side of the battery supply through a bottom MOSFET switch. The top and bottom switches in each arm enable the phase to be connected to the positive side by closing a top transistor and simultaneously opening the bottom one. They also enable it to be connected to the earth by closing the bottom transistor and simultaneously opening the top one. Similarly, they allow the phase to be left floating by simultaneously opening both the top and bottom transistors.

[0093] The opening and closing of the top and bottom MOSFETs of the bridge is controlled by a switching pattern applied to the switches by a control circuit (not shown) which is based upon a microprocessor and bridge driver. The pattern indicates whether each of the switches should be opened and closed at any time. Where MOSFET switches are used as illustrated the pattern may simply comprise a positive voltage applied between Gate-Source terminals of the transistor to close it, or zero voltage between Gate-Source terminals when the switch is to be closed. The choice of switching pattern depends on the position of the motor at any given time, the desired motor torque that is to be achieved, and the desired motor speed. Provided that the motor position and speed are measured and fed to the microprocessor, together with a torque demand signal indicative of the torque required from the motor. These measurements and signals are processed by the microprocessor to produce the desired patterns. Additional signals may be used to determine the desired inverter switching pattern. Such a control circuit is well known in the art, and so will not be discussed here in any detail.

[0094] Associated with the bridge is a diagnostic circuit 120. This comprises a monitoring means that determines an event in which a switch of the bridge is faulty, and a bridge shutdown control means that, upon receiving a signal from the first monitoring means indicating that a switch of the bridge is faulty opens the remaining switches of the bridge.

[0095] Each SSPIR is a solid state switch 104, 105, 106 that as shown comprises a MOSFET transistor. In use this is normally closed (drain-source conductive). The switches are held closed in normal operation by a voltage applied to the gate from an SSPIR control means 108. The control means is an analogue circuit in this example and is shown as a block in FIG. 8, and in more detail in FIG. 7. An exemplary circuit is shown in FIG. 17. The control circuit is arranged in three identical parts-one associated with each SSPIR. For convenience the operation of a single control circuit and SSPIR is given below, the two others working the same way.

[0096] The control circuit functions to hold the SSPIR closed in the normal mode of operation and open it safely when a fault event (shutdown) is triggered. The control circuit responds to an output signal from a respective monitoring circuit 113 that monitors a signal that is a function of the current flowing through the SSPIR to identify a safe time to open. Thus, the SSPIR is only opened by the control circuit 108 when it is safe to do so, defined as a time when the current and voltage across the SSPIR will not reach a level which, if enduring for long enough, will not cause the SSPIR to enter avalanche breakdown.

[0097] The gate supply voltage in this example is derived from a 28V supply, but must not exceed 20V at the gate (abs-max, 14-15V is typical), with the threshold of the device being around 4-5V as stated previously. In the normally closed state, the control means therefore applies a gate supply voltage, of, say 15 volts, to each MOSFET and in this mode each SSPIR has no significant effect on the operation of the motor, other than to provide a small fixed voltage drop across the closed MOSFET.

[0098] The operation of the control circuit 108 and monitoring circuit 113 will now be explained in more detail, with reference to the detailed circuit shown in FIG. 17.

[0099] As shown in the detailed schematic of FIG. 7 and in FIG. 17, the three identical parts of the control means share a common switch 109 that in normal operation with <Shutdown> disabled is closed. The switch 109 connects the Gate Supply voltage 107 via a reverse blocking diode to a low drop-out regulator (LDO) 110 which sets the on-state gate voltage at around 15 volts irrespective of the supply voltage which is nominally around 28 volts. The control means also includes a reservoir capacitor 111 that holds up the gate voltage in the event of brief dips in the Gate Supply.

[0100] The control circuit also includes a proportional gate control circuit 112 that is inoperative in the normal mode, and a gate clamp circuit 114 which is also inoperative in the normal mode. Although shown as separate blocks these are all an integral part of the control circuit for each SSPIR.

[0101] The monitoring means 113 in the example of FIG. 7 and FIG. 17 comprises an edge detection circuit 113 associated with each SSPIR that monitors indirectly the rate of change of current flowing through the SSPIR, and produces an output signal when the current is dropping above a threshold rate after reaching a peak. This indicates it is a safe time to open, and this signal is fed to the control means 108. When this signal indicates that the current has passed a peak, the control means responds by rapidly opening the switch by activating the gate clamp 112 that pulls the gate voltage rapidly down to a low voltage below that at which the SSPIR is opened (non-conducting).

[0102] In normal operation the diagnostic means simply watches the bridge, but if a MOSFET is identified is a faulty the shutdown control means forces all the other MOSFETS to an open (non-conducting condition). This is a first stage of protection of the motor, an initiation of a <shutdown> event. After that event has been initiated the SSPIRs are opened to give additional protection but only when it is determined that it is safe to do so. This two stage, controlled opening of switches ensures that a high degree of protection is given with a low risk of damage to the switches.

[0103] Following initiation of a <Shutdown> fault event, immediately after the bridge switches have been opened, the control means opens the switch 109 and so isolates the gate supply voltage for each SSPRI from the gate. This in turn causes the

[0104] Proportional Gate Control circuit that forms a part of the SSPIR control circuit to become active. This control circuit at that time switches from providing the full on-state gate voltage to a variable proportion of that held on the reservoir capacitor 111, that is around the gate threshold level. For instance if the threshold is 4-5 volts, the voltage at the gate drops to around ⅔.sup.rd of the capacitors 15 volts by the proportional control circuit, which is greatly reduced but still above the threshold by a safe margin as the start of the slow drop.

[0105] As time passes following the start of <Shutdown>, the voltage on the reservoir capacitor 111 decays over time. The Proportional Gate Control circuit 112 continues to supply an ever-smaller proportion of the voltage at the reservoir capacitor, such that the gate voltage reaches the off-state (i.e. SSPIR open) within the duration set by the applicable Safety Requirement (100 ms typical).

[0106] As the gate voltage drops, it will pass through the threshold region, by which we mean the region where the on-state resistance (Rds-on) of the SSPIR MOSFET rises. Any fault current due to Motor regeneration will cause a steadily increasing voltage waveform across the SSPIR (Vds). The monitoring means monitors this voltage once it exceeds a detection threshold. This is the signal that indirectly indicates what the current waveform is doing, since the voltage depends on resistance and current.

[0107] Fault current causing a positive-going rise in Vds will also cause a rise in gate voltage (Vgs) due to the inherent Miller capacitance (drain-gate capacitance) of the SSPIR MOSFET and the relatively high impedance of the Proportional Gate Control circuit. This results in a momentary reduction in Rds-on, limiting the rise of Vds. This effect may be enhanced by additional external drain-gate capacitance as shown. This mechanism ensures that the switch is not opened at a time when an increasing fault current is flowing, because the drop in gate voltage is halted due and hence the gradual opening is halted.

[0108] Eventually, the current in the phase will drop. This is because the back emf is proportional to rpm (which is typically dropping once a fault event has been triggered because the bridge at that time will generally be disabled), plus the SSPIR resistance rises as the gate voltage drops, increasing the on State resistance of the device which is related to the current by the function I=V/R. This drop in current is monitored indirectly by the monitoring means (the circuit marked edge detection in FIG. 7) which detects the negative-going Vds waveform. Once this is detected to be above a threshold level (set by the Vds Edge Detection circuit), the monitoring circuit outputs a signal to a gate clamp that forms part of the SSPIR control circuit that triggers the clamp circuit 114 that is in this example a “thyristor-like” Gate Clamp circuit. The Gate Clamp circuit rapidly discharges both the reservoir capacitor and, via a diode, the voltage on the SSPIR MOSFET gate. This rapidly opens the SSPIR.

[0109] It is safe to assume that the drop in the Vds voltage corresponds to a drop in current because, although the absolute device resistance is unknown it is known that it is gradually rising over time and so in itself cannot lead to a high rate of fall of the voltage, indeed it would contribute to an increasing voltage for a steady current. The voltage is therefore suitable for use in indirectly monitoring the current waveform, and using the SSPIR in this way eliminates the need for a separate current sense resistor.

[0110] To meet applicable Safety Integrity Level (SIL) requirements, correct functioning of the SSPIR control circuit must be verifiable at power-on and at other times, according to the requirement.

[0111] FIGS. 9 and 10 show the operation of the motor drive circuit of FIG. 7 in a typical fault event. In this example, the bridge circuit is shut down at time t=50 mseconds which prompts an immediate operation of the control means for the SSPIR into a fault event mode. The plots correspond to only one SSPIR and include the power PWR_SSPRI, the drain-source current Ids corresponding to the current in the phase, the gate voltage Vgs, the Voltage on the reservoir capacitor Vreservoir, and the voltage dropped across the device from draining to source Vds.

[0112] Prior to the fault event the gate of the SSPIR is held at approximately 14 volts as set by the LDO charging the reservoir capacitor. This is considerably higher than the threshold voltage which is about 4-5 volts for a typical MOSFET as shown in FIG. 16 (the region of the obvious knee in the graph). On the start of the fault event, the proportional gate control starts and the gate voltage is rapidly dropped to a proportion of the voltage held on the reservoir capacitor voltage. In this case the voltage drops about 5 volts below the capacitor voltage, i.e. to around 10 volts and then decreases slowly towards the threshold of about 5 volts as the capacitor voltage gradually decreases. This can be seen to then gradually decrease over time as the reservoir current is drawn off up to about 80 milliseconds. Note that in this example the SSPIR has a threshold of around 5 volts, so the voltage is clearly around that level yet well above the level at which the SSPIR is opened which in this example is around 2 volts.

[0113] The phase current, Ids, varies periodically and is due to the back emf as the motor rotates at 5000 rpm. After approx40 milliseconds, the gate voltage drops below the threshold voltage to the extent that the device resistance rapidly rises. This rise in resistance causes the power in the device to rise rapidly although this is kept in check by the effect of the miller capacitance in the device causing the gate voltage to rise, thus reducing the resistance.

[0114] As soon as the phase current in that cycle starts to drop, at around 85 milliseconds, the threshold detector triggers the clamp. This then rapidly deletes the charge in the reservoir capacitor which causes the gate voltage to drop below the 4 volt level at which the SSPIR is open in this example.

[0115] The switch is therefore rapidly opened but only when it is safe to do so. The power in device does not rise above 500 watts for any significant time. This limitation of the power and the duration of the power pulse together are what prevents an avalanche fault occurring.

[0116] The limit in this particular implementation is ˜800 mJ (e.g. a mean power of 800 W over 1 ms, say), or ˜400 mJ when operating at high temperature (designed to operate within this lower limit).

[0117] To understand the operation more clearly, FIGS. 11 to 15 are test plots obtained during various motor operation conditions from start of a fault event to the SSPIR opening obtained on a test rig simulating an electric power assisted steering system. The rig included a motor with a maximum rated speed of rotation when forced around by a driver of 5000 rpm, and a drive circuit with the control and monitoring circuit configured in accordance with FIG. 17. Each SSPIR MOSFET had a threshold of around 4-5 volts, and an Open gate voltage of 2 volts or less. A gate supply voltage of 28 volts was used, and the capacitor controlled the proportional controller to drop rapidly to 10 volts (some 4 volts or so above the threshold) before being drained over the next 100 milliseconds or so.

[0118] FIG. 11 shows the results of a first test in which </Shutdown> is removed for 10 ms (10 ms per division), with the motor idle. [0119] Yellow trace is Vgs (gate voltage), 5V per division. It rises and holds at 14V for 10 ms, falls rapidly to ˜7V (i.e. 7 volts are immediately removed by the “proportional gate drive cct”), then decays slowly (tracking the reservoir cap decay less 7V), reaching 3V after a further 70 ms. [0120] Magenta is Vds (drain-source voltage), 5V per division. In the test setup, it drops from 1/0V to OV immediately on release of </Shutdown> then rises slowly over 20 ms (i.e. slow switch-off), beginning ˜50 ms after </Shutdown> is asserted with Vgs at ˜3.5V. [0121] Cyan is Ids (drain current), 20 A per division derived from 100 mV p-d across a 5 mΩ resistor for the purpose of taking the measurement on the test circuit. It remains at zero throughout (motor stationary).

[0122] FIG. 12 shows the motor spinning freely prior to </Shutdown> removal (and effective Bridge fault insertion). The initial fault current due to the phase-phase open circuit back-emf of 22V (just prior to fault insertion) is ˜96 A peak. This fault current introduces opposing torque, braking the motor such that the current peak only reaches ˜10 A after 40 ms. No trigger occurs, the SSPIR opens naturally at some point after 60 ms, evidenced by Vds no-longer returning to zero.

[0123] FIG. 13 shows the test repeated for the case where the motor is spinning with significant driver input. Initial current peaks of 125 A are sustained for 20 ms, and only appear to decay as Rds rises, evidenced by a rising Vds signal.

[0124] FIG. 14 is the same test results as FIG. 13, zoomed-in (1 ms/div) to show the triggering and rapid gate turn-off around 28 ms following </Shutdown>. There is a narrow spike in Vds, due to the remaining 10 A of fault current, which disappears almost immediately due to the high negative dI/dt bringing the current rapidly to zero.

[0125] The effect of Miller capacitance can be seen here aiding the turn-off, causing a negative undershoot of the gate voltage (−2V).

[0126] Finally, FIG. 15 is also the same run as FIG. 13. The effect of Miller capacitance can clearly be seen in the Vgs ripple, rising slightly with each positive going current pulse, causing associated Vds rise to be suppressed/delayed, whereas the fall in Ids causes a simultaneous fall in Vgs and Vds. After Ids reaches zero, Vgs recovers from its negative dip in around 5 ms, returning to the steady exponential decay curve.

[0127] It will be understood that the above example is not intended to be limiting to the scope of protection, For instance, while the example uses MOSFETs as the SSPIRs a bipolar transistor could be used. In that case, rather than varying the gate voltage the control means would vary the base current. This could be easily achieved using the circuit shown by a small modification in which the reservoir capacitor supplies the base current through a resistor. Any reference to gradually dropping the gate voltage may therefore be replaced as an equivalent by reference to gradually dropping the gate current.

[0128] The principle and mode of operation of this invention have been explained and illustrated in its preferred embodiment. However, it must be understood that this invention may be practiced otherwise than as specifically explained and illustrated without departing from its spirit or scope.