CIRCUITRY FOR USE IN COMPARATORS

Abstract

There is disclosed herein charge-mode circuitry for use in a comparator to capture a difference between magnitudes of first and second input signals, the circuitry comprising: a tail node configured during a capture operation to receive a charge packet; first and second nodes conductively connectable to said tail node along respective first and second paths; and control circuitry configured during the capture operation to control such connections between the tail node and the first and second nodes based on the first and second input signals such that said charge packet is divided between said first and second paths in dependence upon the difference between magnitudes of the first and second input signals.

Claims

1. Charge-mode circuitry for use in a comparator to capture a difference between magnitudes of first and second input signals, the circuitry comprising: a tail node configured during a capture operation to receive a charge packet; first and second nodes conductively connectable to said tail node along respective first and second paths; and control circuitry configured during the capture operation to control such connections between the tail node and the first and second nodes based on the first and second input signals such that said charge packet is divided between said first and second paths in dependence upon the difference between magnitudes of the first and second input signals.

2. The charge-mode circuitry according to claim 1, wherein: the input signals are voltage-mode signals and the magnitudes are voltage levels; or the input signals are current-mode signals and the magnitudes are values of current; or the input signals are charge-mode signals and the magnitudes are amounts of charge; or the first and second input signals are analogue signals.

3. The charge-mode circuitry according to claim 1, wherein the control circuitry comprises switching circuitry provided along said paths, the switching circuitry configured such that the conductivity of the connections between the tail node and the first and second nodes is controlled by the magnitudes of the first and second input signals.

4. The charge-mode circuitry according to claim 3, wherein the switching circuitry comprises a first transistor whose channel forms part of the first path and a second transistor whose channel forms part of the second path, and wherein gate terminals of those transistors are controlled by the first and second input signals.

5. The charge-mode circuitry according to claim 1, wherein the control circuitry is configured to cause the charge packet to be divided so that portions thereof pass simultaneously along said first and second paths, the relative size of those portions being dependent on the difference between the magnitudes of the first and second input signals.

6. The charge-mode circuitry according to claim 1, comprising a controllable charge pump configured to provide said charge packet during said capture operation.

7. The charge-mode circuitry according to claim 6, wherein the controllable charge pump is configured such that said charge packet has a given or predetermined size.

8. The charge-mode circuitry according to claim 7, wherein: the controllable charge pump is configured to control said given or predetermined size; and/or the given or predetermined size is such that voltage levels at said first and second nodes settle at first and second different values during the capture operation in dependence upon the difference between magnitudes of the first and second input signals.

9. The charge-mode circuitry according to claim 6, wherein the controllable charge pump is connected such that said charge packet is delivered to the tail node during the capture operation.

10. The charge-mode circuitry according to claim 6, wherein said controllable charge pump comprises a capacitor and switching circuitry operable to charge said capacitor prior to said capture operation and to discharge said capacitor during said capture operation so as to provide said charge packet.

11. The charge-mode circuitry according to claim 1, connected to receive a clock signal and configured to perform said capture operation based upon said clock signal.

12. A comparator comprising the charge-mode circuitry according to claim 1.

13. The comparator according to claim 12, comprising differential-input dynamic or clocked latch circuitry, such as strongARM latch circuitry, the latch circuitry connected to receive its inputs from said charge-mode circuitry, optionally from said first and second nodes of the charge-mode circuitry.

14. Analogue-to-digital converter circuitry, comprising the charge-mode circuitry according to claim 1.

15. An IC chip, comprising the charge-mode circuitry according to claim 1.

16. Analogue-to-digital converter circuitry, comprising the comparator according to claim 12.

17. An IC Chip, comprising the comparator according to claim 12.

18. An IC Chip, comprising the analogue-to-digital converter circuitry according to claim 14.

Description

[0045] Reference will now be made, by way of example, to the accompanying drawings, of which:

[0046] FIG. 1, as mentioned above, is a schematic diagram of analogue-to-digital circuitry, to which the invention may be applied;

[0047] FIG. 2, as mentioned above, is a schematic diagram useful for understanding the principle of operation of ADC units of the FIG. 1 ADC banks;

[0048] FIG. 3, as mentioned above, is a schematic diagram useful for understanding a possible application of SAR-ADC circuitry within each sub-ADC unit of FIG. 2;

[0049] FIG. 4, as mentioned above, is a schematic diagram of example SAR ADC circuitry which may be employed with the circuitry of FIGS. 1 and 2, as part of the sub-ADC units;

[0050] FIG. 5 is a schematic diagram of previously-considered example clocked comparator circuitry;

[0051] FIG. 6 is a schematic diagram of previously-considered example clocked pre-amplifier circuitry for use with the circuitry of FIG. 5;

[0052] FIG. 7 is a schematic diagram of clocked pre-amplifier circuitry embodying the present invention;

[0053] FIG. 8 is a graph useful for understanding the operation of the FIG. 7 circuitry; and

[0054] FIG. 9 is a schematic diagram of clocked pre-amplifier circuitry embodying the present invention.

[0055] FIG. 5 is a schematic diagram of previously-considered example clocked comparator circuitry 300. Clocked comparator circuitry 300 may be referred to as latched comparator circuitry 300, and may be compared to latch circuitry known generically as a strongARM latch. The operation of the circuitry can be understood by the graphs provided and alongside and commented on in more detail below.

[0056] Circuitry 300 comprises a differential pair of input transistors 302 and 304, two cross-coupled pairs of transistors 306, 308, 310 and 312, output nodes 314 and 316, intermediate nodes 318, 320, a first reference voltage source 322, a tail node 324, clocked precharge transistors 326 and 328, a clocked “compare” transistor 330 and a second reference voltage source 332, connected together as in FIG. 5.

[0057] More specifically, the differential pair of input transistors 302 and 304 are connected such that their gate terminals serve as a pair of differential inputs receiving input signals IN and /IN. These are the two comparator inputs to be compared to one another (see e.g. the two inputs to comparator 180 in FIG. 4).

[0058] The two cross-coupled pairs of transistors 306, 308, 310, 312 are coupled to form two cross-coupled inverters, with transistors 306 and 310 forming one of the inverters with its output connected to output node 314, and with transistors 308 and 312 forming the other one of the inverters with its output connected to output node 316. The inverter formed by transistors 306 and 310 is connected between the intermediate node 318 and the first reference voltage source 322, in this case VDD. The inverter formed by transistors 308 and 312 is connected between the intermediate node 320 and the first reference voltage source 322. The outputs of the inverters provide the outputs, at output nodes 314 and 316, of the comparator circuitry 300.

[0059] The differential pair of input transistors 302 and 304 are connected respectively between the intermediate nodes 318 and 320 and the common tail node 324.

[0060] The precharge (or reset) transistors 326 and 328 are respectively connected between the output nodes 314 and 316 and the first reference voltage source 322. The compare (or regeneration) transistor 330 is connected between the common tail node 324 and the second reference voltage source 332, in this case ground (GND). The precharge transistors 326 and 328 and the compare transistor 330 are connected to receive a clock signal CLK, in this case a switched logic level (e.g. square wave) signal alternating between logic high (VDD) and logic low (GND), as indicated in the relevant graph.

[0061] The transistors 302, 304, 306, 308 and 330 are NMOS MOSFETs, and the transistors 310, 312, 326 and 328 are PMOS MOSFETs.

[0062] In operation, the circuitry operates in alternating “reset” (when clock signal CLK is low) and “regeneration” (when clock signal CLK is high) phases in synchronisation with the clock signal CLK, as will be appreciated from the graphs in FIG. 5. Regeneration phases may be referred to as “compare” or, particularly in the light of circuitry disclosed later herein, as “capture” phases.

[0063] In the “reset” phase when the clock signal CLK is low, the precharge transistors 326 and 328 are on and pull the output nodes 314 and 316 to logic high or VDD. At this time, the compare transistor 330 is off, preventing current from flowing through e.g. the intermediate nodes 318 and 320.

[0064] As soon as the clock signal CLK goes high for the regeneration phase, the precharge transistors 326 and 328 turn off and the compare transistor 330 turns on. Importantly, the input transistors 302 and 304 are also on to a differing degree if their input signals (the comparator inputs) are slightly different from one another, as they inevitably would be (if only slightly).

[0065] The voltage levels at output nodes 314 and 316 fall as the current begins to flow, but because the transistors 302 and 304 are inevitably on to differing degrees (in practice they will not be on to exactly the same degree) the differing currents flowing through the intermediate nodes 318 and 320 cause one of these voltages to drop (perhaps only slightly) faster than the other. The cross-coupled inverters serve to accelerate and amplify this difference (in the sense of increasing the difference, at an increasing rate) causing the voltage level at one of the output nodes to drop to logic low or ground (GND) and the voltage level at the other output node to rise again to logic high or VDD. This operation, and the associated flow of current through common tail node 324, can be appreciated from the graphs in FIG. 5.

[0066] Which of the output nodes 314 and 316 goes to logic high and which goes to logic low depends on (in the ideal case, in the absence of e.g. noise) which of the input signals IN and /IN is larger, so that the voltage levels of the output signals OUT and /OUT provide the comparison result at the end of that regeneration phase. The accuracy of the circuitry 300 is therefore dependent on the correct “decision” being taken when the voltage levels at the output nodes 314 and 316 diverge under acceleration of the cross-coupled inverters.

[0067] Of course, when the next “reset” phase starts i.e. when the clock signal CLK goes low, the precharge transistors 326 and 328 turn back on and the compare transistor 330 turns back off, stopping the flow of current (such that there is no static current) and precharging the output nodes 314 and 316 to logic high or VDD again.

[0068] It will therefore be appreciated that the clocked comparator circuitry 300 serves to perform a comparison operation per clock cycle, in particular during each regeneration phase when the clock signal CLK is high, the comparison operation comparing the voltage levels of the input signals IN and /IN at that time and giving output signals OUT and /OUT which are either logic high and logic low or vice versa depending (ideally) on which of the input signals IN and /IN has the higher voltage level.

[0069] As explained above, this action is dominated by the cross-coupled inverters in the upper half of the circuitry 300. Based on the difference between the input signals IN and /IN, one of the inverters will start pulling in a particular direction slightly quicker than the other because of the difference between the currents which initially flow through the transistors 302 and 304 at the input. This will cause the two inverters to accelerate/amplify the difference between the two sides, with their outputs rapidly diverging. Like CMOS inverter circuitry the supply current only flows while the circuitry is active.

[0070] The circuitry 300 has disadvantages. The inventors have in particular considered desired high-speed operation, for example with each regeneration phase lasting only 10 to 50 ps. They have also considered low power operation, e.g. with VDD being 1V or even lower. A challenge is that for the input transistors 302 and 304 to be low-noise contributors they would be sized to be relatively big, however this slows their operation (high capacitance).

[0071] The circuitry 300 may be considered to have the following disadvantages, namely: (1) it is sensitive to common-mode input voltage; (2) it is sensitive to variation in device V.sub.TH—for example, in respect of the input transistors 302 and 304; (3) it has relatively poor noise performance—many transistors contribute to the noise, with those transistors being small in order to switch quickly; and (4) it is sensitive to changes in the input signals IN and /IN after the clock edge.

[0072] FIG. 6 is a schematic diagram of previously-considered example clocked pre-amplifier circuitry 400, for use with the clocked comparator circuitry 300. The operation of this circuitry 400 can be understood from the graphs provided alongside and commented on in more detail below, as for circuitry 300.

[0073] Circuitry 400 comprises a differential pair of input transistors 402 and 404, a common tail node 406, intermediate nodes 408 and 410, clocked transistors 412, 414 and 416, a first reference voltage source 418 and a second reference voltage source 420, connected together as in FIG. 6.

[0074] More specifically, the differential pair of input transistors 402 and 404 are connected such that their gate terminals serve as a pair of differential inputs receiving input signals IN and /IN. As before, these are the two comparator inputs to be compared with one another (see e.g. the two inputs to comparator 180 in FIG. 4). However, the clocked pre-amplifier circuitry 400 is for use with the clocked comparator circuitry 300 such that the output signals OUT and /OUT of the circuitry 400 (mentioned below) become the input signals IN and /IN in circuitry 300.

[0075] The input transistors 402 and 404 are connected between the common tail node 406 and the intermediate nodes 408 and 410, respectively. The clocked transistors 412 and 414 are respectively connected between the intermediate nodes 408 and 410 and the second reference voltage source 420, in this case ground (GND). The clocked transistor 416 is connected between the common tail node 406 and the first reference voltage source 418, in this case VDD. The ground and VDD levels between circuitry 300 and 400 may be the same but this is of course not essential.

[0076] The clocked transistors 412, 414 and 416 are connected to receive the clock signal /CLK, i.e. the inverse of the clock signal CLK in FIG. 5. Transistors 412 and 414 are NMOS MOSFETs and transistors 402, 404 and 416 are PMOS MOSFETs.

[0077] The intermediate nodes 408 and 410 provide the output signals OUT and /OUT to the transistors 304 and 302 in FIG. 5 as already mentioned.

[0078] In operation, the circuitry 400 operates based on the clock signal /CLK and thus for ease of comparison the “reset” and “regeneration” phases from FIG. 5 are shown for the graphs of FIG. 6. Note that both “ideal” and “actual” cases are indicated for the output signals OUT and /OUT (V.sub.OUT). The “actual” case corresponds to the circuitry 400 and the “ideal” case will be commented on later in connection with FIGS. 7 to 9.

[0079] In the “reset” phase, when the clock signal /CLK is high (and the clock signal CLK is low), the clocked transistors 412 and 414 are off and the clocked transistor 416 is on. Thus, as with a CMOS inverter, the output signals OUT and /OUT at nodes 408 and 410 are at logic low or ground (GND). In the “regeneration” phase, when the clock signal /CLK is low, the clocked transistors 412 and 414 are off and the clocked transistor 416 is on. Thus, again in line with a CMOS inverter, the output signals OUT and /OUT at nodes 408 and 410 both rise up to logic high or VDD.

[0080] The voltage levels of the input signals IN and /IN control the degree to which transistors 402 and 404 are on, and during the regeneration phase this controls the current flowing through nodes 408 and 410 and consequently how quickly the voltage levels at those nodes rise up to logic high, i.e. up to the same voltage level. An example is shown in the “actual” graph in FIG. 10, with the output signal /OUT rising up to VDD quicker than the output signal OUT, and with there being a corresponding difference in voltage ΔV.sub.OUT between these output signals OUT and /OUT for the short period of time indicated in the lower-most graph. This period could for example be as short as 10 ps, given the example regeneration phase of only 10-50 ps mentioned earlier. It will be appreciated that the clocked pre-amplifier circuitry 400 can provide an amplified voltage difference ΔV.sub.OUT at the input terminals (i.e. between input signals IN and /IN) of the circuitry 300 of FIG. 5, i.e. bigger than the voltage difference between the input signals IN and /IN of the circuitry 400 of FIG. 6 which would otherwise be provided directly to the circuitry 300 (i.e. in the absence of circuitry 400). This amplification provides some noise performance benefit, but there are disadvantages.

[0081] These advantages and disadvantages will now be explored further.

[0082] An advantage of the clocked pre-amplifier circuitry 400 of FIG. 6 is that its gain has a knock-on effect of a noise reduction in the overall circuitry including the circuitry 300 of FIG. 5 and the circuitry 400 of FIG. 6. For example, a gain of 3 in the clocked pre-amplifier circuitry 400 would lead to a noise reduction of the latch circuitry 300 by a factor of 3. Also, the PMOS transistors 402 and 404 at the inputs of the FIG. 6 circuitry 400 can be made big (low noise) without slowing down the regeneration.

[0083] Disadvantages associated with the FIG. 6 circuitry are indicated in the graphs on the right-hand side of FIG. 6.

[0084] In the “ideal” case, the output signals OUT and /OUT would rise (with gain) dependent on the input signals IN and /IN when the clock signal /CLK goes low, and then maintain their values until the subsequent rising clock edge. However, because the uppermost PMOS transistor 416 stays on when the clock signal /CLK is low, the “actual” situation corresponding to circuitry 400 as mentioned above is that the output signals OUT and /OUT rise quickly up to logic high or VDD (i.e. such that they settle at the same voltage levels) with some variation in how quickly this occurs dependent on the current flowing through the uppermost PMOS transistor 416 (i.e. dependent on the common mode voltage V.sub.CM, the threshold voltages V.sub.TH of the input NMOS transistors or switches 402 and 404 and the threshold voltage V.sub.TH of the uppermost PMOS transistor 416). Example “fast” and “slow” cases are indicated in the “actual” graph in FIG. 10.

[0085] Thus, the amplified ΔV.sub.OUT signal (difference between the output signals OUT and /OUT) as indicated in the lower most graph in FIG. 6 may indicate a difference only for a very short period of time (e.g. 10 ps) before it indicates no difference at all, with that profile varying with how quickly the output signals OUT and /OUT are pulled to logic high or VDD. This voltage then may have disappeared before the latch circuitry 300 of FIG. 5 has had time to respond to it by regenerating. This also means that the effective pre-amplifier gain of the circuitry 400 has fallen so that it no longer reduces the noise of the latch circuitry 300.

[0086] Thus, although the FIG. 6 circuitry helps to address the disadvantages (3) and (4) discussed above, it brings with it its own disadvantages (e.g. a disadvantage (5) being that the voltage difference ΔV between the input signals IN and /IN of circuitry 300 disappears as ΔV.sub.OUT disappears for circuitry 400) and the disadvantages (1) and (2) discussed above remain.

[0087] FIG. 7 is a schematic diagram of improved clocked pre-amplifier circuitry 500 embodying the present invention. The operation of this circuitry 500 can be understood from the graph of FIG. 8 described below. It will be noted that the graph of FIG. 8 is similar to the “ideal” case shown in FIG. 6.

[0088] Circuitry 500 is similar to circuitry 400, and thus like elements are denoted in the same way and duplicate description is omitted. Circuitry 500 differs from circuitry 400 in that the clocked transistor 416 has been replaced with a clocked unit 502 which has a charge pump and reset function.

[0089] The general idea is to meter the charge during the regeneration phases which is then split at the common tail node 406 based on the input signals IN and /IN, so that the output voltages of the output signals OUT and /OUT at the nodes 408 and 410 will rise up to around a given “designed” target level and not continue to rise up to VDD. This is indicated in FIG. 8, with the output signals OUT and /OUT rising up towards VDD but levelling out either side of a midline value at which both would be expected to level out if the input signals IN and /IN are equal. A clocked charge pump is schematically shown by way of unit 502 connected between the common tail node 406 and the first reference voltage source 418, i.e. VDD. This unit 502 also has the function to reset the voltage at the common tail node 406 in the reset phases.

[0090] As indicated in FIG. 7, it is possible to design the charge pump aspect of unit 502 to deliver a fixed amount of charge 2Qin, understanding that if this charge splits equally at the tail node than an amount of charge Qin will be delivered to the outputs OUT and /OUT and generate a voltage (V.sub.OUT=Q.sub.IN/C.sub.PARASITIC) over the effective parasitic capacitances (C.sub.PARASITIC) of the inputs to the latch circuitry 300. This would correspond to both of the output signals OUT and /OUT levelling out at the midline value mentioned above. This fixed amount of charge 2Q.sub.IN could for example be designed to deliver midline value V.sub.OUT=circa 0.7 VDD, or whatever voltage is optimum for the best operation of the latch circuitry 300 of FIG. 5.

[0091] Naturally, with the difference between the input signals IN and /IN, the charge 2Q.sub.IN would not split equally at the common tail node 406 leading to a ΔV.sub.OUT (difference between the output signals OUT and /OUT as indicated in FIG. 8. That is, the voltage levels of output signals OUT and /OUT settle at different values dependent on the input signals IN and /IN. Advantageously, this ΔV.sub.OUT is maintained or held because the output signals OUT and /OUT do not continue to rise to VDD as in the “actual” case in FIG. 6. Also, because the circuitry operates based on splitting charge rather than current per se, it is not sensitive to common mode voltage V.sub.CM and threshold voltage V.sub.TH. Thus, this circuitry addresses all of the disadvantages (1) to (5) discussed above.

[0092] FIG. 9 is a schematic diagram of clocked pre-amplifier circuitry 600 corresponding to the circuitry 500 of FIG. 7. The operation of this circuitry also corresponds to that shown in FIG. 8.

[0093] Circuitry 600 is similar to circuitry 500 and thus like elements are denoted in the same way and duplicate description is omitted. Circuitry 600 differs from circuitry 500 in that an example implementation of clocked unit 502 is explicitly shown.

[0094] Clocked unit 502 of circuitry 600 comprises a capacitor C.sub.PUMP 602 connected between nodes 604 and 606. Node 604 is connected via a “compare” switch 608 to the first reference voltage source 418 “VDD” and via a “reset” switch (RST) 610 to the second reference voltage source 420 ground (or GND). Node 606 is connected via a “reset” switch 612 to the first reference voltage source 418 and via a “compare” switch 614 to the common tail node 406.

[0095] The “compare” switches are configured to be closed (conductive) during the “regeneration” (“compare” or “capture”) phases and open during the “reset” phases. Conversely, the “reset” (RST) switches are configured to be open during the “regeneration” phases and closed during the “reset” phases. Any suitable arrangement of clocked NMOS or PMOS transistors could be employed to provide the function of such “compare” and “reset” switches.

[0096] During the “reset” (RST) phase, the voltage V.sub.CAP over the capacitor (or capacitance) C.sub.PUMP 602 is equal to VDD because the left- and right-hand ends of the capacitor C.sub.PUMP 602 are effectively connected to ground 420 and VDD 418, respectively. During the “regeneration” phases, the voltage V.sub.CAP becomes V.sub.TAIL minus VDD, where V.sub.TAIL is the voltage at the common tail node 406 (at the end of the regeneration phase), because the left- and right-hand ends of the capacitor C.sub.PUMP 602 are effectively connected to VDD 418 and the common tail node 406, respectively. The value of the capacitor C.sub.PUMP 602 can thus be set to obtain a given charge 2Q.sub.IN as explained before. Also, this value is dominated by VDD, hence the lower sensitivity to threshold voltage V.sub.TH and common mode voltage V.sub.CM.

[0097] Incidentally, the capacitor C.sub.PUMP 602 could be connected via “compare” switch 608 to a separate reference voltage source V.sub.REF (not shown) rather than to VDD 418, and that separate reference voltage source V.sub.REF then adjusted to remove variation in the values of C.sub.PUMP, VDD, V.sub.TH, V.sub.CM, and the second-stage input voltage (i.e. of the latch circuitry 300 of FIG. 5).

[0098] It will be recalled that the circuitry 500 or 600 could be used in conjunction with latch circuitry such as circuitry 300 of FIG. 5 to provide a comparator. Such a comparator may operate without suffering from the problems (1) to (5) mentioned above, and thus is considered advantageous.

[0099] Such a comparator could be employed in ADC circuitry, for example to form a sub-ADC unit suitable for use in the ADC circuitry 40 of FIG. 1. Embodiments of the present invention therefore extend to charge-mode circuitry for capturing a difference between input voltage signals as in the case of circuitry 500 and 600, to comparator circuitry, and to ADC circuitry.

[0100] It will therefore be appreciated that the circuitry disclosed herein could be described as circuitry for use in a comparator, as a comparator itself, or as an ADC. Circuitry of the present invention may be implemented as integrated circuitry, for example on an IC chip such as a flip chip. The present invention extends to integrated circuitry and IC chips as mentioned above, circuit boards comprising such IC chips, and communication networks (for example, internet fiber-optic networks and wireless networks) and network equipment of such networks, comprising such circuit boards.

[0101] The present invention may be embodied in many different ways in the light of the above disclosure, within the spirit and scope of the appended claims.