CLOCK GENERATION CIRCUITRY

Abstract

There is disclosed herein clock generation circuitry, in particular rotary travelling wave oscillator circuitry. Such circuitry comprises a pair of signal lines connected together to form a dosed loop and arranged such that they define at least one transition section where both said lines in a first portion of the pair cross from one lateral side of both said lines in a second portion of the pair to the other lateral side of both said lines in the second portion of the pair.

Claims

1. Rotary travelling wave oscillator circuitry, comprising a pair of signal lines connected together to form a closed loop and arranged such that they define at least one transition section where both said lines in a first portion of the pair cross from one lateral side of both said lines in a second portion of the pair to the other lateral side of both said lines in the second portion of the pair.

2. The rotary travelling wave oscillator according to claim 1, wherein at the transition section the lines in the first portion cross the lines in the second portion without interconnection therebetween.

3. The rotary travelling wave oscillator circuitry according to claim 1, wherein the pair of signal lines both follow a continuous path which crosses itself at the transition section.

4. The rotary wave travelling oscillator circuitry according to claim 3, wherein: the path defines a figure-of-eight shape; and the transition section is at the crossover section of the figure-of eight shape.

5. The rotary travelling wave oscillator circuitry according to claim 1, wherein the pair of signal lines are generally arranged alongside or parallel to each other.

6. The rotary travelling wave oscillator circuitry according to claim 1, wherein the pair of signal lines is a set of differential transmission lines.

7. The rotary travelling wave oscillator circuitry according to claim 1, wherein at the transition section both said lines in the first portion are substantially perpendicular to both said lines in the second portion.

8. The rotary travelling wave oscillator circuitry according to claim 1, wherein the transition section is arranged so that each signal line in the first portion crosses over one signal line in the second portion and under the other signal line in the second portion.

9. The rotary travelling wave oscillator circuitry according to claim 1, wherein the pair of signal lines are configured in a balanced arrangement such that a travelling wave travelling around the closed loop would spend equal amounts of time either side of the transition section.

10. The rotary travelling wave oscillator circuitry according to claim 1, wherein the pair of signal lines are configured in a symmetrical arrangement such that a set of relative phases 0°, 90°, 180° and 270° of a travelling wave travelling around the closed loop would occur at a corresponding set of virtual points along the signal lines which fall on a straight virtual line.

11. The rotary travelling wave oscillator circuitry according to claim 10, wherein the symmetrical arrangement is such that it provides a plurality of said sets of virtual points, each said set of virtual points being on their own straight virtual line, the straight virtual lines being generally parallel with one another, optionally wherein sections of said signal line, running through said parallel straight virtual lines at the corresponding virtual points are arranged parallel to one another and perpendicular to those virtual lines.

12. The rotary travelling wave oscillator circuitry according to claim 9, wherein said signal lines are configured to have uniform properties along their lengths, and wherein said balanced and/or symmetrical arrangements are defined based on lengths of said signal lines and their relative spatial layout.

13. The rotary travelling wave oscillator circuitry according to claim 1, wherein the closed loop is substantially symmetrical about the transition section.

14. Digital-to-analogue converter circuitry or analogue-to-digital converter circuitry, comprising the rotary travelling wave oscillator circuitry according to claim 1.

15. An IC chip, comprising the rotary traveling wave oscillator circuitry of claim 1.

16. An IC chip, comprising the digital-to-analogue converter circuitry or analogue-to-digital converter circuitry of claim 14.

17. The IC chip of claim 15, wherein the IC chip comprises a flip chip.

18. The IC chip of claim 16, wherein the IC chip comprises a flip chip.

Description

[0033] Reference will now be made, by way of example, to the accompanying drawings, of which:

[0034] FIG. 1, as described hereinabove, shows the known methods for quadrature clock generation;

[0035] FIG. 2, is a schematic diagram of an example RTWO;

[0036] FIG. 3 is a schematic diagram representing RTWO circuitry according to a general embodiment of the present invention;

[0037] FIG. 4 is a schematic diagram showing an enlarged view of the real connection section and dummy connection section according to an embodiment of the present invention;

[0038] FIG. 5 is a schematic diagram showing an enlarged view of the transition section according to an embodiment of the present invention;

[0039] FIG. 6 is a schematic diagram showing exemplary locations at which quadrature clock signals may be taken from the RTWO circuitry of FIGS. 3 to 5; and

[0040] FIG. 7 is a schematic diagram representing RTWO circuitry according to another embodiment of the present invention.

[0041] The present inventors have studied circuitry corresponding to the methods A, B and C of FIG. 1. However, they have identified the rather distant rotary travelling wave oscillator (RTWO) as being suitable for quadrature signal generation with the above-mentioned ADC and DAC circuitry in mind.

[0042] FIG. 2 is a schematic diagram of an example RTWO 1 for generating quadrature phase signals. RTWO 1 comprises a pair of signal lines 2 and 3 and a number of regeneration elements 4.

[0043] Signal line 2 has ends A and B and signal line 3 has ends C and D. The signal lines 2 and 3 are connected end-to-end, i.e. with end B connected to end C and end D connected to end A, to form a closed or endless loop of signal line. It will be appreciated that such signal lines may be implemented as (ideally, lossless) transmission lines, and the present disclosure will be understood accordingly.

[0044] Note that the pair of signal lines 2 and 3 generally follow a path 5 which itself forms an endless loop. Thus, the loop of signal line (the signal-line loop) effectively travels twice around the loop defined by the path 5 (the path loop 5).

[0045] The circuitry essentially corresponds to an open loop of differential signal line, i.e. running from ends A and C round to ends B and D, but with the ends cross-connected at cross-connection section 7 such that the signal line becomes an endless or closed loop of signal line. If the cross-connection section 7 were removed and a voltage applied over one of the two ends of the differential line, e.g. across the ends A and C, a voltage wave would begin to travel around the loop to ends B and D. With the cross-connection section 7 in place, and if there were no losses, the wave (consider e.g. a rising edge) would travel around the signal-line loop indefinitely, providing a full clock cycle every time the wave returns to its starting point.

[0046] To counter the losses, multiple regeneration elements 4 are distributed at locations around the path loop and are connected between the adjacent lines. The regeneration elements 4 may be or comprise antiparallel inverter pairs (as indicated in FIG. 2), which effectively provide gain and drive the travelling wave, overcoming the losses and helping lock the rotation. At any point on the path loop 5 whilst a wave is travelling around the signal-line loop, the intention is that if signals were taken or tapped from the two adjacent conductors of the signal lines 2 and 3 at that point then those signals would be 180° out of phase with one another (supported by the antiparallel inverter pairs). Therefore, with a voltage-signal wave travelling around the loop, a differential clock signal is available at any point on the path loop 5 (i.e. by taking or tapping signals from the adjacent signal lines 2 and 3 at that point).

[0047] An advantage of such circuitry is that it can operate at the desired frequency (i.e. 1F), and that there is no need to add circuits to deal with phase error or to suffer their associated power penalty. The frequency of the clock signal can be determined by the electrical size of the signal-line loop, i.e. how long it takes for the travelling wave to complete a lap of the signal-line loop, given that loop's signal line characteristics. Typically, the signal line would have uniform properties along its length so that the length of the line is proportional to the clock frequency.

[0048] The phase of a wave travelling around the signal line completes one 360° cycle from one point on the signal line round to the same point on the signal line. From a starting point at 0°, the phase of the travelling wave will increase as it moves around the loop, before reaching 360°/0° again. Thus, it is possible to obtain a quadrature clock signal by taking clock signals at different points on the signal-line loop.

[0049] Since the phase difference between clock signals taken from adjacent signal lines 2 and 3 at any point on the path loop is 180° and one full cycle of the signal-line loop (i.e. two laps of the path loop 5) is 360°, the points directly opposite each other on the path loop 5 will be 90° out of phase. Therefore, in order to obtain quadrature clock signals, two clock signals (for example, 0° and 180°) must be taken from one side of the path loop 5 and the other two clock signals (for example, 90° and 270°) must be taken from the opposite side of the path loop 5. FIG. 2 shows two example locations along the path loop 5 where quadrature clock signals could be taken, however these are simply examples.

[0050] As stated above, the quadrature clock signals need to be taken from opposite sides of the path loop 5 and therefore problems arise when arranging the layout of the RTWO oscillator 1 and other circuitry which operates based on clock signals tapped off that RTWO oscillator 1. For example, it may be necessary for the four clock signals to be input to a single circuitry block, such as the sampler 8 shown in FIG. 2 which corresponds to the sampler disclosed in EP 2 211 468 (see FIGS. 9 and 10 of that document). Therefore, getting the clock signals from opposite sides of the path loop 5 to the same circuitry block causes design problems, not only in the routing of the signal lines or tracks to the intended circuitry block 8, but also in the associated losses, impedances and other characteristics of signal lines of different lengths at high frequencies and the associated impact on the relative phases of those clock signals.

[0051] FIG. 3 is a schematic diagram of RTWO circuitry 10 embodying the present invention. For ease of comparison, those elements of RTWO circuitry 10 having corresponding elements in FIG. 2 are denoted in the same way. Thus, the RTWO circuitry 10 comprises a pair of signal lines 2 and 3 and a number of regeneration elements 4 (shown simply as boxes). Signal line 2 has ends A and B and signal line 3 has ends C and D, as in FIG. 2. The signal lines 2 and 3 are also connected end-to-end as in FIG. 2, i.e. with the end B connected to end C and end D connected to end A, to form a closed or endless loop of signal line. Again, such signal lines may be implemented as (ideally, lossless) transmission lines and the present disclosure will be understood accordingly.

[0052] Similarly to the RTWO circuitry 1 of FIG. 2, note that the pair of signal lines 2 and 3 in the RTWO circuitry 10 of FIG. 3 generally follow a path 5 which itself forms an endless loop. Thus, the loop of signal line (the signal-line loop) effectively travels around the loop defined by the path 5 (the path loop 5). However, note that the path 5 of the RTWO circuitry 10 defines a figure-of-eight shape, i.e. an “8” shape, in that the path 5 crosses itself forming two half path-loops.

[0053] The closed signal-line loop is arranged to have a transition section 15 at which both signal lines 2 and 3 of the closed signal-line loop in a first portion of the pair make a transition from or cross from one lateral side of both signal lines in a second portion of the pair to the other lateral side of both signal lines in that second portion of the pair, as can be seen from FIG. 3. Thus, the closed signal-line loop of the RTWO circuitry 10 is arranged so that both signal lines 2 and 3 pass across each other at the transition section 15.

[0054] In the RTWO circuitry 10 in FIG. 3, the pair of signal lines 2 and 3 thus both generally follow the path 5 which defines a figure-of-eight shape, with the transition section 15 at the crossover section of the path 5. At the transition section 15, the signal lines in the first portion do not interconnect or cross-connect with the signal lines in the second portion. That is, although the signal lines 2 and 3 pass across each other, there is no electrical (i.e. conductive) interconnection and the closed signal-line loop in the present embodiment is a single continuous loop in the same sense as in FIG. 2, with no interruptions.

[0055] To avoid such cross-connection at the transition section, the crossings in the transition section involve one of the lines going over or under the line it is crossing, with the crossing lines insulated from one another at that point, for example using multiple metal layers in integrated circuitry having a layered structure. Such metal layers are typically separated by via layers, and are thus insulated from each other except for where vias are formed. A possible configuration will be explored in more detail below.

[0056] As with the RTWO of FIG. 2, the signal lines 2 and 3 in the RTWO circuitry 10 interconnect at the connection section 7 which appears in FIG. 3 at the top. This is the only point in the path loop 5 at which the two signal lines 2 and 3 (the two conductors of the corresponding transmission lines) interconnect in the circuitry 10. This is in order to create the closed or endless signal-line loop as discussed above and respect the basic operation of an RTWO. A number of regeneration elements 4 are located around the path loop 5 as indicated schematically in FIG. 3, as for the RTWO of FIG. 2. As discussed above, these regeneration elements 4 counter the losses in the signal-line loop and may be, for example, antiparallel inverter pairs. For simplicity, the regeneration elements 4 are represented in FIG. 3 as boxes as already mentioned. Their exact number and location is not critical to the present invention. It would be known to a person skilled in the art that an RTWO would comprise one or more regeneration elements 4, located between the conductors of the signal lines 2 and 3.

[0057] In order to keep the lengths of transmission line (signal line) in the two half loops of the path 5 the same and thus provide symmetry to the arrangement, a “dummy” cross-connection section 16 may be provided in the half path loop not containing the “real” cross-connection section 7. In the case of FIG. 3, this is shown in the lower half path loop. The “dummy” cross-connection section 16 corresponds to the “real” cross-connection section 7 and may therefore be located in the corresponding position in the other half loop, i.e. opposite the “real” cross-connection section 7 about the horizontal dashed line of symmetry shown in FIG. 3. Note that another line of symmetry could also be drawn passing vertically through the transition section 15 and passing through both the “real” and “dummy” cross-connection sections 7 and 16.

[0058] Note that there is no actual cross-connection in the “dummy” cross-connection section 16, hence the name. The lengths of the wires in the “dummy” cross-connection section 16 are configured to be the same as the length of the wires in the “real” cross-connection section 7, again to enable the overall circuitry 10 to have a generally symmetrical layout.

[0059] FIG. 4 is a schematic diagram showing an enlarged view of the real cross-connection section 7 and the “dummy” cross-connection section 16 of FIG. 3. As can be seen from FIG. 4, the signal wires do not actually cross over one another or interconnect at the “dummy” cross-connection section 16 and the arrangement merely replicates the general arrangement of the “real” cross-connection section 7 without the conductors connecting or crossing over one another. Although the signal lines 2 and 3 are shown as curving inwardly towards one another in the dummy cross-connection section 16 in FIGS. 3 and 4, those signal lines could for example curve outwardly or away from one another instead, and achieve the same overall effect of keeping the lengths of signal line the same and thus the symmetry of the overall arrangement. Other variations are of course possible.

[0060] The transition section 15 may be implemented as shown in FIG. 5, which is a schematic diagram showing an enlarged view of the transition section 15. As can be seen from FIG. 5, each signal-line conductor in the first portion passes over one conductor in the second portion and passes under the other conductor in the second portion. In FIG. 5, the first portion of the pair of signal lines 2 and 3 is denoted by line portions 21 and 22 and the second portion of the pair of signal lines 2 and 3 is denoted by the line portions 23 and 24. This arrangement provides symmetry in the transition section 15 and ensures that the length of the conductors in the first portion are the same as each other and are the same as the length of each of the conductors in the second portion. Furthermore, the ‘one over, one under’ arrangement keeps the parasitic capacitances to substrate and between lines the same for each conductor and crossing point.

[0061] As can be seen from FIG. 3, one advantage of the arrangement according to a general embodiment of the present invention is that quadrature clock signals can be taken from the same side of the arrangement, i.e. signals mutually 90° out of phase with each other can be taken from a set of points in the same physical location of the arrangement or in locations very close to each other. If one imagines moving the indicated points (0°, 90°, 180° and 270°) together in the same direction forwards around the loop (for example, in the direction indicated by the arrows 17), one will notice that they come together towards the centrally located transition section 15, at which point they may appear together along the same imaginary vertical line.

[0062] Thus, arranging the RTWO circuitry 10 with a transition section 15 and with the signal lines symmetrically arranged as in FIG. 3, enables sets of points to be next to or close to each other whereas in FIG. 2 they would be on opposite sides of the closed path loop.

[0063] FIG. 6 is another schematic diagram of the RTWO circuitry 10, provided to show a number of example sets of points at which quadrature clock signals may be taken from the RTWO circuitry 10. A number of virtual lines 61 to 64 are shown in FIG. 6 simply as examples of possible locations at which sets of points exist where signals that are mutually 90° out of phase may be found along the same vertical line. Each such line 61 to 64 has a set of four points indicated on it at which quadrature clock signals can be found. For example, where line 61 intersects the closed loop of signal line there are four indicated points 611, 612, 613 and 614, with the four points on each of the other lines 62 to 64 being denoted in a similar manner. Clock signals 90° apart in phase may be taken from these points, such as, for example 0° at point 631, 90° at point 633, 180° at point 632 and 270° at point 634, for line 63, these phases being relative to one another.

[0064] If one imagines moving these indicated sets of points together in the same direction around the loop of signal line, for example in the direction indicated by the arrows 17, the phases of the signals at those points will increase equally. That is, as the vertical lines are translated sideways over the circuitry 10 the virtual points move around the signal-line loop together, with the relative phases found at those points increasing in the same way as one another. The phase difference between the points will therefore remain at 90°. Thus, the RTWO circuitry 10 shown in FIGS. 3 and 6 in fact offers many locations where quadrature clock signals can be taken from a set of closely or similarly located points or locations.

[0065] Since the quadrature clock signals can be taken from a set of locations that are very close to each other, the design limitations associated with the FIG. 2 RTWO 1 can be overcome. That is, unlike the known RTWO 1, the quadrature signals do not need to be taken from opposite sides of the path loop 5. This means that the design of overall circuitry layout is made easier, particularly with the task in mind of getting a set of four quadrature clock signals to a common circuitry block 8.

[0066] The layout of the resulting circuitry is therefore much better and the problems associated with routing the signal lines (tracks or transmission lines) and the associated losses and impedances, especially at high frequencies, are reduced. The embodiments of the present invention therefore provide improved circuitry for generating quadrature clock signals, since the quadrature clock signals can be taken from the same physical location (or from regularly located locations, such as on straight lines) in the circuitry 10. For example, see the sets of points which fall on vertical straight lines in FIG. 6. Such clock signals may thus be provided to a circuit block such as sampler 8 using signal lines of a similar length and which are laid out in a similar manner (e.g. with those lines running parallel to one another or in a regular array where the lines have the same length, same set of turns, and/or run in the same metal layers, etc., as one another).

[0067] FIG. 7 is a schematic diagram of RTWO circuitry 70 which is similar to the RTWO circuitry 10. Thus, like elements are denoted in the same way.

[0068] As can be seen from FIG. 7, the closed loop of the arrangement is altered to effectively double the height of the arrangement and (more importantly) to double the length of the signal lines. This arrangement, when in use, results in a generated clock signal frequency which is half of that generated using the RTWO circuitry 10 of FIG. 3. The length and arrangement of the signal lines may therefore be readily designed in order to achieve a desired clock frequency, whilst retaining the benefits of the circuitry in FIG. 3 (i.e. the general symmetry and ability to tap off quadrature clock signals at sets of points along parallel vertical lines, those points being available close together towards the transition section).

[0069] The shape of the half path loops of the path 5 may take the form of loops themselves, such as those shown in FIGS. 3 and 7. However, they may of course take the form of other shapes. The shape of the individual half path loops is not as important as the two half path loops being substantially symmetrical (for example, in the sense of the lengths of the signal lines and their arrangement) and the travelling wave taking the same amount of time to travel around each half loop. Indeed, it will be appreciated that the symmetry is more important closer to the transition section 15 where the sets of points mentioned above are close together, and less important particularly far away from the transition section where the sets of points mentioned above are no longer so close together (and thus no longer so attractive from the point of view of supplying a circuit block with a set of quadrature clock signals).

[0070] According to the embodiment shown in FIG. 7, the quadrature signals may still be taken from the same side of the loop as each other. However, the track length is doubled and so the travelling wave takes twice as long to travel around the loop, which in turn halves the frequency of the generated clock signal. This arrangement therefore provides an improved device for generating quadrature signals, with the length of the signal lines being proportional to the frequency of the signals.

[0071] The operating frequency of the RTWO may also be controlled using other methods, such as, for example, using capacitors. One or more capacitance components may be added between the signal lines in order to slow down the travelling waveform and therefore to tune the frequency of the RTWO. Some such capacitance components may be fixed capacitances. Others may be variable capacitors, with some being used to (coarsely) bring the operating frequency close to a target value and the others to fine-tune the operating frequency. This process may be carried out at startup or during runtime, e.g. dynamically.

[0072] Circuitry of the present invention may form part of an analogue-to-digital converter (ADC) and/or a digital-to-analogue converter (DAC). The circuitry may be employed, for example, with the ADC of EP 2 211 468 discussed above. Accordingly, the quadrature signals may be taken from (approximately) the same location of an RTWO according to embodiments of the present invention and then connected to the sampler of EP 2 211 468.

[0073] Circuitry of the present invention may be implemented as integrated circuitry, for example on an IC chip such as a flip chip. The present invention extends to integrated circuitry and IC chips as mentioned above, circuit boards comprising such IC chips, and communication networks (for example, internet fiber-optic networks and wireless networks) and network equipment of such networks, comprising such circuit boards.

[0074] The present invention may be embodied in many other different forms, within the spirit and scope of the appended claims.