Switched-capacitor multilevel inverter with self-voltage-balancing for high-frequency power distribution system

Abstract

Switched capacitor multilevel inverter (SCMLI) configuration for high-frequency medium voltage applications is presented. A 5L-SCMLI basic configuration is further extended to 9L operation with a reduced number of active switches having self voltage boosting and balancing ability. Further, the proposed 9L-SCMLI is extended up to n level being considered as the basic configuration for the extension of horizontal extension (HE) and vertical extension (VE). A generalized switching table is provided for the proposed extensions. Design of the size of capacitor demonstrated for the proposed 9L-SCMLI.

Claims

1. A switched capacitor multilevel inverter (SCMLI) comprising: a single DC power supply providing an input voltage V.sub.dc; a capacitor; first, second and third switches, the DC power supply and the first switch connected in a first circuit branch, the second switch and the capacitor connected in a second circuit branch parallel to the first circuit branch, and the third switch connected between a first junction of the DC power supply and the first switch and a second junction of the second switch and the capacitor to form a boosting circuit in a first bridge circuit configuration; fourth and fifth switches each connected to a third junction of the first switch and the capacitor of the bridge circuit, the fourth and fifth switches forming a third circuit branch; sixth and seventh switches each connected to a fourth junction of the DC power supply and the second switch of the bridge circuit, the sixth and seventh switches forming a fourth circuit branch parallel to the third circuit branch and the boosting circuit connected between the third and fourth junctions in a second circuit configuration; and a load connected between a fifth junction of the fourth and sixth switches and a sixth junction of the fifth and seventh switches, whereby the first to seventh switches are operated to generate a peak output voltage of magnitude twice the input voltage in five distinct voltage levels, wherein the SCMLI only has seven switches which are the first, second third, fourth, fifth, sixth, and seventh switches.

2. A switched capacitor multilevel inverter (SCMLI) comprising: a single DC power supply providing an input voltage V.sub.dc; first and second capacitors connected in series; a first diode connected in series with the DC power supply in a first circuit branch; a first switch connected in series with the series connection of the first and second capacitors in a second circuit branch; a second switch connected between a first junction of the DC power supply and the first diode and a second junction of the first switch and the series connection of the first and second capacitors to form a first bridge circuit configuration; third and fourth switches connected in a third circuit branch, and fifth and sixth switches connected in a fourth circuit branch parallel to the third circuit branch; a load connected between a third junction of the third and fourth switches and a fourth junction of the fifth and sixth switches to form a second bridge circuit configuration; a seventh switch connected between a fifth junction of the first diode and the second capacitor and a sixth junction of the third and fifth switches of the second bridge circuit configuration; and an eighth switch and a second diode connected in series between a seventh junction between the first and second capacitors and the sixth junction, whereby the first to eighth switches are operated to generate a peak output voltage of magnitude twice the input voltage in nine distinct voltage levels, wherein the SCMLI only has eight switches which are the first, second third, fourth, fifth, sixth, seventh, and eighth switches.

3. A switched capacitor multilevel inverter (SCMLI), comprising: a basic structure with a first cell comprising a single DC power supply providing an input voltage V.sub.dc; first and second capacitors connected in series; a first diode connected in series with the DC power supply in a first circuit branch; a first switch connected in series with the series connection of the first and second capacitors in a second circuit branch; a second switch connected between a first junction of the DC power supply and the first diode and a second junction of the first switch and the series connection of the first and second capacitors to form a first bridge circuit configuration; third and fourth switches connected in a third circuit branch, and fifth and sixth switches connected in a fourth circuit branch parallel to the third circuit branch; a load connected between a third junction of the third and fourth switches and a fourth junction of the fifth and sixth switches to form a second bridge circuit configuration; a seventh switch connected between a fifth junction of the first diode and the second capacitor and a sixth junction of the third and fifth switches of the second bridge circuit configuration; and an eighth switch and a second diode connected in series between a seventh junction between the first and second capacitors and the sixth junction, whereby the first to eighth switches are operated to generate a peak output voltage of magnitude twice the input voltage in nine distinct voltage levels, wherein the basic structure only has eight switches which are the first, second third, fourth, fifth, sixth, seventh, and eighth switches, wherein the first and second capacitors, the first diode, the first and second switches, the seventh switch, and the eighth switch and second diode form the first cell; and one or more cells which replicate the first cell of the basic structure to generate a higher number of higher voltage levels in multiple distinct voltage levels, the number of voltage levels being a function of the number of cells.

4. The switched capacitor multilevel inverter (SCMLI) of claim 3, wherein the one or more cells are replicated horizontally.

5. The switched capacitor multilevel inverter (SCMLI) of claim 3, wherein the one or more cells are replicated vertically.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:

(2) FIG. 1 is a schematic diagram of the hybrid 5L SCMLI circuit according the basic implementation of the invention;

(3) FIG. 2 is a schematic diagram of the 9L SCMLI circuit derived from the 5L SCMLI shown in FIG. 1;

(4) FIGS. 3A to 3D are schematic diagrams of the 9L SCMLI circuit of FIG. 2 showing modes of operation for a positive half cycle;

(5) FIG. 4 is a schematic diagram illustrating a horizontal extension (HE) of the 9L SCMLI circuit based on a structural point of view to generate higher number of levels;

(6) FIG. 5 is a schematic diagram illustrating a vertical extension (VE) of the 9L SCMLI circuit based on a structural point of view to generate higher number of levels;

(7) FIG. 6 is a graph illustrating the nine-level output voltage waveform of the 9L SCMLI circuit;

(8) FIGS. 7A to 7C are graphs illustrating variation of optimal capacitance versus resistive load (RL), frequency (f), and phase angle (Φ), respectively;

(9) FIGS. 8A to 8D are schematic diagrams of the equivalent circuit of the 9L SCMLI at different modes;

(10) FIGS. 9A to 9D are bar graphs illustrating power loss comparison at for the 9L SCMLI at a fundamental frequency of f=50 Hz;

(11) FIGS. 10A to 10D are graphs of simulation waveforms of the 9L SCMLI circuit;

(12) FIGS. 11A to 11C are graphs of experimental waveforms of the 9L SCMLI circuit;

(13) FIGS. 12A to 12C are graphs of experimental waveforms of the 9L SCMLI circuit;

(14) FIGS. 13A to 13C are graphs of experimental waveforms of the 9L SCMLI circcuit;

(15) FIGS. 14A and 14B are graphs of experimental waveforms of the 9L SCMLI circuit;

(16) FIGS. 15A to 15C are graphs of experimental waveforms of the 9L SCMLI circuit;

(17) FIGS. 16A to 16D are graphs of experimental waveforms of a 13L SCMLI circuit;

(18) FIGS. 17A to 17C are graphs of experimental waveforms of the 13LSCMILI circuit;

(19) FIG. 18 is a pictorial representation of an experimental prototype model; and

(20) FIG. 19 is a graph illustrating efficiency analysis of the 9L SCMLI w.r.t. to load variation at f=50 Hz.

DETAILED DESCRIPTION THE INVENTION

(21) Referring now to the drawings, and more particularly to FIG. 1, there is shown the basic unit of the hybrid 5L SCMLI circuit according to the invention. It consists of a single DC power supply V.sub.dc, a capacitor C.sub.F, and seven switches S.sub.1 to S.sub.4 and P.sub.1 to P.sub.3 to generate a peak output voltage of magnitudetwice the input voltage. The circuit arrangement is topologically that of a bridge circuit within a bridge circuit. The outer bridge circuit comprises switches S.sub.1 and P.sub.1 in one series arm and switches S.sub.3 and P.sub.3 in a second series parallel arm, with switches S.sub.1 and S.sub.3 connected to a first junction 11 of the bridge, switches P.sub.1 and P.sub.3 connected to a second junction 12 of the bridge, switches S.sub.1 and P.sub.1 connected to a third junction 13 of the bridge, and switches S.sub.3 and P.sub.3 connected to a fourth junction 14 of the bridge. The inner bridge circuit, hereinafter referred to as the boosting circuit, comprises switch S.sub.2 and power supply V.sub.dc in one series arm and capacitor C.sub.F and switch S.sub.4 in a second series parallel arm, with switch S.sub.2 and capacitor C.sub.F each connected to the first junction 11 and power supply V.sub.dc, and switch S.sub.4 each connected to the second junction 12. Switch P.sub.2 is connected between a fifth junction 15 of switch S.sub.2 and power supply V.sub.dc and a sixth junction 16 of capacitor C.sub.r and switch S.sub.4. Finally, a load is connected across the third and fourth junctions 13 an 14 to complete the circuit.

(22) For the 5L SCMLI circuit of FIG. 1, the switching scheme listed in Table 1 includes the state of the diode and capacitor to have a better and quick understanding of the current path for each cycle. At level +1 Vdc, capacitor CF gets charged. Similarly, at level 0 the capacitor CF also gets charged. At level ±2 Vdc capacitor CF is discharging and its voltage remains unchanged for level −1 Vdc. Therefore the 5L SCMLI inverter is equipped with self-voltage balancing and voltage boosting ability with reduced semiconductor elements, decreasing the cost of implementing and as such does not required additional circuitry for balancing capacitor voltage, which reduces the complexity in the converter design.

(23) TABLE-US-00001 TABLE 1 Switching Scheme of 5L SCMLI Voltage Switches Capacitor levels S.sub.1 S.sub.2 S.sub.3 S.sub.4 P.sub.1 P.sub.2 P.sub.3 C.sub.F +1 V.sub.dc 0 1 1 1 1 0 0 C +2 V.sub.dc 0 0 1 0 1 1 0 D  0 1 1 1 1 0 0 0 C −1 V.sub.dc 1 1 0 1 0 0 1 — −2 V.sub.dc 1 0 0 0 0 1 1 D

(24) A 9L SCMLI inverter is shown in FIG. 2, and it is derived from the 5L SCMLI inverter of FIG. 1 by adding an H-bridge in the backend to change the polarity and capacitors are attached in series/parallel to each other to achieve the desired output voltage. The 9L SCMLI inverter topology comprises two parallel bridge circuits and comprises eight switches, two diodes and two capacitors for generating a peak output of twie the input voltage which comprises nine distinct output voltage levels: ±2 V.sub.dc, ±3 V.sub.dc/2, ±V.sub.dc, ±V.sub.dc/2, and 0. The first bridge circuit comprises a first arm of the power supply V.sub.dc connected in series with a diode D.sub.1 and a second parallel arm of a switch S.sub.8 connected in series with two series connected capacitors C.sub.1 and C.sub.2. Diode D.sub.1 and capacitor C.sub.2 are connected to a first junction 21, and power supply V.sub.dc and switch S.sub.8 are connected to a second junction 22. Switch S.sub.1 is connected between a third junction 23 of power supply V.sub.dc and diode D.sub.1 and a fourth junction 24 of switch S.sub.8 and capacitor C.sub.1. The second bridge circuit comprises a first arm of switches S.sub.6 and S.sub.4 connected in series and a second parallel arm of switches S.sub.7 and S.sub.5 connected in series. Switches S.sub.4 and S.sub.5 are connected to a fifth junction 25, while switches S.sub.6 and S.sub.7 are connected to a sixth junction 26. The fifth junction 25 is connected to the first junction 21 via switch S.sub.2, while the sixth junction 26 is directly connected to the second junction 22. In addition, a seventh junction 27 between capacitors C.sub.1 and C.sub.2 is connected to the fifth junction 25 via series connected switch S.sub.3 and diode D.sub.2. Finally, the load is connected between an eighth junction 28 between switches S.sub.4 and S.sub.6 and a ninth junction 29 between switches S.sub.5 and S.sub.7.

(25) The different modes of operation for the 9L SCMLI inverter shown in FIG. 2 and, for a better understanding, current path is also shown in FIGS. 3A to 3D for positive half cycle, where i.sub.0 represents the direction of current. During +V.sub.dc/2, FIG. 3A first positive level, and +V.sub.dc, FIG. 3B second positive level, both capacitors C.sub.1 and C.sub.2 are charged initially generating an output voltage equivalent to +V.sub.dc/2 and +V.sub.dc, respectively. While, during +3 V.sub.dc/2, FIG. 3C third positive level, capacitor C.sub.1 is discharged to generate output voltage equivalent to +3 V.sub.dc/2. Then, during +2V.sub.dc, FIG. 3D fourth positive level, both capacitors C.sub.1 and C.sub.2 are discharged collectively generating output voltage equivalent to +2 V.sub.dc and so on, as during +V.sub.dc and +2V.sub.dc both capacitors are charged and discharged collectively sharing the same charging and discharging current; therefore, maintaining the constant output current. Whereas, the primary function of the backend H-bridge is to operate at fundamental cycle and change the polarity of the output voltage switching S.sub.4 and S.sub.7 on for positive half, S.sub.5 and S.sub.6 on for negative half and also to generate zero level as switches S.sub.4 and S.sub.5 are turned on. Some of the prominent features of the 9L-SCMLI inverter has the following features: Generates output voltage of magnitude twice the input voltage (V.sub.out=2 V.sub.in). Only eight power switches, two diodes, single source and two capacitors are used to generate desired output voltage requiring reduced number of components are required. Does not require additional circuits for balancing capacitors voltage as it has self-balancing and self-voltage boosting ability with reduced complexity.

(26) The 9L-SCMLI inverter can be further extended based on the structural point of view to generate higher number of levels in all possible directions to generate desired output voltage. The possible ways of extension can be achieved in two ways: horizontal extension (HE) and vertical extension (VE), which are discussed in detail below.

(27) FIG. 4 shows the extension of the 9L-SCMLI inverter in the horizontal direction to generate higher number of levels and is here after referred to as 9L-SCMLI (HE). It can be extended up to N.sup.th cell as 1.sup.st cell, 2.sup.nd cell . . . N.sup.th cell. Each cell contains a desired number of units having same configuration throughout the circuit up to its extension, which can be extended as switches S.sub.11, S.sub.12, S.sub.13 . . . , S.sub.1n. Similarly, switches S.sub.21, S.sub.22, S.sub.23, . . . , S.sub.2n, switches S.sub.31, S.sub.32, S.sub.33, . . . , S.sub.3n and switches S.sub.41, S.sub.42, S.sub.43, . . . , S.sub.4n, diodes D.sub.11 and D.sub.21 and capacitors C.sub.11 and C.sub.21 are extended in the same manner. As capacitors C.sub.11 and C.sub.21 are connected in parallel to each other, it provides a step up in voltage. Further, operation of the 9L-SCMLI (HE) is discussed in brief.

(28) Generalised switching pattern of the proposed 9L-SCMLI (HE) is listed in Table 2, which can be generated with the help of FIG. 4 as it represents the extension of the 9L-SCMLI inverter in the horizontal direction up to n. Further, the charging and discharging of capacitors C.sub.11, C.sub.12, C.sub.13, . . . , C.sub.1n and capacitors C.sub.21, C.sub.22, C.sub.23, . . . , C.sub.2n) are similar to Table 2. When opted for higher number of voltage levels, capacitors are charged for a longer period. While, discharging period of capacitors decreases for higher number of voltage levels. In order to validate the following results, generalized equations (1) to (6) are provided.
N.sub.L=4n+1  (1)
N.sub.cap=2(n−1)  (2)
N.sub.d=2(n−1)  (3)
N.sub.sw=N.sub.driver=4n  (4)
V.sub.max=nV.sub.dc  (5)
V.sub.in:V.sub.ont=1:n  (6)
where N.sub.sw represents number of switches, k.sub.cap is the number of capacitors, N.sub.d is the number of diodes, N.sub.L is the number of voltage levels and V.sub.max is the maximum output voltage, where, n is dependent upon maximum gain to be generated as it satisfies the condition n=2.

(29) TABLE-US-00002 TABLE 2 Generalized Switching Pattern for HE Output On state of switches Voltage S.sub.11, S.sub.21, S.sub.31, S.sub.4, S.sub.5, Diodes conducting state Capacitor States (V.sub.o) S.sub.12, . . . , S.sub.1n S.sub.22, . . . , S.sub.2n S.sub.32, S.sub.3n S.sub.41, . . . , S.sub.4n S.sub.6, S.sub.7 D.sub.11, . . . , D.sub.1n D.sub.21, . . . , D.sub.2n C.sub.11, . . . , C.sub.1n C.sub.21, . . . , C.sub.2n +V.sub.dc/2 -, . . . , - S.sub.21 . . . S.sub.2(n−1) S.sub.3n, -. . .- S.sub.41 . . . S.sub.4n S.sub.4, S.sub.7 D.sub.11 . . . D.sub.1n -. . .-, D.sub.2n C, C . . . , C C, C . . . , C +V.sub.dc -, . . . , - S.sub.21 . . . S.sub.2n -. . .- S.sub.41 . . . S.sub.4n S.sub.4, S.sub.7 D.sub.11 . . . D.sub.1n -, . . . , - C, C . . . , C C, C . . . , C +3 V.sub.dc/2 -. . .-, S.sub.1n S.sub.21 . . . S.sub.2(n−1) S.sub.3n, -. . .- S.sub.41 . . . S.sub.4(n-1) S.sub.4, S.sub.7 D.sub.11 . . . D.sub.1(n−1) -. . .-, D.sub.2n C, . . . , C, D C, . . . C, - +2 V.sub.dc -. . .-, S.sub.1n S.sub.21 . . . S.sub.2(n−1) -, . . .- S.sub.41 . . . S.sub.4(n-1) S.sub.4, S.sub.7 D.sub.11 . . . D.sub.1(n−1) -, . . . , - C, . . . , C, D C . . . C, D +5 V.sub.dc/2 -. . .-S.sub.1(n−1) S.sub.21 . . . S.sub.2(n−2) S.sub.3(n−1), S.sub.41 . . . S.sub.4(n-2) S.sub.4, S.sub.7 D.sub.11 . . . D.sub.1(n−2) -. . .-, D.sub.2(n−1) C . . . C, D, D C . . . C, -, D S.sub.1n -. . .- +3 V.sub.dc -. . .-S.sub.1(n−1) S.sub.21 . . . S.sub.2(n−2) -, . . .- S.sub.41 . . . S.sub.4(n-2) S.sub.4, S.sub.7 D.sub.11 . . . D.sub.1(n−2) -, . . . , - C . . . C, D, D C . . . C, D D S.sub.1n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +(n + 1) S.sub.11 . . . S.sub.1n S.sub.21 . . . S.sub.2n -, . . . , - -, . . . , - S.sub.4, S.sub.7 -, . . . , - -, . . . , - D, D, . . . , D D, D, . . . , D V.sub.dc −(n + 1) S.sub.11 . . . S.sub.1n S.sub.21 . . . S.sub.2n -, . . . , - -, . . . , - S.sub.5, S.sub.6 -, . . . , - -, . . . , - D, D, . . . , D D, D, . . . , D V.sub.dc  0 .Math. V.sub.dc -, . . . , - -, . . . , - -, . . . , - -, . . . , - S.sub.4, S.sub.5 -, . . . , - -, . . . , - -, . . . , - -, . . . , - * - = OFF state and . . . = Continuation of previous states.

(30) FIG. 5 shows the extension of the 9L-SCMLI inverter in a vertical configuration and hereafter referred to as 9L-SCMLI (VE). As it can be extended up to N.sup.th cell, each cell containing an acquired number of units of two switches S.sub.12, S.sub.22, . . . , S.sub.n2) and switches S.sub.14, S.sub.24, . . . , S.sub.n4), three diodes D.sub.11, D.sub.21, . . . , D.sub.n1) and diodes D.sub.12, D.sub.22, . . . , D.sub.n2) and two capacitors C.sub.11, C.sub.12, . . . , C.sub.1n) and capacitors C.sub.12, C.sub.22, . . . , C.sub.n2) connected in parallel to each other to provide a stepped up output voltage. Equations (7) to (12) correspond to 9L-SCMLI (VE) for extending up to n and can be validated with the help of FIG. 5, where, n is dependent upon maximum gain to be generated as it satisfies the condition n≥2. Generalized switching pattern of the proposed extension can be seen from Table 3 for generating (n+1) V.sub.d, voltage levels. Charging and discharging of capacitors with respect to desired voltage level can be seen from Table 3
N.sub.L=4n+1  (7)
N.sub.cap=2(n−1)  (8)
N.sub.d=2(n−1)  (9)
N.sub.sw=N.sub.driver=3n+2  (10)
V.sub.max=nV.sub.dc  (11)
V.sub.in:V.sub.out=1:n  (12)

(31) The determination of a suitable capacitance value is another important factor for SCMLI topologies. Here, the determination of capacitance for the proposed 9L-SCMLI is discussed. For determining the value of capacitance, longest discharging cycle (LDC) of each capacitor is taken into account. To aid this, FIG. 6 representing the waveform of the proposed 9L-SCMLI at fundamental frequency is included.

(32) TABLE-US-00003 TABLE 3 Generalized Switching Pattern for the VE Output On state of switches Diodes conducting state Capacitor States Voltage S.sub.n2 . . . S.sub.22, S.sub.n3 . . . S.sub.4, S.sub.5, D.sub.n2, . . . D.sub.22, C.sub.n1 . . . C.sub.21, C.sub.n2 . . . C.sub.22, (V.sub.o) S.sub.11 S.sub.12 S.sub.32S.sub.13 S.sub.n4 . . . S.sub.24, S.sub.14 S.sub.6, S.sub.7 D.sub.21 D.sub.21, . . . , D.sub.2n C.sub.11 C.sub.12 +V.sub.dc/2 -, . . . , - -, . . . , - S.sub.3n, -, . . . , - S.sub.n4 . . . S.sub.24, S.sub.14 S.sub.4, S.sub.7 D.sub.11, D.sub.21 . . . D.sub.n1 D.sub.n2, -, . . . , - C, C, . . . , C C, C, . . . , C +V.sub.dc -, . . . , - S.sub.n2, - . . . - -. . .- S.sub.n4 . . . S.sub.24, S.sub.14 S.sub.4, S.sub.7 D.sub.11, D.sub.21 . . . D.sub.n1 -, . . . , - C, C, . . . , C C, C, . . . , C +3 V.sub.dc/2 -, . . . , - S.sub.(n−1)2, - . . . - S.sub.3n, -, . . . , - S.sub.(n−1)4, . . . S.sub.14 S.sub.4, S.sub.7 D.sub.(n−1)1, . . . , D.sub.11 D.sub.n2, -, . . . , - D, C, . . . , C -, C, C, . . . C +2 V.sub.dc -, . . . , - S.sub.n2, S.sub.(n−1)2 - . . . -, . . ., - S.sub.(n−1)4, . . . S.sub.14 S.sub.4, S.sub.7 D.sub.(n−1)1, . . . , D.sub.11 -, . . . , - D, C, . . . , C D, C, . . . , C +5 V.sub.dc/2 S.sub.11 -, . . . , - S.sub.(n−1)3, -. . .- S.sub.(n−2)4, . . . S.sub.14 S.sub.4, S.sub.7 D.sub.(n−2)1, . . . , D.sub.11 D.sub.(n−1)2, . . . , D, D, C, . . . , C D, -, C, . . . , C D.sub.12 +3 V.sub.dc S.sub.11 S.sub.n2, -, S.sub.(n−2), - . -, . . . , - S.sub.(n−2)4, . . . S.sub.14 S.sub.4, S.sub.7 D.sub.(n−2)1, . . . , D.sub.11 -, . . . , - D, D, C, . . . , C D, D, C, . . . , C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +(n + 1) -, S.sub.11 . . . S.sub.n2, . . . , S.sub.12 -, . . . , - S.sub.(n−1)4, . . . S.sub.14 S.sub.4, S.sub.7 D.sub.(n−1)1, . . . , D.sub.11 -, . . . , - D, D, . . . , D D, D, . . . , D V.sub.dc −(n + 1) -, S.sub.11 . . . S.sub.n2, . . . , S.sub.12 -, . . . , - S.sub.(n−1)4, . . . S.sub.14 S.sub.5, S.sub.6 D.sub.(n−1)1, . . . , D.sub.11 -, . . . , - D, D, . . . , D D, D, . . . , D V.sub.dc  0 .Math. V.sub.dc -, . . . ,- -, . . . , - -, . . . , - -, . . . , - S.sub.4, S.sub.5 -, . . . , - -, . . . , - -, . . . , - -, . . . , -

(33) As evident, LDC for both capacitors C.sub.1 and C.sub.2 occur in both positive and negative cycles at different time intervals from different voltage levels. Therefore, maximum discharging value for each capacitor can be concluded from the following equations:

(34) $\begin{array}{cc}{Q}_{C1}=2\times {\int }_{T_3}^{T/4}{I}_L\left(t\right)\mathrm{dt}& \left(13\right)\\ Q_{C2}=2\times {\int }_{T4}^{T/4}{I}_L\left(t\right)\mathrm{dt}& \left(14\right)\end{array}$
Here, Q.sub.Ci for =1, 2 represents the maximum discharging amount of capacitors. In equation, k×V.sub.dc represents maximum allowable voltage ripple of capacitors, optimum value of capacitors can be obtained from

(35) $\begin{array}{cc}{C}_{\mathrm{opt}}i\ge \frac{Q_{Ci}}{k\times V_{dc}}& \left(15\right)\end{array}$
Considering the equation of load current for a pure resistive load (R.sub.L) at third and fourth positive output voltages at steady-state conditions, the following can be derived:

(36) $\begin{array}{cc}\begin{array}{cc}{I}_L\left(t\right)=\frac{3V_{dc}}{2R_L},& t_3\le t\le \frac{T}{4}\end{array}& \left(16\right)\\ \begin{array}{cc}{I}_L\left(t\right)=\frac{2V_{dc}}{R_L},& t_4\le t\le \frac{T}{4}\end{array}& \left(17\right)\end{array}$
Further, the fundamental switching timing instants t.sub.3 and t.sub.4 are equal to 3 T/20 and T/5 and are obtained from cutting of DC levels to sinusoidal function of reference waveform. For resistive inductive loading condition function IL(t) can be expressed as
I.sub.L(t)=I.sub.max sin(ωt−φ)  (18)

(37) By solving (13) to (18) at given conditions, the optimum value of capacitors at pure resistive load and resistive-inductive load are shown in the following equation:

(38) $\begin{array}{cc}{C}_{\mathrm{opt},i}\ge \frac{7\pi }{10R_L\times k\times \tilde{\omega }}& \left(19\right)\\ C_{\mathrm{opt},i}\ge \frac{2I_{\max }}{k\times V_{dc}\times \tilde{\omega }}\left[\cos \left(\frac{\pi }{10}-\phi \right)+\sin \left(2\frac{\pi }{5}+\phi \right)\right]& \left(20\right)\end{array}$

(39) It is worth mentioning that equations (19) and (20) represent the optimum value of capacitors for the 9L-SCMLI, inverter which shows an inverse relation with k, ω and R.sub.L from equation (19). To have a better understanding for determining appropriate value of capacitance, a graph is shown in FIG. 7A between C.sub.opt and R.sub.L at different values for an allowable voltage ripple keeping co fixed at the value 100π. From FIG. 7B, it can be concluded that a larger rate of allowable voltage ripple has led to smaller capacitance. By increasing the output frequency at different values of R.sub.L, the value of optimum capacitance gets reduced but may lead to increase in switching losses at higher output frequency. In order to provide a better clarification, a graph is being plotted between different variations of C.sub.opt at different values of output frequency at fixed resistive load R.sub.L=200Ω for higher frequency at allowable voltage ripple.

(40) On the other hand, optimum capacitance is varied for different angles of φ at allowable voltage ripple of 5 and 10%, where k=0.05 and k=0.1, considering a constant value for I.sub.max=5 A, V.sub.dc, =100 V, f=50 Hz and w=100 π at fundamental frequency. It can be concluded that as q) increases the value of capacitance decreases for the SCMLI as shown in FIG. 7C.

(41) Power loss analysis of the 9L-SCMLI includes overall loss calculation, switching losses P.sub.Sw, conduction losses P.sub.Con and ripple losses P.sub.Rip for both capacitors at fundamental frequency as maximum loss conditions are considered during calculations.

(42) In general, switching losses occur during ON and OFF transition state of switches. To reduce the complexity, a linear approximation between voltage and current of switches is being considered for switching period. As an outcome, following equations are considered for switching losses:

(43) $\begin{array}{cc}\begin{array}{c}{P}_{\mathrm{Sw},\mathrm{on},i}={\int }_0^{t_{on}}v\left(t\right)i\left(t\right)\mathrm{dt}\\ ={\int }_0^{t_{on}}\left[\left(\frac{V_{\mathrm{sw},i}}{t_{\mathrm{on}}}t\right)\left(-\frac{I_i}{t_{\mathrm{on}}}\left(t-t_{\mathrm{on}}\right)\right)\right]\mathrm{dt}\\ =\frac{1}{6}{V}_{\mathrm{sw},i}{I}_i{t}_{\mathrm{on}}\end{array}& \left(21\right)\\ \begin{array}{c}{P}_{\mathrm{Sw},\mathrm{off},i}={\int }_0^{t_{\mathrm{off}}}v\left(t\right)i\left(t\right)\mathrm{dt}\\ ={\int }_0^{t_{\mathrm{off}}}\left[\left(\frac{V_{\mathrm{sw},i}}{t_{\mathrm{off}}}t\right)\left(-\frac{{I^{\prime }}_i}{t_{\mathrm{off}}}\left(t-t_{\mathrm{off}}\right)\right)\right]\mathrm{dt}\\ =\frac{1}{6}{V}_{\mathrm{sw},i}{I^{\prime }}_i{t}_{\mathrm{off}}\end{array}& \left(22\right)\end{array}$
where I.sub.i and I′.sub.i are currents through i.sup.th switch, N.sub.on and N.sub.off is number of turn on and off a switch during fundamental cycle k. As a result to calculate total switching loss per one cycle can be written as follows:

(44) $\begin{array}{cc}{P}_{\mathrm{sw},i}=\frac{1}{6T}\underset{i=1}{\overset{7}{.Math.}}\left(\underset{k=1}{\overset{N_{on}}{.Math.}}{P}_{\mathrm{sw},\mathrm{on},\mathrm{ik}}+\underset{k=1}{\overset{N_{\mathrm{off}}}{.Math.}}{P}_{\mathrm{sw},\mathrm{off},\mathrm{ik}}\right)& \left(23\right)\end{array}$

(45) In order to calculate total conduction losses at steady state, a pure resistive load (R.sub.L) is considered. Based on the overall circuit analysis shown in FIGS. 8A to 8D, all possible operations are considered to calculate the maximum conduction loss. FIGS. 8A to 8D represent the equivalent circuit diagram for the 9L-SCMLI inverter. Pure resistive loading condition is considered because there should not exist any auxiliary current path between load current and output voltage to facilitate the charging of capacitors. Therefore, resistive loading condition is considered as worst condition for calculation of losses in SCMLIs

(46) Hereafter, R.sub.onD, R.sub.ESR, R.sub.onu represent internal resistance of power diode, equivalent series resistance of each capacitor and internal resistance of each switch. While VRS, VC and VF showcases reverse biased voltage of power diode, stored voltage of capacitor and forward biased voltage of power diode. By applying Kirchhoffs voltage law and Kirchhoffs current law for connecting nodes, the following equations are summarised. Equation (24) represents the charging current of involved capacitors for states ±V.sub.dc/2 during operating mode (I.sub.L, I). Similarly, in equation (25) for V.sub.dc, as it also involves charging of capacitors at second operating mode (I.sub.L, II). Equations (27) and (28) show third and fourth operating modes with respect to FIGS. 7C and 7D, respectively. Instantaneous value of conduction losses during operating modes I, II, III and IV are given in equations (28) to (31) as follows:
2(R.sub.onD+R.sub.ESR)I.sub.charging+(3R.sub.onu+R.sub.onDR.sub.L)I.sub.L,I+R.sub.onD(I.sub.charging+I.sub.L,I)=V.sub.dc−V.sub.RS−2(V.sub.c+V.sub.F)  (24)
2(R.sub.onD+R.sub.ESR)I.sub.charging+(3R.sub.onu+R.sub.onDR.sub.L)I.sub.L,II+(I.sub.L,II+I.sub.charging)R.sub.onD=V.sub.dc+V.sub.F−2V.sub.c−V.sub.RS)  (25)
(4R.sub.onu+R.sub.onD+R.sub.L+R.sub.ESI)I.sub.L,III=V.sub.dc−V.sub.F+V.sub.c  (26)
(4R.sub.onu+R.sub.L+2.sub.ESR)I.sub.L,IV=V.sub.dc+2V.sub.c  (27)
As an outcome, to calculate the average value during full cycle of output voltage waveform for first, second, third and fourth voltage levels, corresponding time should be taken into consideration
P.sub.con,I=2(I.sub.charging).sup.2(R.sub.onD±R.sub.ESR)+(I.sub.L,1).sup.2(3R.sub.onu+R.sub.onD)+R.sub.onD(I.sub.L,I+I.sub.charging).sup.2  (28)
P.sub.con,II=2(R.sub.onD+2R.sub.ESR)(I.sub.charging).sup.2+3R.sub.onu(I.sub.L,II).sup.2+R.sub.onD(I.sub.L,II+I.sub.charging).sup.2  (29)
P.sub.con,III=(4R.sub.onu+R.sub.onD+R.sub.ESR)(I.sub.L,III).sup.2  (30)
P.sub.con,IV=(4R.sub.onu+2R.sub.ESR)(I.sub.L,IV).sup.2  (31)
From FIGS. 8A to 8D, (t.sub.2−t.sub.1), (t.sub.3−t.sub.2), (t.sub.4−t.sub.3) and (T/4−t.sub.4), respectively, are given in equations (32) to (35). As a result, the total conduction losses (P.sub.con,T) over a full cycle output voltage are shown in equation (36).

(47) $\begin{array}{cc}{\overline{P}}_{\mathrm{con},I}=\frac{4}{T}\left(t_2-t_1\right)P_{\mathrm{con},I}& \left(32\right)\\ {\overline{P}}_{\mathrm{con},\mathrm{II}}=\frac{4}{T}\left(t_3-t_2\right)P_{\mathrm{con},\mathrm{II}}& \left(33\right)\\ {\overline{P}}_{\mathrm{con},\mathrm{III}}=\frac{4}{T}\left(t_4-t_3\right)P_{\mathrm{con},\mathrm{III}}& \left(34\right)\\ {\overline{P}}_{\mathrm{con},{\mathrm{IV}}^{=}}\frac{4}{T}\left(\frac{T}{4}-t_4\right)P_{\mathrm{con},\mathrm{IV}}& \left(35\right)\\ {\overline{P}}_{con,T}={\overline{P}}_{\mathrm{con},I}+{\overline{P}}_{\mathrm{con},\mathrm{II}}+{\overline{P}}_{\mathrm{con},\mathrm{III}}+{\overline{P}}_{\mathrm{con},\mathrm{IV}}& \left(36\right)\end{array}$

(48) Simulation results for power losses are compared in this section under dynamic load, where, conduction and switching losses of the 9L-SCMLI inverter are calculated for each switch. FIGS. 9A to 9D demonstrate the outcomes from loss calculation as discussed above, where P.sub.con_sw, P.sub.sw_sw represent conduction and switching losses in IGBT and P.sub.con_d, P.sub.sw_d represent conduction and switching losses in diode.

(49) Only switch S.sub.8 experiences maximum loss as compared to other switches. While switches present in H-bridge, that is S.sub.4, S.sub.5, S.sub.6 and S.sub.7 share almost equal losses and switch S.sub.3 having the least. Overall, power loss for proposed topology is quite low.

(50) Ripple losses usually occur when capacitors are connected in parallel for charging operation due to the difference between input voltage and voltage of capacitors. Therefore, voltage ripple of capacitors is shown in the following equation:

(51) $\begin{array}{cc}\Delta V_{Ci}=\frac{1}{Ci}{\int }_{t^{\prime }}^t{i}_{\mathrm{Ci}}\left(t\right)dt& \left(37\right)\end{array}$

(52) where [t−t] represents time interval of discharging modes in capacitors. Total value of ripples losses for a fundamental cycle can be seen from

(53) $\begin{array}{cc}{P}_{Rip}=\frac{1}{2T}\underset{i=1}{\overset{2}{.Math.}}{C}_i\Delta V_{Ci}^2& \left(38\right)\end{array}$

(54) Since P.sub.Rip is inversely proportional to the capacitance Ci, larger value of capacitance leads to increase in overall efficiency. Equations (39) and (40) represent total losses using which the overall efficiency of the proposed 9L-SCMLI can be deduced as below, where P.sub.out is output power of the SCMLI inverter.

(55) 0$\begin{array}{cc}{P}_{\mathrm{Loss}}=P_{\mathrm{Rip}}+P_{\mathrm{Con},T}+P_{\mathrm{sw}}& \left(39\right)\\ \eta =\frac{P_{\mathrm{out}}}{P_{\mathrm{out}}+P_{Loss}}& \left(40\right)\end{array}$

(56) The simulation and experimental results validate the performance of the SCMLI according to the invention. Firstly, the SCMLIs were simulated in MATLAB/SIMUINK for values V.sub.in=100 V with each capacitor of 470 μF having R.sub.ESR=0.1Ω under dynamic load condition for fundamental frequency (f=50 Hz) and f=400 Hz-1 kHz. In order to verify the performance of the SCMLI experimentally, a laboratory prototype was fabricated using Semikron insulated gate bipolar transistors (IGBT SKM75GB063D switches) having R.sub.onu=14 mΩ and power diode 25 HMR 120 with R.sub.onD=3 mΩ and each capacitor of 470 μF were used. The dSPACE 1104 is used for generating the gate pulses at fundamental frequency of 50 Hz, while SKYPER-32-PRO-R as gate driver were used during implementation of prototype.

(57) Both simulation waveforms of the 9LSCMLI at f=50 Hz and 1 kHz are shown in FIGS. 10A to 10D under R−L (R=50Ω, L=1 mH) load condition. While, experimental waveforms are shown in FIGS. 11a-c at f?=?50 Hz, 400 Hz and 1 kHz under R−L (R=50Ω, L=1 mil) load condition at different frequency having output voltage equal to 200V and output current equal to 4 A, as both capacitors voltage equal to 50V. However, waveforms shown in FIGS. 11A to 11C represent the performance of the 9L-SCMLI when opted for higher frequency at a fixed load condition. Dynamic load variation is done at f=400 Hz as shown in FIGS. 12A to 12C. Waveforms shown in FIGS. 11A to 11C highlight the feasibility of the SCMLI for load variation adaptability at higher frequency. Change in modulation index (m) is shown in FIGS. 13A to 13C. At m equal to 0.2, 0.4, 0.6 and 1 at f equal to 1 kHz. FIG. 12A represents a change in m from 0.2 to 0.4 causing change in output voltage and current waveform while the voltage across both the capacitors remains constant (capacitors are neither charged nor discharged). Similarly, as in FIG. 13B, while in FIG. 13C voltage across capacitors changes with change in in from 0.6 to 1. In conclusion, during change in m change in output voltage levels is observed as shown in FIG. 13A from 3L to 5L, FIG. 13B from 5L to 7L, FIG. 13C from 7L to 9L. Change in step input voltage from 100V to 200V is shown in FIG. 14A, generally. From low to high causing change in output voltage, current and voltage across capacitors represents the stability of the SCMLI under sudden change in input voltage at f=1 kHz. Switch voltage and current across switches S.sub.2 and S.sub.6 is shown in FIG. 14B at f=50 Hz under R−L (R=50Ω, L=1 mH) load condition. Feasibility of the proposed SCMLI under R−L (80Ω-100 mH) load condition is shown in FIGS. 15A and 15B.

(58) Results of a31L-SCMLI (HE) are presented. As shown in FIGS. 16A and 16B, simulation results representing output voltage, current and voltage across capacitors is shown at f=50 Hz under R−L (R=65Ω, L=1 mH) load condition. Similarly, under the same load condition at f=400 Hz simulation results are shown in FIGS. 16C and 16D. While, experimental results are shown in FIGS. 17A and 17B representing the feasibility of the SCMLI under dynamic load variation and output voltage across capacitors is shown in FIG. 17C under R−L (R=65Ω, L=1 mH) load at f=50 Hz. In conclusion, the above discussed waveforms represent the operability of the SCMLI under dynamic conditions. The experimental prototype used for testing is shown in FIG. 18. FIG. 19 represents the efficiency graph for the proposed 9L-SCMLI w.r.t. to load variation at f=50 Hz having efficiency up to 97.08% (R=225Ω, L=1 mH).

(59) While the invention has been described in terms of a preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.