MUSCLE FATIGUE MONITORING SYSTEM
20170258373 ยท 2017-09-14
Assignee
Inventors
Cpc classification
G06F3/015
PHYSICS
A61B5/7246
HUMAN NECESSITIES
International classification
A61B5/11
HUMAN NECESSITIES
G06F3/023
PHYSICS
Abstract
A muscle fatigue monitoring system includes an sEMG amplifier module configured to receive sEMG signals and amplify the received sEMG signals; a filter module connected with the sEMG amplifier module; a bit-stream converter connected with the filter module and configured to digitize the sEMG signals and convert the sEMG signals to a discrete signal based on a single threshold without digitizing the complete sEMG signals, and a bit-stream cross correlator connected with the bit-stream converter, the bit-stream cross correlator including a plurality of correlation stages connected in series, a plurality of counters connected with the correlation stages respectively, and a maximum value selector connected to the counters, and configured to continuously correlate the sEMG signals in a given time window, count all time instances where the sEMG signals are the same, compares all the counters in cycles, and find distance between specific reference points on the sEMG signals through the counter with a maximum value.
Claims
1. A muscle fatigue monitoring system comprising: an sEMG amplifier module configured to receive sEMG signals and amplify the received sEMG signals; a filter module connected with the sEMG amplifier module; a bit-stream converter connected with the filter module and configured to digitize the sEMG signals and convert the sEMG signals to a discrete signal based on a single threshold without digitizing the complete sEMG signals; a bit-stream cross correlator connected with the bit-stream converter, the bit-stream cross correlator comprising a plurality of correlation stages connected in series, a plurality of counters connected with the correlation stages respectively, and a maximum value selector connected to the counters, and configured to continuously correlate the sEMG signals in a given time window, count all time instances where the sEMG signals are the same, compares all the counters in cycles, and find distance between specific reference points on the sEMG signals through the counter with a maximum value; a bias generator; a timing control module connected with the bit-stream cross correlator; and a serial peripheral interface connected with the timing control module and the maximum value selector; wherein: the sEMG amplifier module comprises a plurality of dual channel instrumentation amplifiers and an external floating high-pass filter; the filter module comprises two low-pass filters and is configured to extract signal attributes in a frequency band of 10 Hz-500 Hz; the bit-stream converter comprises two analog comparators; the maximum value selector comprises a plurality of comparing blocks, and is configured to start by comparing values of the counters in pairs and then proceed with evaluating results of the previous comparisons, each comparing block being configured to compare two 14 bit numbers; each correlation stage comprises a delay block, a counter and a correlator; the delay block is a D-type flip flop, delay time of the delay block being controlled by a sampling frequency of the system; the counter of each correlation stage is a 14 bit ripple counter with a counter size being selected by analyzing retrospective sEMG data; and the correlator comprises a XNOR gate and an AND gate connected with the XNOR gate.
2. The muscle fatigue monitoring system of claim 1, wherein the low-pass filters are Sallen Key low-pass filters with cutoff frequency of 2.5 kHz.
3. The muscle fatigue monitoring system of claim 1, wherein reference voltages of the two analog comparators are kept separate to allow offset mismatch compensation.
4. A muscle fatigue monitoring system comprising: an sEMG amplifier module configured to receive sEMG signals and amplify the received sEMG signals; a filter module connected with the sEMG amplifier module; a bit-stream converter connected with the filter module and configured to digitize the sEMG signals and convert the sEMG signals to a discrete signal based on a single threshold without digitizing the complete sEMG signals; and a bit-stream cross correlator connected with the bit-stream converter, the bit-stream cross correlator comprising a plurality of correlation stages connected in series, a plurality of counters connected with the correlation stages respectively, and a maximum value selector connected to the counters, and configured to continuously correlate the sEMG signals in a given time window, count all time instances where the sEMG signals are the same, compares all the counters in cycles, and find distance between specific reference points on the sEMG signals through the counter with a maximum value; wherein: the sEMG amplifier module comprises a plurality of dual channel instrumentation amplifiers and an external floating high-pass filter; the filter module comprises two low-pass filters; the bit-stream converter comprises two analog comparators; and each correlation stage comprises a delay block, a counter and a correlator.
5. The muscle fatigue monitoring system of claim 4 further comprising a bias generator, a timing control module connected with the bit-stream correlator, and a serial peripheral interface connected with the timing control module and the maximum value selector.
6. The muscle fatigue monitoring system of claim 4, wherein the filter module comprises is configured to extract signal attributes in a frequency band of 10 Hz-500 Hz.
7. The muscle fatigue monitoring system of claim 4, wherein the maximum value selector comprises a plurality of comparing blocks, and is configured to start by comparing values of the counters in pairs and then proceed with evaluating results of the previous comparisons, each comparing block being configured to compare two 14 bit numbers.
8. The muscle fatigue monitoring system of claim 4, wherein the delay block is a D-type flip flop, delay time of the delay block being controlled by a sampling frequency of the system.
9. The muscle fatigue monitoring system of claim 4, wherein the counter of each correlation stage is a 14 bit ripple counter with a counter size being selected by analyzing retrospective sEMG data.
10. The muscle fatigue monitoring system of claim 4, wherein the correlator comprises a XNOR gate and an AND gate connected with the XNOR gate.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0015]
[0016]
[0017]
[0018]
DETAILED DESCRIPTION
[0019] Reference will now be made in detail to a preferred embodiment of the muscle fatigue monitoring system disclosed in the present patent application, examples of which are also provided in the following description. Exemplary embodiments of the muscle fatigue monitoring system disclosed in the present patent application are described in detail, although it will be apparent to those skilled in the relevant art that some features that are not particularly important to an understanding of the muscle fatigue monitoring system may not be shown for the sake of clarity.
[0020] Furthermore, it should be understood that the muscle fatigue monitoring system disclosed in the present patent application is not limited to the precise embodiments described below and that various changes and modifications thereof may be effected by one skilled in the art without departing from the spirit or scope of the protection. For example, devices and/or features of different illustrative embodiments may be combined with each other and/or substituted for each other within the scope of this disclosure.
[0021]
[0022] The sEMG amplifier module 101 includes a plurality of dual channel instrumentation amplifiers and is configured to receive sEMG signals and amplify the received sEMG signals. The sEMG amplifier module 101 is capable of rejecting up to 300 mV DC Polarization Voltage (PV) from the bio-potential electrodes.
[0023] The sEMG amplifier module 101 further includes an external floating high-pass filter. Compared to using conventional passive high-pass filters, no grounded resistors are required, which result in very large common mode input impedance.
[0024] The filter module 103 includes two low-pass filters and is configured to extract signal attributes in a frequency band of 10 Hz-500 Hz. Preferably the low-pass filters are Sallen Key low-pass filters with cutoff frequency of 2.5 kHz.
[0025] The bit-stream converter 105 includes two analog comparators and is configured to digitize the sEMG signals. The reference voltages of the two comparators are kept separate to allow offset mismatch compensation.
[0026] The bit-stream cross correlator 107 is configured to continuously correlate the sEMG signals in a given time window, count all time instances where the sEMG signals are the same, compares all the counters in cycles, and find distance between specific reference points on the sEMG signals through the counter with a maximum value.
[0027]
[0028] Referring to
[0029] Referring to
[0030]
[0031]
[0032] In this embodiment, the bit-stream cross correlator 107 is configured to execute a cross-correlation algorithm and compute the time delay between the sEMG signals. The algorithm can be applied to finding the distance between specific reference points such as a valley, a peak or a zero, so that the cross correlation process is simplified. The sEMG signals are converted by the bit-stream converter to a discrete signal based on a single threshold, without digitizing the complete sEMG signals, while retaining the necessary information for cross correlation and delay estimation. This eliminates the need to cross-correlating the whole sEMG signal, while only a single bit approximation of the sEMG signals is required to be cross-correlated, so that the cross-correlator's architecture is greatly simplified.
[0033] In this embodiment, bit-stream buffer window is eliminated by continuously cross correlating the two sEMG signals in a given time window. This is achieved by counting all the time instances where the two signals are the same. A cross correlation time window replaces the buffer window for x(n).
[0034] In this embodiment, discrete time lags for the cross-correlation output are obtained by continuously delaying the input signal. Cross correlation result for every discrete time delay is obtained. The time lag between the two signals is returned by the counter with the larger value, so that the number of transistors required is greatly reduced.
[0035] While the present patent application has been shown and described with particular references to a number of embodiments thereof, it should be noted that various other changes or modifications may be made without departing from the scope of the present invention.