Switching control circuit with signal process to accommodate the synchronous rectifier of power converters

Abstract

A switching control circuit of a power converter according to the present invention comprises an input circuit and a clock generator. The input circuit is coupled to receive a feedback signal for generating a switching signal. The clock generator generates a clock signal to determine a switching frequency of the switching signal. The feedback signal is correlated to an output of the power converter. The switching signal is coupled to switch a transformer of the power converter for regulating the output of the power converter. The pulse width of the switching signal is reduced before the switching frequency of the switching signal is changed from a low frequency to a high frequency.

Claims

1. A switching control circuit of a power converter, comprising: a switching circuit coupled to receive a feedback signal for generating a switching signal; and a clock generator generating a clock signal to determine a switching frequency of the switching signal; wherein the feedback signal is correlated to an output of the power converter; the switching control circuit generates the switching signal to switch a transformer of the power converter for regulating the output of the power converter; when the switching control circuit operates at a same load state before the switching circuit increases the switching frequency of the switching signal the switching circuit first decreases a pulse width of the switching signal to resolve a limitation of a synchronous rectifier of the power converter.

2. The circuit as claimed in claim 1, wherein the pulse width of the switching signal is reduced before the switching signal is disabled.

3. The circuit as claimed in claim 1, wherein the pulse width of the switching signal is decreased to a specific value before the switching signal is disabled for the protection of the power converter.

4. The circuit as claimed in claim 1, wherein the switching circuit modulates the pulse width of the switching signal step by step in response to the feedback signal.

5. The circuit as claimed in claim 4, wherein the switching circuit further comprises a feedback circuit, the feedback circuit receives the feedback signal to generate an attenuated feedback signal, the switching circuit generates a modulated feedback signal in accordance with the attenuated feedback signal for generating the switching signal.

6. The circuit as claimed in claim 5, wherein the switching circuit further comprises a logic circuit generating the switching signal in response to the modulated feedback signal and the clock signal.

7. The circuit as claimed in claim 1, wherein the power converter comprises the synchronous rectifier at a secondary side of the transformer.

8. A control circuit of a power converter, comprising: a switching circuit coupled to receive a feedback signal for generating a switching signal; wherein the feedback signal is correlated to an output of the power converter; the switching signal is coupled to switch a transformer of the power converter for regulating the output of the power converter; the switching circuit changes its output step by step in accordance with its input signal, when the control circuit operates in a protection state the switching signal is disabled and a pulse width of the switching signal is decreased before the switching signal is disabled, when the control circuit operates at a same load state before the switching circuit increases a switching frequency of the switching signal the switching circuit first decreases the pulse width of the switching signal to resolve a limitation of a synchronous rectifier of the power converter.

9. The circuit as claimed in claim 8, wherein the power converter comprises the synchronous rectifier at a secondary side of the transformer.

10. The circuit as claimed in claim 8, further comprising: a clock generator generating a clock signal to determine a switching frequency of the switching signal.

11. The circuit as claimed in claim 8, wherein the pulse width of the switching signal is decreased to a specific value before the switching signal is disabled for the protection of the power converter.

12. A controller of a power converter, comprising: a switching circuit coupled to receive a feedback signal for generating a switching signal; and a protection circuit coupled to disable the switching signal in response to the protection of the power converter; wherein the feedback signal is correlated to an output of the power converter; the switching signal is coupled to switch a transformer of the power converter for regulating the output of the power converter; when the controller operates in a protection state the switching signal is disabled and a pulse width of the switching signal is decreased before the switching signal is disabled, when the controller circuit operates at a same load state before the switching circuit increases a switching frequency of the switching signal the switching circuit first decreases the pulse width of the switching signal to resolve a limitation of a synchronous rectifier of the power converter.

13. The controller as claimed in claim 12, wherein the power converter comprises the synchronous rectifier at a secondary side of the transformer.

14. The controller as claimed in claim 12, further comprising: a clock generator generating a clock signal to determine a switching frequency of the switching signal.

15. The controller as claimed in claim 12, wherein the pulse width of the switching signal is decreased to a specific value before the switching signal is disabled for the protection of the power converter.

16. The controller as claimed in claim 12, wherein the switching circuit is coupled to receive the feedback signal for generating the switching signal; the switching circuit is coupled to modulate the pulse width of the switching signal step by step in response to the feedback signal.

Description

BRIEF DESCRIPTION OF ACCOMPANIED DRAWINGS

(1) The accompanying drawings are included to provide further understanding of the invention, and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

(2) FIG. 1 shows a circuit diagram of a switching power converter.

(3) FIG. 2 is a circuit diagram of an embodiment of the switching control circuit in accordance with the present invention.

(4) FIG. 3 is a circuit diagram of an embodiment of the pulse generator in accordance with the present invention.

(5) FIG. 4 is a circuit diagram of an embodiment of the clock generator according to the present invention.

(6) FIG. 5 is a circuit diagram of an embodiment of the input circuit according to the present invention.

(7) FIG. 6 is a circuit diagram of an embodiment of the micro-stepping circuit according to the present invention.

(8) FIG. 7 is a circuit diagram of another embodiment of the micro-stepping circuit according to the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

(9) FIG. 2 is a circuit diagram of an embodiment of a switching control circuit in accordance with the present invention. The switching control circuit 100 is also a controller that comprises a switching circuit coupled to receive the feedback signal V.sub.FB for generating the switching signal S.sub.W. The switching circuit includes a logic circuit and an input circuit (INPUT) 300. The logic circuit includes a flip-flop 110, an AND gate 115, a comparator 150, an NOR gate 151, and an NAND gate 152. A clock generator 200 generates a clock signal C.sub.K coupled to determine the switching frequency of the switching signal S.sub.W. The clock signal C.sub.K is coupled to a clock input terminal CK of the flip-flop 110. An input terminal D of the flip-flop 110 is coupled to receive an enable signal EN. An output terminal Q of the flip-flop 110 is coupled to a first input terminal of the AND gate 115. A second input terminal of the AND gate 115 is coupled to receive the clock signal C.sub.K. An output terminal of the AND gate 115 generates the switching signal S.sub.W. The switching signal S.sub.W is coupled to control the transistor 20 to switch the transformer 10 (as shown in FIG. 1) of the power converter for regulating the output V.sub.O of the power converter.

(10) The input circuit 300 is coupled to receive the feedback signal V.sub.FB and generate a modulated feedback signal V.sub.B. The modulated feedback signal V.sub.B is coupled to disable the flip-flop 110 and the switching signal S.sub.W via the comparator 150, the NOR gate 151 and the NAND gate 152. The modulated feedback signal V.sub.B is coupled to a positive input terminal of the comparator 150. A ramp signal R.sub.MP is produced from the clock generator 200 and/or from the current-sense signal V.sub.CS. The ramp signal R.sub.MP is connected to a negative input terminal of the comparator 150 to disable the switching signal S.sub.W once the ramp signal R.sub.MP is higher than the modulated feedback signal V.sub.B. An output terminal of the comparator 150 is coupled to a first input terminal of the NOR gate 151. An output terminal of the NOR gate 151 is coupled to a first input terminal of the NAND gate 152. An output terminal of the NAND gate 152 is coupled to a reset input terminal R of the flip-flop 110 to reset the flip-flop 110 for disabling the switching signal S.sub.W.

(11) A frequency modulation signal H/L is utilized to program the switching frequency of the switching signal S.sub.W. The frequency modulation signal H/L is applied to the clock generator 200 to modulate the frequency of the clock signal C.sub.K for modulating the switching frequency of the switching signal S.sub.W, and the clock generator 200 generates an on-time adjust signal S.sub.J coupled to the input circuit 300 in response to the frequency modulation signal H/L. The on-time adjust signal S.sub.J is utilized to adjust the pulse width (on-time) of the switching signal S.sub.W. Before the switching frequency of the switching signal S.sub.W changes from a low frequency to a high frequency, the pulse width (on-time) of the switching signal S.sub.W will be reduced in advance. This on-time adjustment is done before the switching frequency of the switching signal S.sub.W is changed, which can achieve a proper operation for the synchronous rectifier (transistor 40) at the secondary winding N.sub.S (secondary side) of the transformer 10.

(12) Two protection signals OFF1 and OFF2 are applied to disable the switching signal S.sub.W in response to the protection of the power converter. The first protection signal OFF1 (such as the over-voltage protection (OVP)) is applied to a protection circuit to disable the switching signal S.sub.W immediately. The first protection signal OFF1 is thus coupled to reduce the pulse width of the switching signal S.sub.W before disabling the switching signal S.sub.W. The protection circuit includes a flip-flop 170. The first protection signal OFF1 is coupled to an input terminal D of the flip-flop 170. The clock signal C.sub.K is connected to a clock input terminal CK of the flip-flop 170 to set flip-flop 170 when the first protection signal OFF1 is enabled. An output terminal Q of the flip-flop 170 is coupled to disable the path for the reset of the flip-flop 110 through NOR gate 151, which allows the clock signal C.sub.K to turn on (enable) the switching signal S.sub.W with a specific pulse width (on-time).

(13) Once the switching signal S.sub.W is on state in response to the enable of the first protection signal OFF1, a pulse generator 120 generates a pulse signal BLK coupled to a second input terminal of the NAND gate 152 in response to the switching signal S.sub.W to determine this specific pulse width of the switching signal S.sub.W, Therefore, the pulse width of the switching signal S.sub.W is decreased to the specific value before the switching signal S.sub.W is disabled for the protection of the power converter. After the pulse signal BLK is generated, the pulse signal BLK will trigger a flip-flop 175 for latching off the enable signal EN. The enable signal EN coupled to the flip-flop 110 is utilized to enable the flip-flop 110 for generating the switching signal S.sub.W. The pulse signal BLK is coupled to a clock input terminal CK of the flip-flop 175. An input terminal D of the flip-flop 175 is coupled to receive a supply voltage V.sub.CC. An output terminal /Q of the flip-flop 175 generates the enable signal EN. A reset signal RST is coupled to a reset input terminal R of the flip-flop 175 to reset the flip-flop 175. The pulse signal BLK is further coupled to a reset input terminal R of the flip-flop 170 to reset the flip-flop 170.

(14) The second protection signal OFF2 (such as the over-temperature protection, the open-loop protection, the brownout protection, etc.) is coupled to the input circuit 300 to disable the switching signal S.sub.W through a micro-stepping circuit (MS) 350 (as shown in FIG. 5) that decreases the pulse width of the switching signal S.sub.W step by step in response to the feedback signal V.sub.FB.

(15) FIG. 3 is a circuit diagram of an embodiment of the pulse generator 120 according to the present invention. The pulse generator 120 comprises inverters 121, 127, a current source 122, a transistor 123, a capacitor 125, and an NAND gate 129. The switching signal S.sub.W is coupled to a gate of the transistor 123 to control the transistor 123 through the inverter 121. One terminal of the current source 122 is coupled to the supply voltage V.sub.CC. The other terminal of the current source 122 is coupled to a drain of the transistor 123, one terminal of the capacitor 125 and an input terminal of the inverter 127. A source of the transistor 123 and the other terminal of the capacitor 125 are coupled to the ground. The capacitor 125 is charged by the current source 122 when the switching signal S.sub.W is on state. An output terminal of the inverter 127 is coupled to a first input terminal of the NAND gate 129. A second input terminal of the NAND gate 129 is coupled to receive the switching signal S.sub.W. An output terminal of the NAND gate 129 generates the pulse signal BLK. The pulse width of the pulse signal BLK is determined by the level of the current source 122 and capacitance of the capacitor 125. That is, the level of the current source 122 and capacitance of the capacitor 125 determine the specific pulse width of the switching signal S.sub.W.

(16) FIG. 4 is a circuit diagram of an embodiment of the clock generator 200 according to the present invention. A capacitor 215 and a capacitor 216 are coupled to a signal generator (OSC) 250 to determine the frequency of the clock signal C.sub.K. A switch 211 coupled between the capacitor 216 and the signal generator 250 is controlled by a signal S.sub.X for switching the capacitor 216. When the switch 211 is turned off, the frequency of the clock signal C.sub.K will become higher. The signal generator 250 generates a pulse signal PLS. The pulse signal PLS is utilized to generate the clock signal C.sub.K via an inverter 270.

(17) The pulse signal PLS is further coupled to clock input terminals CK of flip-flops 230 and 231. The frequency modulation signal H/L coupled to an input terminal D of the flip-flop 230 is applied to enable/disable the flip-flop 230. An output terminal Q of the flip-flop 230 generates the on-time adjust signal S.sub.J in response to the pulse signal PLS. The on-time adjust signal S.sub.J is further coupled to an input terminal D of the flip-flop 231 to enable/disable the flip-flop 231 for generating the signal S.sub.X in response to the pulse signal PLS. The signal S.sub.X is generated by an output terminal Q of the flip-flop 231 via an inverter 271. The frequency modulation signal H/L is further connected to reset input terminals R of the flip-flops 230 and 231 to reset the flip-flops 230 and 231. Therefore, the on-time adjust signal S.sub.J is generated to reduce the pulse width of the switching signal S.sub.W before the signal S.sub.X is generated to increase the switching frequency of the switching signal S.sub.W.

(18) FIG. 5 is a circuit diagram of an embodiment of the input circuit 300 according to the present invention. The input circuit 300 comprises a feedback circuit and the micro-stepping circuit 350. The feedback circuit includes resistors 310, 325, 326, and a level-shift transistor 315 to receive the feedback voltage V.sub.FB for generating an attenuated feedback signal V.sub.A. The resistor 310 is coupled between a gate of the level-shift transistor 315 and the supply voltage V.sub.CC and applied to pull high the feedback signal V.sub.FB. A drain of the level-shift transistor 315 is also coupled to the supply voltage V.sub.CC. A gate of the level-shift transistor 315 is coupled to receive the feedback signal V.sub.FB for generating the attenuated feedback signal V.sub.A through the resistors 325 and 326. The attenuated feedback signal V.sub.A represents the feedback signal V.sub.FB. A terminal of the resistor 325 is coupled to a source of the level-shift transistor 315. The resistor 326 is coupled between the other terminal of the resistor 325 and the ground. The attenuated feedback signal V.sub.A is generated at a joint of the resistors 325 and 326.

(19) A first terminal of a resistor 327 is coupled to the joint of the resistors 325 and 326. A switch 331 is coupled between a second terminal of the resistor 327 and the ground. The resistor 327 is turned on/off by the switch 331. The switch 331 is controlled by the on-time adjust signal S.sub.J. When the switch 331 is turned on, the resistor 327 is further parallel connected to the resistor 326 for reducing the level of the attenuated feedback signal V.sub.A and decreasing the pulse width of the switching signal S.sub.W. The second protection signal OFF2 is coupled to turn on/off a switch 332. The switch 332 is coupled between the ground and the joint of the resistors 325 and 326. The switch 332 is utilized to connect the attenuated feedback signal V.sub.A to the ground (decrease to zero voltage) for disabling the switching signal S.sub.W. Therefore, the switch 332 serves as the protection circuit to disable the switching signal S.sub.W in response to the second protection signal OFF2.

(20) The micro-stepping circuit 350 slowly changes its output in accordance with its input signal. The micro-stepping circuit 350 generates the modulated feedback signal V.sub.B in accordance with the attenuated feedback signal V.sub.A for generating the switching signal S.sub.W. That is, the micro-stepping circuit 350 is coupled to receive the feedback signal V.sub.FB for generating the switching signal S.sub.W. Further, the micro-stepping circuit 350 is coupled to modulate the pulse width of the switching signal S.sub.W step by step in response to the feedback signal V.sub.FB.

(21) FIG. 6 is a circuit diagram of an embodiment of the micro-stepping circuit according to the present invention. A resistive device 351 and a capacitor 352 develop a pass filter with a time delay. A first terminal of the resistive device 351 is coupled to receive the attenuated feedback signal V.sub.A. The capacitor 352 is coupled between a second terminal of the resistive device 351 and the ground. Therefore, the pass filter generates the modulated feedback signal V.sub.B in accordance with the attenuated feedback signal V.sub.A, and the modulated feedback signal V.sub.B has the time delay comparing with the attenuated feedback signal V.sub.A.

(22) FIG. 7 is a circuit diagram of another embodiment of the micro-stepping circuit according to the present invention. The micro-stepping circuit comprises two current sources 381 and 382, two transistors 371 and 391, a capacitor 385, and a resistor 395. A terminal of the current source 381 is coupled to the supply voltage V.sub.CC. The other terminal of the current source 381 is coupled to a source of the transistor 371 and one terminal of the capacitor 385. The other terminal of the capacitor 385 is coupled to the ground. The current source 382 is coupled between a drain of the transistor 371 and the ground. A drain of the transistor 391 is coupled to the supply voltage V.sub.CC. A gate of the transistor 391 is coupled to the capacitor 385. The resistor 395 is coupled between a source of the transistor 391 and the ground.

(23) A gate of the transistor 371 is coupled to receive the attenuated feedback signal V.sub.A. The source of the transistor 371 is further coupled to the gate of the transistor 391 to generate the modulated feedback signal V.sub.B at the joint of the source of the transistor 391 and the resistor 395. The capacitor 385 and the current sources 381, 382 are coupled in between the transistor 371 and the transistor 391 for developing a linear time delay and performing the micro-stepping. The level of the current sources 381, 382 and the capacitance of the capacitor 385 determine the slew rate of the micro-stepping.

(24) Although the present invention and the advantages thereof have been described in detail, it should be understood that various changes, substitutions, and alternations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims. That is, the discussion included in this invention is intended to serve as a basic description. It should be understood that the specific discussion may not explicitly describe all embodiments possible; many alternatives are implicit. The generic nature of the invention may not fully explained and may not explicitly show that how each feature or element can actually be representative of a broader function or of a great variety of alternative or equivalent elements. Again, these are implicitly included in this disclosure. Neither the description nor the terminology is intended to limit the scope of the claims.