OPTICAL TRANSCEIVER BY FOWLP AND DOP MULTICHIP INTEGRATION

Abstract

An optical transceiver by hybrid multichip integration. The optical transceiver includes a PCB with a plurality of prefabricated surface bonding sites. A first chip includes a FOWLP package of multiple electronics devices embedded in a dielectric molding layer overlying a dielectric redistribution layer is disposed on the PCB by respectively bonding a plurality of conductor balls between the dielectric redistribution layer and the plurality of prefabricated surface bonding sites while exposing soldering material filled in multiple through-mold vias (TMVs) in the dielectric molding layer. The optical transceiver further includes a second chip configured as a Sipho die comprising photonics devices embedded in a SOI wafer substantially free from any electronics device process. The second chip is stacked over the first chip with multiple conductor bumps being bonded respectively to the soldering material in the multiple TMVs.

Claims

1. An optical transceiver by hybrid multichip integration comprising: a PCB with a plurality of prefabricated surface bonding sites; a first chip comprising multiple electronics devices embedded in a dielectric molding layer overlying a dielectric redistribution layer, the first chip being disposed on the PCB by bonding the dielectric redistribution layer via a plurality of conductor balls respectively on the plurality of prefabricated surface bonding sites while exposing soldering material filled in multiple through-mold vias (TMVs) formed in the dielectric molding layer; and a second chip comprising photonics devices embedded in a SOI wafer having a front surface with multiple conductor bumps being added, the second chip being stacked over the first chip with the multiple conductor bumps on the front surface being bonded respectively to the soldering material in the multiple TMVs.

2. The optical transceiver of claim 1 wherein the first chip comprises multiple electronics dies packaged together using an Embedding Insulation Sheet (EBIS) type material for the dielectric molding layer under a fan-out wafer level package (FOWLP) architecture overlying a HD-8940 PBO film for the dielectric redistribution layer.

3. The optical transceiver of claim 1 wherein the multiple electronics devices comprise a PAM4 ASIC module, a driver module, a trans-impedance amplifier module, and multiple AC coupling capacitors.

4. The optical transceiver of claim 1 wherein each of the plurality of conductor balls is bonded to a first conductive pad embedded in the dielectric redistribution layer.

5. The optical transceiver of claim 1 wherein the soldering material filled in each of the multiple TMVs is bonded to a second conductive pad embedded in the dielectric redistribution layer.

6. The optical transceiver of claim 1 wherein the second chip is a Si-photonics chip substantially free from through-silicon via structures.

7. The optical transceiver of claim 6 wherein the photonics devices comprise Si-based optical waveguides, a modulator, and multiple photo diodes.

8. The optical transceiver of claim 6 wherein the second chip further comprises one or more laser diodes mounted on a recessed region of the front surface and electrically coupled via a mounting pad with at one or more of multiple conductor bumps through one or more conductive pads in the dielectric redistribution layer and one or more of the plurality of conductor balls to connect to the PCB without any external wire bonds.

9. The optical transceiver of claim 6 wherein the second chip further comprises one or more fiber coupling structures formed near an edge of the front surface.

10. The optical transceiver of claim 7 wherein the dielectric redistribution layer further comprises embedded conductive wires for selectively connecting the multiple electronics devices to at least the modulator and the multiple photo diodes respectively through the soldering material filled in the multiple TMVs and the multiple conductor bumps on the front surface of the second chip.

11. The optical transceiver of claim 10 further comprising one or more optical fibers being installed in the one or more fiber coupling structures between the front surface of the second chip and the dielectric molding layer of the first chip to couple with corresponding Si-based optical waveguides.

12. A method for assembling a compact optical transceiver comprising: providing a PCB with a plurality of prefabricated surface bonding sites; packaging a first chip by embedding multiple electronics devices in a dielectric molding layer overlying a dielectric redistribution layer; adding a plurality of conductor balls to a back-end surface of the dielectric redistribution layer; forming multiple through-mold vias (TMVs) in the dielectric molding layer, each TMV being filled with a soldering material; disposing the first chip on the PCB by bonding the plurality of conductor balls respectively onto the plurality of prefabricated surface bonding sites while exposing the soldering material filled in the multiple TMVs; forming a second chip comprising photonics devices embedded beneath a front surface of a SOI wafer without any through-silicon via structure; adding multiple conductor bumps on the front surface; and flipping the second chip to bond the multiple conductor bumps respectively to the soldering material in the multiple TMVs in the dielectric molding layer of the first chip.

13. The method of claim 12 wherein packaging a first chip comprises utilizing an Embedding Insulation Sheet (EBIS) type material as the dielectric molding layer for packaging several electronics dies together under a fan-out wafer level package (FOWLP) architecture overlying a HD-8940 PBO film as the dielectric redistribution layer.

14. The method of claim 12 wherein adding a plurality of conductor balls comprises forming electrical connections between each of the plurality of conductor balls and selected one or more of the multiple electronics devices via internal conductive pads and wirings formed by back-end patterning processes in the dielectric redistribution layer.

15. The method of claim 14 wherein forming multiple TMVs comprises forming straight profile via structure through total thickness of the dielectric molding layer by a laser or chemical etching technique to reach a conductive pad in the dielectric redistribution layer so that the soldering material filled in each TMV forms a electrical contact with the conductive pad to connect selected one or more of the multiple electronics devices embedded in the dielectric molding layer.

16. The method of claim 12 wherein the multiple electronics devices comprise a PAM4 ASIC module, a driver module, a trans-impedance amplifier module, and multiple AC coupling capacitors.

17. The method of claim 12 wherein the photonics devices comprise Si-based optical waveguides, a modulator, and multiple photo diodes.

18. The method of claim 17 further comprising mounting one or more laser diodes on a recessed region of the front surface.

19. The method of claim 18 wherein adding multiple conductor bumps comprises drawing power from an external source for the one or more laser diodes by forming electrical contacts with one or more conductive pads in the dielectric redistribution layer through one or more of the plurality of conductor balls to connect to the PCB without using any external wire bonds.

20. The method of claim 18 wherein adding multiple conductor bumps further comprises forming electrical connection between the modulator and multiple photo diodes in the second chip and selected one or more of the multiple electronics devices in the first chip via soldering material filled in corresponding TMVs.

21. The method of claim 12 wherein forming the second chip comprising forming a single silicon-photonics die substantially free from any electronics device process.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The following diagrams are merely examples, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize many other variations, modifications, and alternatives. It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this process and scope of the appended claims.

[0013] FIG. 1 is a top view of an optical transceiver assembled by DoP process on a PCB according to an embodiment of the present invention.

[0014] FIG. 2 is a diagram showing cross-sectional AA′ cut view of the optical transceiver assembly of FIG. 1 according to the embodiment of the present invention.

[0015] FIG. 3 is a diagram showing cross-sectional BB′ cut view of the optical transceiver assembly of FIG. 1 according to the embodiment of the present invention.

[0016] FIG. 4 is a diagram showing cross-sectional CC′ cut view of the optical transceiver assembly of FIG. 1 according to the embodiment of the present invention.

[0017] FIGS. 5A-5D are diagrams showing a series of processes for assembling a compact optical transceiver according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0018] The present disclosure is related to an integrated photonics device. More particularly, a high-speed compact optical transceiver is formed by a die-on-package (DoP) multichip integration of a high-yield silicon photonics chip stacking over a FOWLP packaged electronics chip with through-mold vias (TMVs) for electrical coupling. In certain embodiments, the invention is applied for high speed optical communication, though other applications are possible.

[0019] The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it in the context of particular applications. Various modifications, as well as a variety of uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0020] In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

[0021] The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification, (including any accompanying claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

[0022] Furthermore, any element in a claim that does not explicitly state “means for” performing a specified function, or “step for” performing a specific function, is not to be interpreted as a “means” or “step” clause as specified in 35 U.S.C. Section 112, Paragraph 6. In particular, the use of “step of” or “act of” in the Claims herein is not intended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.

[0023] Please note, if used, the labels left, right, front, back, top, bottom, forward, reverse, clockwise and counter clockwise have been used for convenience purposes only and are not intended to imply any particular fixed direction. Instead, they are used to reflect relative locations and/or directions between various portions of an object.

[0024] FIG. 1 is a top view of an optical transceiver assembled by multichip integration including FOWLP and DoP process on a PCB according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown, an optical transceiver 100 is assembled by multichip integration. A first chip is formed under a Fan-Out Wafer Level Packaging (FOWLP) architecture to integrate all critical electronics dies needed for an optical transceiver. A second chip is formed as a single

[0025] Si-photonics (Sipho) die to integrate major photonics parts including surface-mounted laser diode. The second chip or Si-photonics die is stacked over the first chip in a Die-on-Package process to couple the corresponding electronics devices in the first chip by employing through-mold via (TMV) technology.

[0026] Referring to FIG. 1, in the top view of the assembled optical transceiver 100, a molding material 110 covers multiple electronics devices in a package disposed on the PCB 101. The multiple electronics devices are either separate electronics dies including PAM4 ASIC module 122, Driver module 124, Trans-impedance Amplifier module 126, or multiple individual AC coupling capacitors 128 and other passive components 127. On an exposed front-end surface of the molding material 110, a Sipho die 130 is disposed by flipping its front surface to face the exposed front-end surface of the molding material 110. As seen, one or more laser diodes 132 are mounted on front surface of the Sipho die that faces down in this top view. Other components of the optical transceiver 100 including at least a microcontroller unit (MCU) 141 and a power management unit (PMU) 142 are directly assembled on the PCB 101. Additional features of the assembly structure of the compact optical transceiver 100 can be found below in several cross sectional cut views along lines AA′, BB′, and CC′.

[0027] FIG. 2 is a diagram showing cross-sectional AA′ cut view of the optical transceiver assembly of FIG. 1 according to the embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown in this AA′ cut view, a first chip is bonded to a surface of the PCB 101 by a plurality of balls 119. The first chip, as mentioned earlier in FIG. 1, is a FOWLP package of multiple electronics dies. Particularly in this cut view, a PAM4 ASIC module 122, a Driver module 124, and several AC coupling capacitors (CAP) 128 are embedded in a molding material 110. The molding material 110 is an Embedding Insulation Sheet (EBIS) type dielectric material commonly used for the FOWLP package process.

[0028] As seen, the molding material 110 is formed overlying another dielectric material served as a redistribution layer (RDL) 113. This RDL 113 includes multiple patterned or separately embedded conductive pads or wirings 115. On a back-end surface of RDL 113, a plurality of conductor balls 119 are added via a back-end process before disposing the FOWLP package onto corresponding a plurality of prefabricated surface bonding sites of the PCB 101. Each of the plurality of conductor balls 119 forms an electrical contact to a conductive pad inside the RDL 113 and is led to other locations of the 2D plane of the RDL 113 for connecting to designated electronics devices in the FOWLP package. Of course, the plurality of conductor balls 119 also connect the internal wirings of the PCB that lead to other electronics devices on the PCB such as MCU or PMU or other external sources for operating the optical transceiver.

[0029] Additionally shown in FIG. 2, a second chip 130 is stacked over the first chip. In an embodiment, the second chip 130 is formed as a Sipho die by integrating substantially all photonics devices only without including any electronics device process and any costly trans-silicon via (TSV) structure through the fragile photonics devices. In an example, the photonics devices in the Sipho die 130 include optical modulator 135, multiple photo diodes (137 in FIG. 4), and Si or SiN based optical waveguides for beam couplers/splitters or mux/demux devices (not explicitly shown). In another example, several fiber coupling structures 134 or 136 are formed on the front surface of the second chip for either coupling laser outputs or optical fibers for input/output optical signals of the optical transceiver.

[0030] Referring again to FIG. 2, such multichip stacking integration is achieved by utilizing a TMV technology via a Die-on-Package process. Before stacking the second chip, on the exposed front-end surface of the molding material 110 multiple through-mold via (TMV) structures are formed with straight profile through the whole thickness of the molding material 110 in multiple patterned locations to reach corresponding conductive pads in the RDL 113. A soldering material 129 is dropped in to substantially fill the whole via with its tip near or slightly above the front-end surface of the molding material 110. Accordingly, the second chip 130, after a separate packaging process to form a Sipho die, is prepared by adding multiple conductor bumps 139 on its front surface in locations that are designated to match the patterned locations of multiple TMVs. Now, the second chip 130 is flipped over to make the front surface facing down the exposed front-end surface of the molding material so that the multiple conductor bumps 139 are respectively bonded (by soldering) to soldering material in the multiple TMVs.

[0031] The bonding between the second chip and the first chip via the TMV structure via conductor bump 139 provides a low-parasitic electrical connection for designated opto-electrical control and signal communication between the electronics devices in the first chip and the photonics devices in the second chip. For example, the modulator 135 embedded in the Sipho die 130 is connected, via one of the multiple conductor bump 139 through a soldering material 129 and one or more conductive pads and wirings in the RDL 113, to the Driver module 124 to modulate output laser light based on designated digital signal patterns. In another example, the photo diodes 137 (see FIG. 4 below) are also electrically coupled, via one of the multiple conductor bump 139 through a soldering material 129 and one or more conductive pads and wirings in the RDL 113, to send converted current signals (from received optical signals) to the Trans-impedance Amplifier module 126. No wirebonds exist in the whole optical transceiver package on PCB assembly. The wirebonds-free assembly scheme makes the optical transceiver capable of delivering >56Gbaud symbol rate, and thus capable of delivering 112 Gbps with PAM4 signal modulation format.

[0032] In another embodiment, one or more laser diodes 132 are mounted on a prefabricated recess region 131 of the front surface where a conductive pad 133 can be disposed for receiving the laser diodes 132. The conductive pad 133 includes an extended portion at a normal (not-recessed) region on the front surface. When adding multiple conductor bumps 139 on the front surface, at least one conductor bump is attached the extended portion of the conductive pad 133 for providing DC power for the laser diodes 132. The recessed region 131 is formed to allow a sufficient gap between the flip-bonding Sipho die on the FOWLP package even with the surface mounting laser diodes being installed there. Again, no wirebonds exist in this DoP process, even the wire bonds typically used for powering laser diodes are replaced by bump bonds and internal wirings to reduce overall parasitic capacitance.

[0033] FIG. 3 is a diagram showing cross-sectional BB′ cut view of the optical transceiver assembly of FIG. 1 according to the embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown in the particular cut view along BB′ line, an optical fiber 138 is coupled to the corresponding fiber coupling structure 136 formed in the front surface of the second chip 130. In this multichip stacking configuration, at least a section of the optical fiber 138 is capped between the front surface of the second chip and the front-end surface of the molding material 110 of the first chip. In a specific embodiment, the fiber coupling structure 136 is formed to align optical core of the optical fiber 138 with the optical waveguides in the Sipho die 130. The proper alignment may be achieved by proper positioning the fiber coupling structures 136 such as V-groove at a recessed region of the front surface when forming the Sipho die 130.

[0034] FIG. 4 is a diagram showing cross-sectional CC′ cut view of the optical transceiver assembly of FIG. 1 according to the embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown in the particular cut view along CC′ line, a first chip is bonded to the PCB 101 via a plurality of balls 119. The first chip, as mentioned earlier in FIG. 1 and FIG. 2, is a FOWLP package of multiple electronics dies. Particularly in this cut view, a PAM4 ASIC module 122, a Trans-impedance Amplifier (TIA) module 126, and several AC coupling capacitors (CAP) 128 are embedded in a molding material 110. The second chip, as mentioned earlier in FIG. 1, FIG. 2 and FIG. 3, is a Sipho die 130 that integrates substantially all photonics devices including embedded photo diodes 137 and surface mounted laser diodes 132 and optical fibers 138. The bonding between the second chip and the first chip via the TMV structure via conductor bump 139 provides a low-parasitic electrical connection for designated opto-electrical control and signal communication between the electronics devices, such as TIA 126, in the first chip and the photonics devices, such as photo diodes 137, in the second chip.

[0035] In an alternative embodiment, the present invention also provides a method for assembling a compact optical transceiver by illustrating a few key processes based on a multichip stacking integration employing low cost FOWLP architecture and TMV technology for facilitating a DoP process. FIGS. 5A-5D are diagrams showing a series of processes of the method according to an embodiment of the present invention. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. One or more processes may be skipped by the illustration of just four snap shots of the whole assembly processes. One of the existing or additionally processes may be inserted in more than single sequential orders. Other processes may be included upon minor changes in components while not affecting the main sequence of the assembly process.

[0036] Referring to FIG. 5A in a cross-sectional view, a FOWLP package is formed with multiple electronics devices embedded in a dielectric molding layer 110 overlying a dielectric redistribution layer 113. The dielectric molding layer 110 leaves a front-end surface 111 and the dielectric redistribution layer 113 has a back-end surface 112. The FOWLP package basically integrates substantially all electronics dies including PAM4 or CDR, driver, and TIA for assembling an optical transceiver. Being incorporated as part of the FOWLP process, a TMV process is performed to create multiple straight profiled through-mold vias (TMVs) in multiple patterned locations. Additionally, the FOWLP process also includes a formation of patterned conductive pads 115 or wirings in the dielectric redistribution layer 113. These conductive pads 115 are selectively formed, using Cu material through a back-end process, at certain locations in the front end surface (not exposed) and alternative locations in the back-end surface 112. A 2-dimensional network of conductive wirings is also formed therein to selectively connect those conductive pads based on the designated application.

[0037] In an embodiment, each TMV is created by laser process to etch or drill down from the front-end surface 111 with high aspect ratio through the whole thickness of the molding layer 110 to reach one of the conductive pad 115 at the front end (generally not exposed) of the dielectric redistribution layer 113. Following the formation of multiple TMVs, a soldering material 129 is dropped into each TMV following a formation of UBM structure on the Cu pad by electroless Ni/Au plating. In certain embodiments, the soldering material is sufficiently filled each TMV such that a tip portion of the soldering material 129 is near or slightly above the front-end surface 112.

[0038] In another embodiment, the FOWLP process also includes a back-end surface bump formation process. In particular, on the back-end surface 112, a plurality of conductor balls 119 (usually made of a selected soldering material or alloy) is formed at predetermined locations that are matched with a plurality of prefabricated surface bonding sites on the PCB 101.

[0039] Referring to FIG. 5B in a cross-sectional view, a Si-photonics (Sipho) die 130 is formed separately to integrate photonics devices only. No critical electronics device process is done with this die. Particularly, the Sipho die 130 is made from a piece of SOI wafer in which various optical waveguides and optical components are formed. In an example, the optical waveguides can be Si-based or Si.sub.3N.sub.4-based to provide optical beam coupling/splitting or wavelength mux/demux functions. Other components including optoelectronic devices such as laser modulator 135 and photo diodes can be also embedded beneath a front surface 130F of the Sipho die 130. But, no any through-Silicon via structure is included in the Sipho die formation process to avoid easy damage to the embedded photonics devices or near-surface optical components in the thin SOI wafer and any associated low-yield production issue.

[0040] In a specific embodiment, the Sipho die formation process also includes forming a recessed region 131 in the front surface 130F and a conductive pad 133 can be laid out and placed over the recessed region 131 including at least one extended portion with regular level of the front surface 130F. This recessed region 131 plus corresponding conductive pad 133 provides a base for mounting one or more laser diodes 132. The laser diodes 132 has all its corresponding electrical connections especially those for receiving a DC current for driving laser excitations being established through the conductive pad 133.

[0041] In another specific embodiment, a follow-up process of preparing the Sipho die 130 includes adding multiple conductor bumps 139 on multiple selected locations on the front surface 130F including the at least one extended portion of conductive pad 133. Nevertheless, the multiple conductor bumps, each may be made of a selected soldering material, are configured to form electrical connection for the embedded laser modulator 135 or photo diodes as well as for the surface mounted laser diodes 132.

[0042] Referring to FIG. 5C, the optical transceiver assembly process is performed by a multichip 3D stacking integration. The FOWLP package is disposed on the PCB 101 with the back-end surface 112 facing the PCB so that the plurality of conductor balls 119 is respectively bonded to the plurality of prefabricated surface bonding sites of the PCB 101. These bump bonds substantially establish necessary electrical connections of the multiple electronics devices in the FOWLP package between themselves or between them and external devices without using any wire bonds. Thus, desired very low parasitic capacitance for the attachment of the FOWLP package on the PCB can be achieved for assembling a high (>56) Gbaud symbol rate transceiver.

[0043] Additionally, the Sipho die 130 is flipped over to have the front surface 130F facing the front surface 112 of the molding material 110 of the FOWLP package. A Die-on-Package process is performed by bonding the multiple conductor bumps 139 directly onto respective tip portion of soldering material 129 in the multiple TMVs formed in the molding material 110. Again, the attachment of Sipho die 130 on the FOWLP package requires no wire bonds even for the power line of the one or more laser diodes 132. Instead, TMV technology is employed to make vertical interconnect between top Sipho die and bottom electronics dies in FOWLP package. This provides tremendous flexibility to various electronic technology nodes and is beneficial for the optical transceiver designer to change particular technology for optimizing the performance of modulator driver/TIA modules by selecting either SiGe, GaAs, or CMOS technology and enhancing the performance of CDR or PAM4 ASIC under 45 nm, 28 nm, 20 nm CMOS technology scaling up.

[0044] Referring to FIG. 5D in an alternative cross-sectional view of the assembled optical transceiver on the PCB, after the DoP process multichip stacking of the Sipho die 130 on the FOWLP packaged chip, one or more optical fibers 138 are attached to one or more prefabricated fiber coupling structures 136 on an edge of the front surface 130F of Sipho die 130. Now the locations of fiber coupling structures 136 are somewhere between the front surface 130F and the front-end surface 111 of the molding material 110. In an embodiment, the front surface 130F of the Sipho die 130 is properly recessed from the end region to allow space for installing the optical fibers 138 such that the fiber core can be properly aligned (and fixed) to the optical waveguides in the Sipho die 130. Of course, one of ordinary skill in the art shall recognize many variations, alternatives, and modifications about the optical fiber installation on to the compact optical transceiver.

[0045] While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.