LOW-CONSUMPTION RRAM MEMORY DIFFERENTIAL READING
20220238154 · 2022-07-28
Assignee
Inventors
Cpc classification
G11C2013/0042
PHYSICS
International classification
Abstract
A Resistive random access memory (ReRAM) comprising: an array (M.sub.1) of cells (C.sub.ij) each connected to a first supply line (SL) set at a first supply potential, each cell being provided with a resistive element (1, 2) and a selection transistor (Ms.sub.1, Ms.sub.2), a read circuit (40.sub.0) associated with a given row of cells and comprising a sense amplifier (44.sub.0) of the latch type connected to a second supply line (45) set at a second supply potential, the device further comprising: a circuit for controlling read operations configured to during a reading: apply to said first bit line (BL.sub.0) a potential equal to said first supply potential (GND, VDD) while isolating the first bit line (BL.sub.0) from said sense amplifier (44.sub.0), then, couple the first bit line (BL.sub.0) to said sense amplifier (44.sub.0).
Claims
1. A resistive random access memory (ReRAM) device comprising: an array of memory cells each connected to a first supply line set at a first supply potential, each cell of said array being provided with at least one first resistive element of variable resistivity and in series with at least one first selection transistor, a read circuit associated with a column of cells of the array, the read circuit comprising: a sense amplifier of the latch type consisting of cross-connected inverters and equipped with a first read node and a second read node, said inverters respectively forming a first branch and a second branch each connected on one side to a second supply line set at a second supply potential, different from said first supply potential, at least one first coupling transistor connecting another side of said first branch to a first bit line coupled to the first respective resistive elements of the cells of said column, at least one second coupling transistor connecting another side of said second branch either to a second bit line coupled to the second resistive elements of the cells of said column, or to a reference line delivering a reference current; a circuit for controlling read operations on the array by way of signals for controlling switch elements, said control circuit being configured to, during a read operation carried out on a given cell of said column: according to a waiting phase, charge said first bit line to a potential equal or close or substantially equal to said first supply potential, then, according to a reset phase of said sense amplifier, by way of at least one reset transistor connect the first read node and the second read node, so as to equalise the potentials of the first read node and of the second read node; according to a partial discharge phase, connect the first bit line to the second supply line and when the device includes the second bit line connect the second bit line to the second supply line, so as to partially discharge said first bit line or said bit lines and obtain at the terminals of the cells of said column a non-zero difference of potentials while being lower, and in particular much lower, than a difference of potentials between the first supply potential and said second supply potential, the reset phase being triggered during the partial discharge phase; then according to a comparison phase, during which said first and second coupling transistors are rendered conducting, and said at least one reset transistor is rendered non-conducting, in order to make possible a circulation of a first current through said first branch of said sense amplifier, the first bit line and a first resistive element of said cell and a circulation of a second current through said second branch of said sense amplifier as well as either the reference line or the second bit line and a second resistive element of said cell, until a toggling of said sense amplifier according to a difference between said first and second currents.
2. The resistive random access memory device according to claim 1, wherein from said switch elements figures at least one first reset transistor belonging to a reset stage of said sense amplifier, and controlled by way of a first control signal, said control circuit being configured to: during said reset phase, maintain conducting the first reset transistor, so as to interconnect the first read node and the second read node, or connect the first read node to the second supply line or connect a first terminal and a second terminal of the first inverter to the second supply line, and during the comparison phase place the first control signal in a second state, different from said first state, so that said first reset transistor is non-conducting.
3. The resistive random access memory device according to claim 2, wherein said at least one first coupling transistor is or comprises a first isolation transistor arranged between said sense amplifier and said first bit line, said first isolation transistor being controlled by way of at least one second control signal, the control circuit being further configured to: during the waiting phase, place said second control signal in a given state so as to render OFF the first isolation transistor and thus isolate the first bit line from said sense amplifier and place said first control signal in a state so as to maintain conducting the first reset transistor, said control circuit being further configured to during partial discharge and comparison phases: place said second control signal in another state, different from said given state, so as to render conducting the first isolation transistor and thus connect the first bit line to said sense amplifier.
4. The resistive random access memory device according to claim 3, wherein the memory cells are each provided with at least one second resistive element in series with a second selection transistor, said column of cells being coupled to said second bit line, said at least one second coupling transistor being or comprising a second isolation transistor between the sense amplifier and said second bit line, the second isolation transistor being controlled by way of said second control signal.
5. The resistive random access memory device according to claim 4, wherein the read circuit further comprises: a third isolation transistor and a fourth isolation transistor, the third isolation transistor and the fourth isolation transistor being cross-connected so that the third isolation transistor has a first electrode coupled to the first isolation transistor and a second electrode coupled to the second isolation transistor and so that the fourth isolation transistor has a first electrode coupled to the second isolation transistor and a second electrode coupled to the first isolation transistor.
6. The resistive random access memory device according to claim 4, able to carry out memory operations, in particular at least one logic operation, said control circuit being further provided with: a control logic block configured to produce drive signals of the respective gates of said isolation transistors according to at least one digital operating mode selection signal emitted over one or more inputs of said control logic block and of a volatile logic data as input of said control logic block, to select between a first operating mode of the read circuit corresponding to a read operation and at least one other operating mode of the read circuit corresponding to the implementation of at least one logic operation between at least one non-volatile data stored in the given cell of the given row of cells and the volatile logic data as input of said control logic block, said control logic block being configured to: when the digital selection signal has a first value corresponding to a selection of a read operation: apply drive signals of the gate of the first isolation transistor and to the gate of the second isolation transistor corresponding to the second control signal, when the digital selection signal has a value different from the first value and corresponding to a selection of a logic operation: transmit a first drive signal to the gate of the first isolation transistor and a second drive signal to the gate of the second isolation transistor, so as to block one of said first and second isolation transistors while rendering conducting the other of said first and second isolation transistors.
7. The resistive random access memory device according to claim 6, wherein the read circuit further comprises: a third isolation transistor and a fourth isolation transistor cross-connected, the control logic block being further configured to produce a drive signal of the respective gates of said third and fourth isolation transistors and wherein: when said other value is a second value corresponding to a selection of a first logic operation, in particular of the OR type or of the AND type, the control logic block is configured so as to produce a first drive signal, a second drive signal different from the first drive signal, so as to render conducting the first isolation transistor while rendering OFF the second isolation transistor, when said other value is a third value corresponding to a selection of a second logic operation, in particular of the AND type or of the OR type: transmit a first drive signal and a second drive signal so as to render OFF the first isolation transistor while rendering conducting the second isolation transistor, when the digital selection signal has a fourth value corresponding to a selection of a third logic operation, in particular of the XOR type, said logic selection block is configured so as to transmit a first drive signal to the gate of the first isolation transistor and a second drive signal to the gate of the second isolation transistor identical to the first drive signal, the third drive signal being in a state different from that of the first drive signal and from the second drive signal.
8. The resistive random access memory device according to claim 2, comprising: a first reset transistor coupled to the second node and to the second supply line, the first reset transistor having a gate controlled by the first control signal, a second reset transistor coupled to the first node and to the second supply line, the second reset transistor having a gate controlled by the first control signal.
9. The resistive random access memory device according to claim 2, further comprising: a reset transistor having a gate controlled by the first control signal, the reset transistor being arranged between said first node and said second node.
10. The resistive random access memory device according to claim 1, wherein said read circuit is further provided, as output of said sense amplifier, with at least one memory storage element, configured to keep a data produced as output of said sense amplifier during said comparison phase after said toggling, said memory storage element being in particular provided with: an RS flip-flop provided with an input coupled to the first read node and with another input coupled to the second read node, or a D flip-flop comprising an input coupled to the first read node or the second read node.
11. The resistive random access memory device according to claim 1, wherein during the partial discharge phase, the first bit line is connected to the second supply line by means of a first reset transistor rendered conducting by way of a first control signal, and by means of the first coupling transistor rendered conducting by way of a second control signal.
12. The resistive random access memory device according to claim 1, wherein during a waiting phase following a comparison phase of a preceding read operation, said sense amplifier is maintained in a latched state after its toggling, without reset, and wherein said first bit line recharges by a current passing through at least one selected cell of said column.
13. The resistive random access memory device according to claim 12, wherein the reset phase is performed only at the same time as the partial discharge phase.
14. The resistive random access memory device according to claim 1, wherein from said switch elements figures at least one switch element controlled by way of a first control signal and wherein said control circuit is further provided with a first comparator that receives a measured voltage of the first bit line, and produces as output the first control signal the state of which depends on a comparison carried out by said first comparator between said measured voltage and a predetermined reference voltage.
15. The resistive random access memory device according to claim 14, wherein said column is coupled to a first bit line and to a second bit line, and wherein the control circuit is provided with a second comparator that receives another measured voltage of said second bit line, the state of the first control signal further depending on a comparison carried out by said second comparator.
16. The resistive random access memory device according to claim 15, wherein the device further comprises: at least one first so-called “repolarisation” transistor arranged between the first bit line and said first supply line, the first repolarisation transistor being configured to, according to a repolarisation drive signal applied on its gate, alternately couple the first supply line to the first bit line and uncouple the first supply line from the first bit line, said first repolarisation transistor being rendered conducting in a waiting phase and non-conducting during said partial discharge and comparison phases.
17. The resistive random access memory device according to claim 16, wherein said at least one first coupling transistor is or comprises a first separation transistor between the first bit line and the sense amplifier, the first separation transistor being controlled by an additional control signal called “read enable signal”, the control circuit being configured to place said read enable signal in a state determined during said read operation so as to render conducting the first separation transistor, and place said read enable signal in another state, different from said determined state, during a write operation on the array so as to block the first separation transistor.
18. The resistive random access memory device according to claim 17, wherein said at least one first coupling transistor includes a transistor with a gate dielectric thicker than the gate dielectric of transistors constituting said sense amplifier.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0077] The present invention will be better understood upon reading the description of examples of embodiment given, purely by way of indicative and non-limiting example, while referring to the appended drawings wherein:
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[0108] Furthermore, in the description hereafter, terms that depend on the orientation of the device such as for example “vertical”, “horizontal” are applied by considering that the device is oriented in the manner illustrated in the figures.
[0109] Identical, similar or equivalent portions of various figures bear the same numerical references such as to facilitate the change from one figure to the other.
DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS
[0110] As an introductory remark, in the present application the reference system of the “0” or “1” logic levels will be used to signify respectively, by shortcut, a low potential, for example equal to a ground gnd, and a high potential, for example equal to a supply voltage Vdd.
[0111] Reference is now made to
[0112] The cell C.sub.ij is provided to keep a binary data and a conventional arrangement, with, in this example, two resistive elements 1, 2, of variable resistivity between two LRS and HRS resistivity levels, and imposed by read operations, the level imposed on the first resistive element 1, in the example illustrated noted LRS, being different from that imposed on the second resistive element 2 and which, in the example illustrated, is noted HRS. The resistive elements 1, 2 of the same cell are thus written in opposition of state.
[0113] The resistive elements 1, 2 are each equipped with an electrode coupled to a so-called “source” line SL and to another electrode coupled to a selection transistor M.sub.s1, M.sub.s2. According to a particular embodiment, the resistive elements 1, 2 are of the OxRAM type.
[0114] In an elementary cell, two selection transistors M.sub.s1, M.sub.s2, the gates of which are controlled by a signal conveyed by the same word line WL.sub.i thus make it possible, alternately to couple or uncouple the resistive elements 1, 2, respectively to/from a first bit line BL.sub.j and to/from a second bit line BL.sub.j+1. The term “coupled” is used throughout the present application to designate a direct electrical connection or a connection established via one or more intermediate components (resistance(s), transistor(s), etc.).
[0115] In this example, the elementary cells are thus of the “2T-2R” type with two resistive elements 1, 2 and two selection transistors M.sub.s1, M.sub.s2 per cell.
[0116] In an array M.sub.1 of cells, a partial view of which is given by way of example in
[0117] It will be noted that the array of memory cells may be accessed in read or in write (including the useful erasure for some resistive memory technologies). In the present invention the read mode is more particularly of interest. In read mode, the source line SL is in the examples described permanently connected to the same supply potential. In the example being described, this supply potential is “high”, here equal to VDD.
[0118] During a write mode, the source line SL may for example be connected to the ground GND by a source line driver 10.
[0119] The array M.sub.1 is also associated, as illustrated in
[0120] The memory device is also typically provided with bit line drivers, for example one driver 30.sub.0, . . . , 30.sub.m−1 per bit line, so that for an array of m/2 columns of cells and two bit lines per column, the memory device includes m bit line drivers 30.sub.0, . . . , 30.sub.m−1, each making it possible to select the cells of the same column of cells.
[0121] Around the periphery of the array, and in particular at the base of each pair of columns, a read circuit 40.sub.0, . . . , 40.sub.m/2−1 is provided to make it possible to translate into a binary data on the respective output OUT.sub.0, . . . , OUT.sub.m/2−1 from such a read circuit the resistive states of the resistive elements 1, 2 of a ReRAM memory cell which is read accessed.
[0122] In order to improve the read operations, and in particular to reduce the dynamic consumption during read operations, the read circuits 40.sub.0, 40.sub.1, . . . , 40.sub.m/2−1 each coupled to a pair BL.sub.0-BL.sub.1, . . . , BL.sub.m−2-BL.sub.m−1 of bit lines are here provided with a particular arrangement.
[0123] An example of embodiment of a read circuit 40.sub.0 is given in
[0124] The read circuit 40.sub.0 is provided with a stage 44.sub.0 forming a sense amplifier also called read amplifier, of the latch type.
[0125] The sense amplifier 44.sub.0 is here provided with transistors M.sub.41, M.sub.43 forming a first inverter and with transistors M.sub.42, M.sub.44 forming a second inverter, the first inverter and the second inverter being cross-connected i.e. with an input of the first inverter corresponding to the output of the second inverter and the output of the second inverter corresponding to the input of the first inverter. The sense amplifier 44.sub.0 is thus provided with a first read node N.sub.1 connecting the input of the first inverter and the output of the second inverter, whereas a second read node N.sub.2 connects the input of the second inverter and the output of the first inverter.
[0126] The sense amplifier 44.sub.0 is further connected to a second supply line 45 set at a potential different from that of the first supply line or source line SL. Typically, the second supply line 45 is set at a high potential when the first corresponding supply line or source line SL is set at a low potential and vice versa. In the particular example of embodiment illustrated the second supply line 45 is set at a high potential corresponding to the supply voltage VDD.
[0127] Each inverter of the sense amplifier 40.sub.0 constitutes a branch connected on the one hand to the second supply line and on the other hand to a bit line, the first and second inverters thus constitute first and second branches respectively connected to the bit lines BL.sub.0 and BL.sub.1.
[0128] When a read operation is carried out on the cell C.sub.i0, the difference of resistance between the resistive element 1, and the resistive element 2 results in a current imbalance between the two branches of the amplifier 44.sub.0 each connected to one of these resistive elements, and between two respective read nodes N.sub.1, N.sub.2 of these branches. If the two nodes N1 and N2 are both initially at the same potential, for example equal to the second supply line 45, the consequence of this imbalance is that the threshold voltage of one of the transistors M.sub.41 or M.sub.42, connected to the branch with the highest resistance, is reached more rapidly. In this example, where the transistors M.sub.41, M.sub.42, are of the PMOS type and connected to the supply voltage VDD, this results in setting at VDD the node N1 or N2 of the branch connected to the HRS resistance, and the other node N2 or N1 of the other branch has a potential substantially equal to that of the bit line connected to this other branch.
[0129] The read amplifier has consequently “toggled” into a state that self-services so long as the read nodes N.sub.1, N.sub.2 are not reset. The respective potential of the read nodes N.sub.1, N.sub.2 is frozen and it is said that the sense amplifier 44.sub.0 is in a latch state.
[0130] In the particular example of embodiment illustrated in
[0131] The sense amplifier 44.sub.0 is associated with a reset stage 46.sub.0 of the read nodes N.sub.1, N.sub.2. This stage 46.sub.0 is equipped with at least one first switch element, in this example in the form of two reset transistors Mrz.sub.1, Mrz.sub.2 also called reset-to-zero transistors, particularly provided to make it possible to reset the read nodes, at the same potential and thus remove the sense amplifier 44.sub.0 from its latched state.
[0132] Each reset transistor Mrz.sub.1, Mrz.sub.2 thus makes it possible alternately, depending on the OFF or conducting state wherein it may be placed by way of a first control signal Cmd.sub.1 common and applied on the gate of two transistors Mrz.sub.1, Mrz.sub.2, to isolate or connect the nodes N.sub.1, N.sub.2 from/to the second supply line 45, in this particular example of embodiment a supply line set at a “high” potential, here corresponding to the supply potential VDD.
[0133] The state of this first control signal Cmd.sub.1 also has to be modified during a read operation carried out on the cell C.sub.i0.
[0134] The read circuit 40.sub.0 has here the specific feature of including a so-called “isolation” stage 42.sub.0 between the pair of bit lines BL.sub.0, BL.sub.1 and the stage 44.sub.0 forming the latch sense amplifier.
[0135] The isolation stage 42.sub.0 includes in this example two isolation transistors Mi.sub.1, Mi.sub.2, a first isolation transistor Mi.sub.1 being disposed between the sense amplifier 44.sub.0 and a first bit line BL.sub.0, a second isolation transistor Mi.sub.2 being disposed between the sense amplifier 44.sub.0 and a second bit line BL.sub.1.
[0136] The isolation transistors Mi.sub.1, Mi.sub.2 thus make it possible alternately, depending on their OFF or conducting state, controlled by a second control signal Cmd.sub.2 applied on their gate, to isolate the bit lines BL.sub.0, BL.sub.1 from the sense amplifier 44.sub.0 or to connect the bit lines BL.sub.0, BL.sub.1 to the sense amplifier 44.sub.0. The state of the second control signal Cmd.sub.2 is itself controlled by a circuit for controlling the read circuit and has to be modified during a read operation carried out on the cell C.sub.i0, in order to modify the conduction state of the isolation transistors Mi.sub.1, Mi.sub.2 during this read operation. The isolation transistors thus have here a function of coupling transistors for alternately coupling and uncoupling the circuit for reading elements located upstream.
[0137] An example of read operation performed with the aid of such a read circuit 40.sub.0 will now be given in connection with
[0138] The read operation is performed in this example in two phases and typically includes a waiting phase and a comparison phase.
[0139] During a “waiting phase”, (
[0140] During this waiting phase, the selection transistors Ms.sub.1, Ms.sub.2 are enabled by way of a word line WL.sub.i placed for example in a state ‘1’, in particular when they are of the NMOS type.
[0141] The control signal Cmd.sub.2 of the first isolation transistor Mi.sub.i and of the second isolation transistor Mi.sub.2, is placed in a state, in this example where the isolation transistors Mi.sub.1, Mi.sub.2 are of the NMOS type corresponding to a logic level ‘0’, so as to render OFF the transistors Mi.sub.1, Mi.sub.2. The bit lines BL.sub.0, BL.sub.1 are thus disconnected and isolated from the sense amplifier 44.sub.0. During this step, a discharge of the bit lines BL.sub.0, BL.sub.1 is thus prevented that are then connected to the same first potential, here equal to the ground GND in other words to a potential equal or substantially equal to that of the source line SL. In this example of embodiment rather than a specific pre-charge circuit, it is the source line SL that makes it possible to impose the first potential GND on the bit lines BL.sub.0, BL.sub.1.
[0142] It will be noted that by convention, pre-charge of a bit line refers to the operation consisting of maintaining or bringing a bit line to a potential substantially equal to that present on the first supply line, in other words that present on the source line. Subsequently, discharge of a bit line refers to an operation consisting of moving its potential away from its pre-charge level, by moving it closer to the potential present on the second supply line. Thus in the examples of
[0143] After the waiting phase, during a so-called “comparison” phase (
[0144] During this comparison phase, the selection transistors Ms.sub.1, Ms.sub.2 are always enabled by way of a word line WL.sub.i that is in the state corresponding here to a ‘1’ logic. During the comparison phase, the control signal Cmd.sub.2 of the first isolation transistor Mi.sub.1 and of the second isolation transistor Mi.sub.2, is for its part placed in a state different from that of the waiting phase. In this example, where the isolation transistors Mi.sub.1, Mi.sub.2 are of the NMOS type, a signal Cmd.sub.2=‘1’ is applied, so as to render conducting the isolation transistors Mi.sub.1, Mi.sub.2. The bit lines BL.sub.0, BL.sub.1 are thus connected to the sense amplifier 44.sub.0. When the isolation transistors Mi.sub.1, Mi.sub.2 are placed in conduction, each branch of the amplifier 440 is connected to a resistance of the cell C.sub.i0. A current is established in each of the branches until the amplifier latches. The latching being relatively rapid, the bit lines BL.sub.0, BL.sub.1 discharge very little and their potential remains close to the ground GND in this example.
[0145] As opposed to an operation of devices of the aforementioned prior art for which the bit lines undergo an almost integral discharge during the comparison operation here a full-scale discharge-charge of the bit lines between the ground GND and the supply voltage Vdd is prevented. Such an operating mode thus makes it possible to reduce the amplitude of the charge-discharge of the bit lines BL.sub.0, BL.sub.1 and thus improve the dynamic consumption of the reading, this consumption then being mainly due to that of the sense amplifier. This advantage is related to the fact that the pre-charge level of the bit lines corresponds to the voltage level applied to the resistive memories of the memory cells on the side opposite to the bit lines. In other words, prior to a comparison operation, the resistive memories, once the word line (WL.sub.i) has been enabled, see at their terminals a relatively low voltage, which may for example correspond to a few percent, 5 to 10%, of the voltage between the two supply lines, gnd and Vdd. This voltage at the terminals of the resistive memories increases very slightly the time that the amplifier latches to stabilise and reduce once the amplifier has been latched.
[0146] It is noted, that in the example of operation that has just been described, the Cmd.sub.1, Cmd.sub.2 are modified concomitantly. In other words, the reset of the amplifier 440 is interrupted at the moment where the branches of the amplifier are connected to the bit lines. In practice, this operating mode may induce possible read errors if the bit lines have a high capacitance because it may transpire that the amplifier latches on discharge currents of the respective capacitances of the bit lines, and not on the resistance levels of the resistive memories. A solution to this problem is given infra. With an operating mode as described above, the polarisation of the word line WL.sub.i between the waiting phase and the comparison phase is not modified. The state of a signal SWL applied on the word line WL.sub.i is only modified, and for example placed at a state ‘0’, after completion of the comparison phase and of the read operation. The isolation transistors Mi.sub.1, Mi.sub.2 described above are in this example different from other transistors called “separation” transistors, and that can be used to isolate the read circuit 40.sub.0 during write operations carried out in the array M.sub.1.
[0147] Thus, in order to protect the transistors of the read circuit 40.sub.0 during write operations, it is possible to provide at the base of the column, as in the example of embodiment illustrated in
[0148] The separation transistors M.sub.61, M.sub.62 are enabled, in other words rendered “conducting” during read operations whereas during write operations, the separation transistors M.sub.61, M.sub.62 are rendered OFF in order to isolate the read circuit of the cell wherein it is written.
[0149] Typically, the separation transistors M.sub.61, M.sub.62 in the same way as the selection transistors M.sub.s1, M.sub.s2 are provided with a gate dielectric thicker than that of the transistors of the read circuit 40.sub.0, in order to be able to be subjected to significant voltage levels whereas the transistors of the sense amplifier and the isolation transistors Mi.sub.1, Mi.sub.2, are provided with a thinner gate dielectric. In practice, this makes it possible, during the reading, to prevent a loss of information in the memory cells due to possible undesired writing and further makes it possible to limit the consumption.
[0150] During a read operation, the Enable.sub.read read validation signal is constantly maintained in the same state, for example Enable.sub.read=‘1’ when the separation transistors M.sub.61, M.sub.62 are as in
[0151] According to one variant not shown, the respective functions of isolation, by the transistors Mi.sub.1, Mi.sub.2, and of separation, by the transistors M.sub.61, M.sub.62, may be performed by the same pair of transistors. Thus, it would be possible for example to only keep the transistors M.sub.61, M.sub.62 and render them conducting when in read mode (as opposed to other types of operations on the array, such as the writing, the erasure of memory cells) and when, still in a read mode, it is desired to remove the isolation between the memory cell array and the differential sense amplifier 44.sub.0. It is particularly desired to remove the isolation function when a comparison is performed and in most embodiments described during the partial discharge phase prior to the comparison phase as is described in more details in the following examples.
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[0153] The high capacitance of the bit lines BL.sub.0, BL.sub.1 may pose a problem, in particular when the control signal Cmd.sub.2 of the isolation transistors Mi.sub.1, Mi.sub.2 is modified and the bit lines BL.sub.0, BL.sub.1 are connected to the sense amplifier 44.sub.0. From this connection may indeed optionally and in some cases result a discharge of the bit lines BL.sub.0, BL.sub.1 towards the sense amplifier 44.sub.0 which is not systematically correlated with the respective states of the resistive elements of the cell that it is desired to read and that may tend to toggle the output of the sense amplifier 44.sub.0 without this output being representative of the binary data stored in memory of the read data.
[0154] To overcome this problem and improve the read reliability, a solution may consist of implementing different sequences between the sequence of the control signal Cmd.sub.2 of the isolation transistors Mi.sub.1, Mi.sub.2 and the sequence of the control signal Cmd.sub.1 of the reset transistors Mrz.sub.1, Mrz.sub.2.
[0155] A read operation in accordance with this variant is illustrated in
[0156] Likewise, to make it possible to reset the sense amplifier 44.sub.0 the read nodes N.sub.1, N.sub.2 are set at the same potential here corresponding to the ground GND. Thus, in the example of embodiment illustrated in
[0157] Subsequently, a two-phase cycle is carried out.
[0158] According to a so-called “partial discharge” phase (illustrated in
[0159] In the example of embodiment illustrated in
[0160] Then, after a relatively short time, when the parasitic discharge of the bit lines has been evacuated and the currents are finally function of the values of the resistive elements, the reset transistors Mrz.sub.1, Mrz.sub.2 are disabled to thus make it possible to switch the sense amplifier in accordance with the binary data contained in the 2T-2R cell selected.
[0161] It will be noted that the aim of this operation of partially discharging bit lines is to slightly discharge the output bit lines so as to make it possible to establish a minimum voltage at the terminals of the resistive elements for inducing a flow of currents in the resistances that become significant in relation to the self-discharge current of the bit lines and furthermore that make it possible to obtain relative currents in the resistive memories sufficiently different from one another to be able to pass to the following comparison step.
[0162] Thus, after the partial discharge phase the so-called “comparison” phase (illustrated in
[0163] The adjustment of the duration of the discharge phase and consequently the delay between enabling the isolation transistors and disabling the reset transistors is carried out in such a way as to optimise the energy efficiency of the read operation, particularly in such a way as to limit the partial discharge of the bit lines as a minimum.
[0164] There again, as opposed to a conventional operation, a discharge of the bit lines BL.sub.0, BL.sub.1 from the supply voltage of VDD to the Ground GND is not carried out. A gain in consumption is thus obtained and the read dynamic consumption is reduced.
[0165] In
[0166] The curves C.sub.cmd1, C.sub.cmd2 are representative respectively of the first control signal cmd1 of the reset transistors Mrz.sub.1, Mrz.sub.2, and of the first control signal cmd2 of the isolation transistors Mi.sub.1, Mi.sub.2, whereas the curves Cv.sub.BL0, Cv.sub.BL1 are used to illustrate respectively the voltage on the first bit line BL.sub.0, in this example connected to a resistive element at the HRS level, the voltage on the second bit line BL.sub.1, in this example connected to a resistive element at the LRS level. The curves C.sub.IBL0, C.sub.IBL1 are used to illustrate respectively the evolution of the current on the first bit line BL.sub.0, and that of the current on the second bit line BL.sub.1, whereas the curves CoutA, CoutB give the evolution of the respective potentials of the nodes N.sub.2, N.sub.1.
[0167] It may be observed that with such a delay, a partial discharge of the bit lines BL in the order of 80 mV is performed, for a full-scale discharge of 0.9 V i.e. less than 10% of the supply voltage of the circuit.
[0168] During simulation with the aid of the Monte Carlo tool, a total consumption is obtained (by taking into account the circuits for controlling bit lines and word lines WL, the charging of word lines WL, the generation of the delay) per bit/read in the order of 30 fJ. This is comparable with a SRAM of the same technology and better than the prior art of the abovementioned resistive memory-based memory circuits, by being able to divide by two, or even by three the order of magnitude of the read consumption.
[0169] In the example of embodiment illustrated in
[0170] The adjustable delay generator 91 may be formed for example of a succession of inverters with which a multiplexer is associated. The adjustment of the delay may be carried out by way of a configuration word, the delay being, in this case, a delay chosen from a set of delays predetermined depending on the values of the bits of the configuration word.
[0171] The control signals Cmd.sub.1, Cmd.sub.2 are propagated from one read circuit 40.sub.0 to the other 40.sub.1 of the plurality of read circuits 40.sub.0, . . . , 40.sub.(m/2)−1 located at the base of the columns and each coupled to a pair of bit lines BL.sub.0, BL.sub.1 (resp. BL.sub.2, BL.sub.3 . . . ), according to a direction of propagation typically as shown schematically by an arrow F.sub.1 in
[0172] According to one alternative embodiment, during a read operation, it is possible to trigger the end of the partial discharge phase depending on a comparison between a voltage level measured on at least one bit line, in particular on one or other of the bit lines BL.sub.0, BL.sub.1 or each of the bit lines BL.sub.0, BL.sub.1 coupled to a cell that it is desired to read and a predetermined reference voltage.
[0173] In the particular example of embodiment illustrated in
[0174] As seen on the simulation curves C.sub.VBL0, C.sub.VBL1 above, the voltages of the bit lines BL.sub.0, BL.sub.1 drop as the partial discharge of their capacitance progresses. This drop corresponds to a moment with the formation of a current through the resistive elements 1, 2. In the example illustrated, the lower the bit line voltage VBL is the higher the current passing through in the sense amplifier 44.sub.0 is representative of the resistance values of the ReRAM and therefore the more reliable the read operation is.
[0175] It is triggered in this example the change of state of the first control signal Cmd.sub.1 for locking the reset transistors by using the output signal of a comparator 101 an input of which receives the voltage V.sub.BL0 of a bit line BL.sub.0. The reference voltage Vref that is used as reference may be determined by taking into account parameters of technological variability, of thermal effects, of mismatches between performances of the components.
[0176] In another example of embodiment illustrated in
[0177] It is then triggered the change of state of the control signal Cmd.sub.1 of the reset stage this time by using a first comparator 101 to compare an input receiving the voltage V.sub.BL0 of a first bit line BL.sub.0 and the reference voltage V.sub.ref, and a second comparator 112 to compare an input receiving the voltage V.sub.BL1 of the second bit line BL.sub.1 and the reference voltage V.sub.ref. The control signal Cmd.sub.1 of the reset stage may then be produced as output of a logic block, in this example a gate 115, performing an AND function between an output of the first comparator 101 and an output of the second comparator 112. The duration of the discharge phase is thus adjusted depending on the longest duration between two different discharge times.
[0178] Alternatively, in the particular example of embodiment illustrated in
[0179] As a variant of one or other of the examples of embodiment described above, a reset of the nodes N.sub.1, N.sub.2 of the sense amplifier 44.sub.0 can be carried out in a different way than that described above with the reset transistors Mrz.sub.1, Mrz.sub.2.
[0180] Thus, in the example of embodiment illustrated in
[0181] Thus, instead of resetting the sense amplifier 44.sub.0, by connecting or coupling its nodes N.sub.1, N.sub.2 to a supply line 45 connected to the ground or to a supply potential Vdd, it is possible to short-circuit these nodes N.sub.1, N.sub.2 to perform this reset.
[0182] The switch element 136 is thus configured to, depending on the state of the control signal Cmd.sub.1, interconnect the nodes N.sub.1, N.sub.2 of the sense amplifier, then disconnect from one another the nodes N.sub.1, N.sub.2 of the sense amplifier.
[0183] The switch element 136 may be produced in a plurality of ways depending on the technology used and on the type of transistors forming the sense amplifier. For example the switch element 136 may be produced by a CMOS transmission gate typically consisting of a NMOS transistor and of a PMOS connected in parallel. According to another example of embodiment, when the sense amplifier 44.sub.0 is as in
[0184] Alternatively, when the sense amplifier 44.sub.0 is, as in the example of embodiment illustrated in
[0185] With such a reset stage, a three-phase operation as described above may be kept. Such an operation is shown in
[0186] The sense amplifier 44.sub.0 is in this example connected to a supply line 45 connected to the ground GND and the isolation transistors Mi.sub.1, Mi.sub.2 are of the PMOS type.
[0187] A so-called “waiting” phase is firstly carried out (
[0188] At the same time, the first control signal Cmd.sub.1, in this example set at the state ‘1’, makes it possible to establish the short-circuit and thus interconnect the nodes N.sub.1, N.sub.2 of the sense amplifier 44.sub.0. During the waiting phase described here, it can be noted that in this example the transistors M.sub.141, M.sub.142, M.sub.143, M.sub.144 of the sense amplifier 44.sub.0 are in an uncertain state, which does not hinder the operation of the read operation strictly speaking and which mainly takes place in the following steps. Subsequently (
[0189] Finally (
[0190] Another alternative embodiment less performant than that described above in connection with
[0191] Thus, in the example illustrated in
[0192] After a read operation, the control signals Cmd.sub.1 and Cmd.sub.2 are typically returned to their initial state corresponding to the waiting phase, that is to say that the first control signal Cmd.sub.1 is placed in a state so as to enable (i.e. render conducting) the reset transistors whereas the second control signal Cmd.sub.2 is placed in a state so as to disable (i.e. render OFF) the isolation transistors.
[0193] By carrying out this operation, particularly the reset operation, the information read during this read operation is likely to be lost. To prevent this, the read circuit may be configured to wait for the memory device to take into account the read result, for example by only carrying out the return to waiting phase following a capture of information read by a flip-flop or another block of the memory, for example the input/output block of the memory or an internal processing/computation block of the memory.
[0194] One variant of the memory device may be provided particularly if it is desired to be able to anticipate a next reading and for this enable a word line other than that enabled to carry out a reading in progress. One example of embodiment is given in
[0195] In the example illustrated in
[0196] One alternative embodiment, illustrated in
[0197] Typically, the D flip-flop 163 is preceded by a Schmitt flip-flop 162 also called “Schmitt trigger” to make it possible to perform a formatting of the output signal and produce the interfacing with a logic portion.
[0198] According to a particular embodiment, it may be envisaged, at the end of the read operation, to help to recharge the bit lines BL0 and BL1 and thereby to make it possible to sequence the readings more rapidly, by injecting an additional current into the bit lines.
[0199] Thus, in the example of embodiment illustrated in
[0200] In this particular example of embodiment, these repolarisation transistors Mrep.sub.1, Mrep.sub.2 are not connected directly to the bit lines but here to the separation transistors M.sub.61, M.sub.62 typically having a gate dielectric thicker than that of the transistors of the read circuit in order to protect the latter. Such a configuration makes it possible to prevent having to produce repolarisation transistors with thick gates.
[0201] The enabling of repolarisation transistors Mrep.sub.1, Mrep.sub.2 is performed during the comparison phase, on the end of the comparison phase, with the aid of a repolarisation control signal S.sub.repol applied on their gate. This enabling is triggered some time after the change of state of the first control signal Cmd.sub.1 of the reset transistors Mrz.sub.1, Mrz.sub.2 stopping the reset. If an example of embodiment is taken such as described in relation to
[0202] A memory device in accordance with the invention is not necessarily limited to an arrangement of memory cells as described above in relation to
[0203] Thus, in order to particularly limit the consumption related to the discharge of the capacitance of the bit lines, an alternative arrangement may be implemented wherein the 2T-2R cell is “returned” in relation to the arrangement described above. Indeed, according to the resistive memory technology used, it is possible that the electrodes of a resistive memory are less capacitive than the sources of the selection transistors, inducing a lower total bit line capacitance.
[0204] In the example of embodiment illustrated in
[0205] A memory device in accordance with the invention may be further provided to perform logic operations, in particular IMC (In Memory Computing) or NMC (Near Memory Computing) memory operations.
[0206] Thus, an operation may be particularly carried out between a volatile binary data coming from an element external to the memory array and at least one non-volatile data stored in the RRAM memory. Such a functionality may be incorporated into the proposed read circuit.
[0207] In the example of embodiment illustrated in
[0208] When a simple read operation is carried out, the signals Cmd.sub.A, Cm.sub.B are identical and adopt one or other of the sequences described above of the control signal Cmd.sub.2. The signal Cmd.sub.C applied on the gate of the isolation transistors Mi.sub.3 and Mi.sub.4 may be in this case placed constantly in a state so as to lock the isolation transistors Mi.sub.3 and Mi.sub.4.
[0209] When a logic operation is carried out, the signals Cmd.sub.A, Cmd.sub.B, Cmd.sub.C may depend on the value of the volatile logic data Data.sub.VOL with which the operation is carried out. For example, if this volatile logic data Data.sub.VOL equals ‘1’, the isolation transistors Mi.sub.1, Mi.sub.2 are enabled (i.e. placed in a conducting state) by disabling (i.e. placing them in an OFF state) the isolation transistors Mi.sub.3, Mi.sub.4. In this case, if a volatile logic data ‘0’ is processed, the crossed pair Mi.sub.3, Mi.sub.4 is enabled, while disabling (i.e. placing them in an OFF state) the isolation transistors Mi.sub.1, Mi.sub.2.
[0210] To apply an XOR function, the drive signals Cmd.sub.A and Cmd.sub.B are provided as for a normal reading, so as to enable the isolation transistors Mi.sub.1, Mi.sub.2 whereas the isolation transistors Mi.sub.3, Mi.sub.4 are disabled when the volatile data Data.sub.VOL is Data.sub.VOL=‘0’. When Data.sub.VOL=‘1’, the signal Cmd.sub.C is provided in such a way as to enable the crossed pair Mi.sub.3, Mi.sub.4, whereas the isolation transistors Mi.sub.1, Mi.sub.2 are disabled.
[0211] The device is not limited to the implementation of an XOR or NXOR function and may also make it possible to implement other logic functions, in particular an OR function and/or an AND function as well as their complementaries.
[0212] For the operations of the AND or OR type, depending on the value of the volatile data Data.sub.VOL, the result is either directly equal to the value of the non-volatile data Data.sub.NON-VOL, or independent of the non-volatile data Data.sub.NON_VOL.
[0213] Consequently, a suitable driving of the signals Cmd.sub.A and Cmd.sub.B may make it possible to bias the reading in the cases where the result is independent of Data.sub.NON_VOL.
[0214] With a device as illustrated in
[0215] If it is desired to only perform operations of the OR and type (or complementaries), it is therefore possible alternatively to provide a read circuit as in
[0216] In one case, for example, where the implementation of OR and functions is provided, with a device wherein a logic ‘1’ stored in an elementary cell is coded by forcing the first resistive element 1 to LRS and the second resistive element 2 to HRS: when an OR logic function is implemented only the first isolation transistor Mi.sub.1 is enabled by way of the signal Cmd.sub.A.
[0217] In this case, to carry out an AND function only the second isolation transistor Mi.sub.2 is enabled by way of the signal Cmd.sub.B.
[0218] Thus, at the generation of signals Cmd.sub.A, Cmd.sub.B, Cmd.sub.C, these signals depend on whether the operation carried out is a simple read operation or on the chosen logic operation, as well as on the value of a volatile binary data Data.sub.VOL that is used as an operand.
[0219] With a device as illustrated for example in
[0224] The control circuit that produces the drive signals Cmd.sub.A, Cmd.sub.B, Cmd.sub.C may be provided with a digital control block 210, as illustrated in
[0225] To code four different operating modes, it is possible to use two input bits: RegMODE<1>, and RegMODE<0> of the digital block 210, as in the table given below.
TABLE-US-00001 Mode REG.sub.MODE<1> REG.sub.MODE<0> Simple read 0 0 XOR 0 1 AND 1 0 OR 1 1
[0226] The drive signals Cmd.sub.A, Cmd.sub.B, Cmd.sub.C may be produced from the control signal Cmd.sub.2 the evolution of which may be as described above. It should be reminded that in the case of a simple reading, we typically have the drive signals Cmd.sub.A and Cmd.sub.B identical to the control signal Cmd.sub.2.
[0227] The way of encoding a data in a cell, the output of the sense amplifier 44.sub.0 observed when a reading or an operation is carried out from that with OutB connected to the first node N.sub.1 and that with OutA connected to the second node N.sub.2, the way of selecting a given logic operation are the choice of the Person Skilled in the Art and may be different from those described above.
[0228] A control block 210 for producing the drive signals Cmd.sub.A, Cmd.sub.B, Cmd.sub.C of the isolation transistors Mi.sub.1, Mi.sub.2 may be associated with means as described above to make it possible to produce the control signal Cmd.sub.1 of the reset transistors Mrz.sub.1, Mrz.sub.2.
[0229] Thus, in the example of embodiment of
[0230] In the alternative embodiment of
[0231] An example of truth table of the selection block 210 is given below, with various states of signals Cmd.sub.A, Cmd.sub.B, Cmd.sub.C to make it possible to drive respectively the gate of the first isolation transistor Mi.sub.1, the gate of the second isolation transistor Mi.sub.2, and the respective gates of the additional pair of isolation transistors Mi.sub.3, Mi.sub.4.
TABLE-US-00002 Read Mode REG.sub.MODE<1> REG.sub.MODE<0> Data.sub.VOL Cmd.sub.A Cmd.sub.C Cmd.sub.B type Simple 0 0 0 ‘1’ ‘0’ ‘1’ Normal read 1 ‘1’ ‘0’ ‘1’ Normal XOR 0 1 0 ‘1’ ‘0’ ‘1’ Normal 1 ‘0’ ‘1’ ‘0’ Reversed AND 1 0 0 ‘0’ ‘0’ ‘1’ Force ‘0’ 1 ‘1’ ‘0’ ‘1’ Normal OR 1 1 0 ‘1’ ‘0’ ‘1’ Normal 1 ‘1’ ‘0’ ‘0’ Force ‘1’
[0232] A selection block 210 responding to such a truth table may be implemented for example with the aid of an arrangement of logic gates 251, 252, 253, 254, 255, 256, 257, such as given by way of example in
[0233] A memory device as described above may be applied particularly in the implementation of neuron network systems for which it is desired to limit as far as possible the consumption and wherein the read memory accesses are numerous and non-stop.
[0234] In such systems, the RRAM memory cells may make it possible to store a synaptic weight. In this case, the memory may be read by carrying out a read access on a complete row of cells, in particular on a line (horizontal row) of cells.
[0235] As a variant of one or other of the examples of embodiments described above, it is possible, by replacing cells of the 2T-2R type, to provide an array with cells of the so-called “1T-1R” type wherein the stored value is kept this time with the aid of a single resistive element of variable resistivity between two LRS and HRS resistivity levels, this resistive element having an electrode coupled to a selection transistor. In such elementary cells, the selection transistor is also controlled by a signal SWL conveyed by a word line WL.sub.i thus making it possible, alternately to couple or uncouple the resistive element to/from a bit line BLj. The bit line BLj+1 is, as illustrated in the example of embodiment of
[0236] Around the periphery of the array, and in particular at the base of each column, a read circuit 40.sub.j is then provided to make it possible to translate into a binary data the resistive state of the resistive element of a memory cell. The read circuit 40.sub.j of a column of cells may have a structure as described above but here is associated with a single bit line BL.sub.i and with a reference line 260 provided with a resistance R.sub.ref in order to be able to determine a current difference between the current circulating on the bit line and a reference current circulating on the reference line 260 and to thus evaluate whether the resistive element stores a value corresponding to a HRS state or another value corresponding to a LRS state.
[0237] It will be noted that the reference line is in this example constructed and polarised in a similar manner to a 1T1R memory cell when the memory cell is selected for reading. Thus, the reference resistance Rref is in this example connected to an identical supply line by sharing for example the same source line. It is possible for example to provide a reference resistance Rref per column, positioned opposite or close to the amplifier 40j (therefore right at the top or right at the bottom of the array) and connected to the amplifier 40j by a reference bit line.
[0238] The read operations performed with this reference line are a differential reading that may be performed in a similar manner to the examples of operations described above. The only difference resides in the fact that the reference resistance Rref will have a resistivity value that will not be the HRS or LRS value corresponding to the one that may be taken by a memory cell, but an intermediate value between these two values. Thus, this embodiment with “single” memory cells of the 1T1R type may in practice be used when the difference between the HRS and LRS values is sufficient. In other words, it is necessary to make sure that the variation range of possible HRS resistance values and that of possible LRS resistance values (due to technological dispersions, to the temperature) are not only not overlapping, but sufficiently spaced apart to be able to envisage using a reference resistance of which the variation range of values must be situated between the two other HRS and LRS ranges. If reference is made to an arrangement with isolation transistors as described above, it may thus be envisaged to couple the first bit line BL.sub.i−1 to the first isolation transistor Mi.sub.1 whereas the reference line 260 is coupled to the second isolation transistor Mi.sub.2. Likewise, the person skilled in the art will know how to adapt all of the embodiments of a read circuit presented with 2T2R memory cells to the use of a single bit line connected to a selected 1T1R memory cell and of a reference line 260 with the resistance Rref.
[0239] Advantageously, although the 1T1R memory cells may be programmed with more than two resistance values, for example, 3, 4, or even more, then this example of embodiment with a reference line and a differential reading makes it possible to advantageously read multivalued memory cells. To this end, the reference resistance R.sub.ref, may be a variable resistance. It is then possible to determine the stored value by way of successive readings. The value of the resistance Rref may thus be modified from one read operation to the other in order to be able to determine a plurality of current differences between the current circulating on the bit line and a reference current circulating on the reference line 260 and find through successive tests which is the value stored in the resistive cell.
[0240] According to one alternative embodiment of the reference line, it comprises a current source produced other than with a reference resistance connected to the source line SL. Thus, it is possible to use for example a current mirror the value of which may be changed easily according to known production techniques.
[0241] In one or other of the examples that have been described above, an isolation stage is provided, in particular equipped with two isolation transistors Mi.sub.1, Mi.sub.2 to alternately couple and uncouple the bit line(s) to/from the sense amplifier 44.sub.0 in order, during a waiting phase between two reads, to be able to limit the static consumption, and furthermore to be able to anticipate the reset operation if necessary.
[0242] One alternative embodiment without isolation transistor is this time illustrated in
[0243] In this example of embodiment, the sense amplifier 44.sub.0 is connected to a high supply line 45 i.e. set at VDD, whereas the cells are connected to the source line SL this time forming a low supply line i.e. connected to the ground GND.
[0244] A read operation in a plurality of phases and in accordance with this variant of arrangement is illustrated in
[0245] The control signals of the various operating phases are this time the control signal Cmd.sub.1 applied on the gate of the switch transistor 146 and the signal SWL from the word line WL and applied on the gate of the selection transistor(s) Ms.sub.1, Ms.sub.2. According to a so-called “partial discharge” phase (illustrated in
[0246] The bit lines BL.sub.0, BL.sub.1 are coupled, by means of resistive elements, to the source line SL here connected to the ground. During this partial discharge phase, the bit lines BL.sub.0, BL.sub.1 see their potentials slightly increase progressively, but the read nodes N.sub.1 and N.sub.2 are maintained connected to one another. A reset is then carried out in order to avoid switching the sense amplifier 44.sub.0 due to the partial discharge currents of the bit lines, as explained above.
[0247] According to a so-called “comparison” phase (illustrated in
[0248] When the sense amplifier 44.sub.0 has toggled and it is in a latched state, it has a state of high impedance at the bit lines BL.sub.0, BL.sub.1 that are consequently returned to the ground by means of transient currents through the memory cell, low currents insofar as the bit lines are not very far away from the ground potential during the partial discharge step. Once the potential of the bit lines corresponds to that of the ground, there is almost no more current that circulates neither in the memory cell, nor in the amplifier. Thus, it is possible to desire to maintain this almost-zero consumption state until a next read operation. This state corresponds to a waiting state between two successive readings.
[0249] Thus, the device is subsequently placed in a so-called “transition” phase (
[0250] When another read operation is carried out on a new cell of another line, another word line is then enabled (control signal SWL=‘1’) and this makes it possible to couple the new cell and consequently the bit lines to the source line SL making it possible to find a waiting state similar to that shown in
[0251] The various waiting (with or without transition phase), partial discharge, comparison phases, likely to be implemented with a read circuit as described above in relation to
[0252] In this figure the evolution curve CSWL gives the evolution of the signal SWL applied on the word line and for alternately disabling the selection transistors during the transition phase then enabling the selection transistors during the waiting, discharge and comparison phases. It will be noted that in the interest of simplification, in this figure and that presented previously, a single signal CSWL is shown for potentially a plurality of word lines successively enabled.
[0253] The curve C.sub.cmd1, is representative of the control signal Cmd.sub.1 of the reset switch, alternately for uncoupling from one another the read nodes N.sub.1, N.sub.2 during the phase of transition then of waiting, then coupling the read nodes N.sub.1, N.sub.2 during the partial discharge phase and uncoupling them again during the comparison phase. The curves Cv.sub.BL0, Cv.sub.BL1 are used to illustrate respectively a voltage on the first bit line BL.sub.0, a voltage on the second bit line BL.sub.1, whereas the curves CoutA, CoutB give the evolution of the respective potentials of the nodes N.sub.2, N.sub.1.
[0254] It is observed that the comparison phase consists of a very short toggling phase during which the outputs of the amplifier toggle on one side or the other depending on the resistivity differences, then of a longer phase for recharging the bit lines. This recharge phase in fact resembles a waiting phase before a new partial discharge operation. Thus, generally “waiting phase” refers to any phase during which the bit lines no longer convey significant current between the memory cells and the amplifier 44.sub.0, as opposed to that occurring during a partial discharge phase and the start of the comparison until the toggling of the amplifier. Such a waiting phase may include a so-called transition phase in the case where the following reading is performed on another line. In the case where isolation transistors are provided, it is possible during a waiting phase to perform an operation for resetting the amplifier 440. The choice of whether or not to perform a reset operation during a waiting phase among other things depends on the type of reset circuit chosen, on the presence or not of an element of the flip-flop type (D or RS or other).
[0255] The curves of
[0256] It is possible to sequence read operations strictly speaking comprising a partial discharge phase with reset, then a comparison phase having a minimum duration ensuring the toggling of the amplifier regardless of the dispersions of the resistivity values of the memory cells. The phase for recharging line bits at the end of the comparison phase may be relatively short and it is not essential to achieve the complete recharging of bit lines before triggering a new pre-discharge phase for a new reading. The use of repolarisation transistors for performing an active polarisation of bit lines BL.sub.0, BL.sub.1 has been described above in connection with FIG. 17. It is also possible to provide such transistors with a device as described above in relation to
[0257] Thus, in
[0258] In this particular example of embodiment, the enabling of the repolarisation transistors M′rep.sub.1, M′rep.sub.2 is performed during the transition phase with the aid of a repolarisation control signal S.sub.repol applied on their gate to couple the bit lines to the source line and thus connect them to the ground GND. The repolarisation transistors M′rep.sub.1, M′rep.sub.2 may also be enabled in a second stage of the comparison phase, after a first stage reserved for performing the toggling of the amplifier. Thus, for example, it is possible to provide an end of toggling sense system for enabling the repolarisation transistors to accelerate the recharging of the bit lines to the voltage level of the source line, in order for example to be able to sequence more rapidly a new read cycle with a new phase of partial discharge and of comparison. Likewise, the repolarisation transistors are enabled during a transition phase and make it possible to maintain a supply of the latch amplifier during a transition phase as described above. By supplying the latch amplifier it is ensured here to maintain the bit lines at the potential of the source line SL, here at the ground. Furthermore, during this transition phase, all or part of the phase for recharging the bit lines may be performed thanks to the repolarisation transistors. This also offers the possibility of implementing a waiting phase that does not need the enabling of a word line WL. According to a variant not shown, it is also possible to provide a set of additional transistors to perform the partial discharge phase of the bit lines other than through the separation transistors and the branches of the amplifier, by providing such additional transistors connecting the bit lines to the source line SL.
[0259] Thus generally, the partial discharge phase consists of partially discharging the bit lines by connecting the latter to the source line. Advantageously, it is used for this, the transistors already existing for other functions, such as the transistors of the branches of the amplifier, or the transistors used for the reset phase. However, it is possible to use transistors other than these.
[0260] A ReRAM memory device as described above may also be integrated into onboard systems of the Internet of Things (IoT) type or of the Cyber-Physical System (CPS) type.