ANALOG-TO-DIGITAL CONVERTING CIRCUIT RECEIVING REFERENCE VOLTAGE FROM ALTERNATIVELY SWITCHED REFERENCE VOLTAGE GENERATORS AND REFERENCE VOLTAGE CAPACITORS AND OPERATING METHOD THEREOF

Abstract

An analog-to-digital converting circuit for converting an analog signal into a digital signal includes a plurality of reference voltage generators each generating a reference voltage, a plurality of reference voltage decoupling capacitors respectively corresponding to the reference voltage generators, and an analog-to-digital converter generating a comparison voltage based on the reference voltage and generating the digital signal corresponding to the analog signal based on a result of comparing the comparison voltage with the analog signal. At least one different combination of the reference voltage generators and the reference voltage decoupling capacitors is connected to the analog-to-digital converter in each of a plurality of conversion periods.

Claims

1. An analog-to-digital converting circuit for converting an analog signal into a digital signal, the analog-to-digital converting circuit comprising: a plurality of reference voltage generators each configured to generate a reference voltage; an analog-to-digital converter configured to generate a comparison voltage based on the reference voltage and the analog signal, and generate the digital signal corresponding to the analog signal based on a result of comparing the comparison voltage with a common voltage; and a plurality of decoupling capacitors connected to the plurality of reference voltage generators, respectively, wherein at least one of the plurality of decoupling capacitors is connected to the analog-to-digital converter in each of a plurality of time periods.

2. (canceled)

3. The analog-to-digital converting circuit of claim 1, wherein each of the plurality of reference voltage generators comprises a low-dropout regulator (LDO).

4. The analog-to-digital converting circuit of claim 1, wherein the analog-to-digital converter comprises: a capacitor array including a plurality of comparison voltage capacitors; a comparator configured to compare the comparison voltage with the common voltage; and a switch array including a plurality of switches respectively corresponding to the plurality of comparison voltage capacitors, the plurality of switches configured to be turned on or off in correspondence to respective bits included in the digital signal.

5. The analog-to-digital converting circuit of claim 4, wherein the turning on or off generates different comparison voltages for the respective bits.

6. The analog-to-digital converting circuit of claim 1, wherein, when the at least one of the plurality of decoupling capacitors is connected to the analog-to-digital converter, a peak current is provided to the analog-to-digital converter.

7. The analog-to-digital converting circuit of claim 6, wherein the comparison voltage is generated based on charges provided from the at least one of the plurality of decoupling capacitors.

8. The analog-to-digital converting circuit of claim 7, wherein the plurality of decoupling capacitors comprises: a first decoupling capacitor configured to provide charges to the analog-to-digital converter in a first conversion period; and a second decoupling capacitor configured to provide charges to the analog-to-digital converter in a second conversion period, and wherein the second conversion period is a different time period from the first conversion period.

9. The analog-to-digital converting circuit of claim 8, wherein the plurality of time periods includes: a sampling period during which the analog signal is sampled; and a reset period during which the comparison voltage is reset, and wherein the analog-to-digital converter is configured to receive the charges from the first decoupling capacitor in the reset period and the charges from the second decoupling capacitor in the sampling period.

10. The analog-to-digital converting circuit of claim 8, wherein a first number of bits, starting from a most significant bit (MSB), are converted during the first conversion period, a second number of bits are converted during the second conversion period after the first conversion period.

11. The analog-to-digital converting circuit of claim 10, wherein a capacitance of the first decoupling capacitor is different from a capacitance of the second decoupling capacitor.

12. The analog-to-digital converting circuit of claim 10, wherein a range of fluctuation of the reference voltage generated in the first conversion period is greater than a range of fluctuation of the reference voltage generated in the second conversion period.

13. An analog-to-digital converting circuit for converting an analog signal into a digital signal, the analog-to-digital converting circuit comprising: a plurality of reference voltage generation circuits including a first reference voltage generation circuit and a second reference voltage generation circuit; an analog-to-digital converter configured to generate a digital signal corresponding to an analog signal based on a reference voltage provided from the plurality of reference voltage generation circuits; and a plurality of switches respectively configured to control connections between the analog-to-digital converter and the plurality of reference voltage generation circuits, wherein one of the plurality of switches is configured to be activated and connect one of the plurality of reference voltage generation circuits to the analog-to-digital converter during one of a plurality of time periods.

14. (canceled)

15. The analog-to-digital converting circuit of claim 13, wherein the analog-to-digital converter comprises: a capacitor array including a plurality of comparison voltage capacitors; a comparator configured to compare a comparison voltage with a common voltage; and a switch array including a plurality of switches respectively corresponding to the plurality of comparison voltage capacitors, the plurality of switches configured to be turned on or off based on respective bits included in the digital signal.

16. The analog-to-digital converting circuit of claim 13, wherein, when at least one of the plurality of reference voltage generation circuits is connected to the analog-to-digital converter, a peak current is provided to the analog-to-digital converter.

17. The analog-to-digital converting circuit of claim 16, wherein each of the plurality of reference voltage generation circuits comprises a decoupling capacitor configured to provide the peak current to the analog-to-digital converter.

18. The analog-to-digital converting circuit of claim 17, wherein the first reference voltage generation circuit comprises a first decoupling capacitor configured to provide charges to the analog-to-digital converter in a first conversion period, and the second reference voltage generation circuit comprises a second decoupling capacitor configured to provide charges to the analog-to-digital converter in a second conversion period, wherein a comparison voltage is generated based on charges provided from the plurality of reference voltage generation circuits, and wherein the second conversion period is a different time period from the first conversion period.

19. (canceled)

20. The analog-to-digital converting circuit of claim 18, wherein a first number of bits, starting from a most significant bit (MSB), are converted during the first conversion period, and a second number of bits are converted during the second conversion period after the first conversion period.

21. The analog-to-digital converting circuit of claim 20, wherein a capacitance of the first decoupling capacitor is different from a capacitance of the second decoupling capacitor.

22. The analog-to-digital converting circuit of claim 21, wherein a range of fluctuation of the reference voltage generated in the first conversion period is greater than a range of fluctuation of the reference voltage generated in the second conversion period.

23. A method of converting an analog signal to a digital signal, the method comprising: generating, by a first reference voltage generation circuit, a first reference voltage during a first time period; providing the first reference voltage to an analog-to-digital converter; generating a comparison voltage based on the first reference voltage and the analog signal; generating, by a second reference voltage generation circuit, a second reference voltage during a second time period different from the first time period; providing the second reference voltage to the analog-to-digital converter; generating the comparison voltage based on the second reference voltage and the analog signal; and performing an analog-to-digital conversion operation based on the comparison voltage and a common voltage in at least one of the first time period and the second time period.

24.-29. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

[0010] FIG. 1 is a schematic block diagram illustrating a plurality of elements included in an analog-to-digital converting circuit, according to some example embodiments;

[0011] FIG. 2 is a schematic block diagram of an analog-to-digital converting circuit according to a comparative embodiment;

[0012] FIG. 3 is a graph of a comparison voltage generated according to a comparative embodiment, a current provided by a reference voltage generator, a peak current consumed by an analog-to-digital converting circuit, and a reference voltage;

[0013] FIG. 4 is a graph showing a change in the reference voltage, which is generated according to the comparative embodiment of FIG. 3, with respect to a peak current;

[0014] FIG. 5 is a diagram of the configuration of an analog-to-digital converting circuit including a plurality of reference voltage generators, according to some example embodiments;

[0015] FIG. 6 is a circuit diagram of a reference voltage generator according to some example embodiments;

[0016] FIG. 7 is a block diagram of the configuration of an analog-to-digital converter (ADC) according to some example embodiments;

[0017] FIG. 8 is a circuit diagram illustrating a digital-to-analog converter (DAC) and a comparator of an ADC, according to some example embodiments;

[0018] FIG. 9 is a graph showing data of a digital signal generated by comparing a comparison voltage with the voltage level of an input signal;

[0019] FIG. 10 is a graph showing switch signals applied to a plurality of switches and a comparison current provided to an ADC, according to some example embodiments;

[0020] FIG. 11 is a graph showing a plurality of reference voltages generated by an analog-to-digital converting circuit and reference voltages applied to an ADC, according to some example embodiments;

[0021] FIG. 12 is a graph showing a comparison voltage and a comparison current, which are generated by an ADC, according to FIGS. 10 and 11;

[0022] FIG. 13 is a graph showing the results of simulating a signal-to-noise and distortion ratio (SNDR) of an ADC with respect to the capacitance of decoupling capacitors used in an example embodiment and a comparative embodiment;

[0023] FIG. 14 is a block diagram of a communication device according to some example embodiments;

[0024] FIG. 15 is a block diagram illustrating systems according to some example embodiments; and

[0025] FIG. 16 is a block diagram of a system-on-chip (SoC) according to some example embodiments.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] Hereinafter, some example embodiments will be described in detail with reference to the accompanying drawings. Unless otherwise noted, like reference characters denote like elements throughout the attached drawings and written description, and thus descriptions will not be repeated.

[0027] Although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections, these terms are only used to distinguish one element, component, region, layer, or section, from another region, layer, or section. Thus, a first element, component, region, layer, or section, discussed below may be termed, for example, a fifth element, component, region, layer, or section, without departing from the scope of this disclosure.

[0028] FIG. 1 is a schematic block diagram illustrating a plurality of elements included in an analog-to-digital converting circuit 10, according to some example embodiments.

[0029] Referring to FIG. 1, the analog-to-digital converting circuit 10 may be configured to convert an analog signal (e.g., of an electronic device) into a digital signal. For example, the electronic device may be implemented as a communication device, and may be configured to communicate with another device. For example, the electronic device may be (and/or used in) a wireless communication device, a cellular phone, a personal digital assistant (PDA), a handheld device, a wireless modem, a wireless phone, a radio station, a Bluetooth device, a health care device, a wearable device, and/or the like. For example, the electronic device may be implemented as a semiconductor device so as to program or read data at the request of a host.

[0030] A plurality of first through n-th reference voltage generators 100a through 100n may receive a bandgap reference voltage and respectively generate reference voltages based on the bandgap reference voltage. The reference voltages respectively generated by the first through n-th reference voltage generators 100a through 100n may have the same voltage value as each other, but may be slightly changed, e.g., by the first through n-th decoupling capacitors CREF1 through CREFn respectively included in the first through n-th reference voltage generators 100a through 100n are respectively connected to capacitors (e.g., C.sub.1 through C.sub.4 of FIG. 8) of the analog-to-digital converter (ADC 200). For example, when a switch, among a plurality of switches 400, corresponding to the first reference voltage generator 100a is turned on, the first decoupling capacitor C.sub.REF1 connected to the first reference voltage generator 100a may be connected to the ADC 200, and a reference voltage may be decreased by a peak current that is supplied from the first decoupling capacitor C.sub.REF1 to the ADC 200.

[0031] As at least one of the switches 400 is turned on, at least one of the first through n-th reference voltage generators 100a through 100n may be connected to the ADC 200, and the ADC 200 may convert an analog signal into a digital signal based on a reference voltage provided from the connected one of the first through n-th reference voltage generators 100a through 100n. According to some example embodiments, the ADC 200 may include a successive approximation regulator (SAR) ADC (not illustrated). The generating of a digital signal based on a reference voltage will be described in detail with reference to FIGS. 8 through 10.

[0032] A controller 300 may control the switches 400 to provide a reference voltage from at least one of the first through n-th reference voltage generators 100a through 100n to the ADC 200. In addition, the controller 300 may transmit a control signal to the ADC 200 to generate a comparison voltage with respect to each bit of a digital signal, wherein the digital signal is constituted of a plurality of bits. For example, the controller 300 may be and/or may include processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuity more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), and programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The comparison voltage may be compared with the voltage level of an analog signal such that a logic level of a corresponding bit position is determined. An example embodiment of determining a logic level according to a result of comparing a comparison voltage with the voltage level of an analog signal will be described in detail with reference to FIGS. 9 and 10.

[0033] FIG. 2 is a schematic block diagram of an analog-to-digital converting circuit according to a comparative embodiment.

[0034] Referring to FIG. 2, the analog-to-digital converting circuit of the comparative embodiment may generate a reference voltage using a single reference voltage generator 101 and a capacitor C.sub.REF. According to the comparative embodiment, an ADC 201 may include a SAR ADC, and the reference voltage generator 101 may include a low-dropout regulator (LDO) (not illustrated) that generates a low-power reference voltage. When the analog-to-digital converting circuit of the comparative embodiment performs a capacitive digital-to-analog converter (CDAC) switching operation, the reference voltage generator 101 may consume high power to supply a peak current, which has a high-frequency signal characteristic, to the ADC 201. In some cases, the power consumed by the reference voltage generator 101 may be greater than power consumed by the SAR ADC.

[0035] When the reference voltage generator 101 that generates a reference voltage with low power is used, a capacitor having high capacitance may be necessary to decrease a change in a voltage generated by a peak current below a threshold level. For example, the threshold level may be a voltage level corresponding to a comparison voltage of the least significant bit (LSB) of a digital signal. For example, in the case of a SAR ADC, a capacitor of about 1 nF may be necessary to secure a resolution of about 12 bits, and a 1 nF capacitor may occupy a large proportion of the area in the analog-to-digital converting circuit.

[0036] When the reference voltage generator 101 according to the comparative embodiment includes an LDO generating a reference voltage with low power, the reference voltage generator 101 has a low-speed feedback loop and may thus not supply a peak current necessary for the CDAC switching operation of the ADC 201. Accordingly, the peak current may not be supplied from the capacitor C.sub.REF to the ADC 201.

[0037] FIG. 3 is a graph of a comparison voltage generated according to a comparative embodiment, a current provided by a reference voltage generator, a peak current consumed by an analog-to-digital converting circuit, and a reference voltage.

[0038] Referring to FIG.2 and FIG. 3, the analog-to-digital converting circuit may perform conversion in first through fourth time periods T.sub.1 through T.sub.4. During the first through fourth time periods T.sub.1 through T.sub.4, the reference voltage generator 101 may continuously output a reference current I.sub.REF at a low level, which has an average of a current I.sub.CDAC needed by the ADC 201, and the capacitor C.sub.REF may be charged by the reference current I.sub.REF.

[0039] For example, during a first time period T.sub.1, the analog-to-digital converting circuit may sample an analog signal, and/or the reference voltage generator 101 may supply charges to the capacitor C.sub.REF. After completing the sampling of the analog signal, the analog-to-digital converting circuit may perform conversion during the second time period T.sub.2. The ADC 201 may perform a CDAC switching operation in correspondence to a bit position to undergo conversion in the second time period T.sub.2 and receive a peak current I.sub.PEAK in correspondence to the CDAC switching operation. The peak current I.sub.PEAK may correspond to a pulse current that is generated with the change in the number of comparison voltage capacitors connected to the reference voltage generator 101 according to the CDAC switching operation. For example, the peak current I.sub.PEAK may be generated when the ADC 201 performs a CDAC switching operation during the second time period T.sub.2, and a comparison voltage V.sub.CDAC (e.g., that is generated from a reference voltage V.sub.REFP according to the CDAC switching operation) may be updated.

[0040] The analog-to-digital converting circuit that has completed the conversion according to the CDAC switching operation may reset the comparison voltage V.sub.CDAC by performing a CDAC reset operation during the third time period T.sub.3. The reset of the comparison voltage V.sub.CDAC may include an operation of resetting a digital input voltage of the comparison voltage V.sub.CDAC to an initial value to convert a subsequently sampled signal into a digital signal. After the CDAC reset, the analog-to-digital converting circuit may perform a sampling operation on a subsequent analog signal during the fourth time period T.sub.4.

[0041] At this time, the comparison voltage V.sub.CDAC may have been generated from the reference voltage V.sub.REFP through CDAC switching. It may be ideal that the reference voltage generator 101 generates the reference voltage VREFP at a constant level such that a digital signal is accurately generated according to a result of comparing the comparison voltage V.sub.CDAC with the voltage level of a sampled signal. However, though not illustrated in FIG. 3, the reference voltage V.sub.REFP may be changed, e.g., by the amount of charges drained out of the capacitor C.sub.REF, due to the expression of the peak current I.sub.PEAK. The change in the reference voltage V.sub.REFP will be described with reference to FIG. 4 below.

[0042] FIG. 4 is a graph showing a change in the reference voltage V.sub.REFP, which is generated according to the comparative embodiment of FIG. 3, with respect to the peak current I.sub.PEAK.

[0043] Referring to FIG. 4, each time the peak current I.sub.PEAK is generated, the amount of charge stored in the capacitor C.sub.REF may be decreased, e.g., by the peak current I.sub.PEAK, and accordingly, the reference voltage V.sub.REFP may be decreased. When there is no peak current I.sub.PEAK, the reference voltage generator 101 may output an average of the reference current Icmc, which is used for the CDAC switching operation, as the reference current I.sub.REF, and accordingly, the reference voltage V.sub.REFP may increase by a slope of the reference current I.sub.REF/the capacitance of the capacitor C.sub.REF. Such a repetition of the decrease and increase of the reference voltage V.sub.REFP may deteriorate the performance of the ADC 201. Furthermore, the capacitor C.sub.REF may need to have and/or maintain a high capacitance to maintain the amplitude change of the reference voltage V.sub.REFP below a threshold voltage level. For example, when the reference voltage V.sub.REFP is generated using a single reference voltage generator (e.g., the reference voltage generator 101) and the capacitor C.sub.REF (e.g., according to the comparative embodiment) the capacitor C.sub.REF needs to have high capacitance, and accordingly, a circuit for generating the reference voltage VREFP needs to be assigned a large area in the analog-to-digital converting circuit.

[0044] Contrarily, an analog-to-digital converting circuit according to some example embodiments may be provided with charges from a capacitor, among a plurality of capacitors, corresponding to a conversion period and may, thus, include capacitors having lower capacitance, compared to the comparative embodiment, and accordingly, the space efficiency of a circuit configuration may be improved and/or optimized.

[0045] FIG. 5 is a diagram of the configuration of an analog-to-digital converting circuit 10 including a plurality of reference voltage generators, according to some example embodiments.

[0046] Referring to FIG. 5, the analog-to-digital converting circuit 10 may include a first reference voltage generation circuit and a second reference voltage generation circuit. Each of the first and second reference voltage generation circuits may include a paired reference voltage generator (100a and 100b) and decoupling capacitor (C.sub.ref1 and C.sub.ref2). For example, the first reference voltage generation circuit may include the first reference voltage generator 100a and the first decoupling capacitor C.sub.REF1, and the second reference voltage generation circuit may include the second reference voltage generator 100b and the second decoupling capacitor C.sub.REF2. For example, each of the first and second reference voltage generators 100a and 100b may include an LDO that generates a reference voltage with low power. The circuit diagram of each of the first and second reference voltage generators 100a and 100b will be described in detail with reference to FIG. 6 below.

[0047] Each of the first and second reference voltage generation circuits may provide a reference voltage to the ADC 200, e.g., according to the activation and/or deactivation of a switch (e.g., a first switch SW.sub.1 and/or a second switch SW.sub.2) connected to the first or second reference voltage generation circuit. For example, when a first switch SW.sub.1 is activated in a first conversion period, a first reference voltage V.sub.REF1, generated by the first reference voltage generation circuit, may be provided to the ADC 200 and/or when a second switch SW.sub.2 is activated in a second conversion period, a second reference voltage V.sub.REF2 generated by the second reference voltage generation circuit may be provided to the ADC 200.

[0048] The ADC 200 may convert an input analog signal into a digital signal and may perform a sampling operation on the analog signal before the conversion operation. For example, in some example embodiments, the ADC 200 may include an SAR ADC and may generate a digital signal with respect to a sampled signal based on a result of comparing the sampled signal with a comparison voltage generated using a reference voltage. The SAR ADC may change a comparison voltage for each bit in the digital signal and compare the sampled signal with the comparison voltage. An example conversion operation of the SAR ADC will be described below with reference to FIGS. 7 through 9.

[0049] Each switch connected to a reference voltage generation circuit may be controlled by a controller (e.g., the controller 300 in FIG. 1). The on or off state of each switch may be updated at the transition of a predetermined (and/or otherwise devised) conversion period of an entire conversion period. For example, the first switch SW.sub.1 may be activated and a second switch SW.sub.2 may be deactivated in a first conversion period, whereas the first switch SW.sub.1 may be deactivated and the second switch SW.sub.2 may be activated in a second conversion period. An example embodiment in which the entire conversion period is divided into the first conversion period and the second conversion period will be described with reference to FIGS. 10 through 12 below.

[0050] FIG. 6 is a circuit diagram of the reference voltage generator 100a and 100b according to the embodiment of FIG. 5.

[0051] Referring to FIG. 6, the reference voltage generators 100a and 100b may externally receive a bandgap reference voltage V.sub.BGR and generate a reference current I.sub.REFP from a supply voltage V.sub.DD according to a result of comparing the bandgap reference voltage V.sub.BGR with a reference voltage V.sub.REF that has been fed back. The reference voltage generator may include a regulator that reliably generates a constant voltage and/or an LDO that generates the reference voltage V.sub.REF with low power.

[0052] The bandgap reference voltage V.sub.BGR may include a direct current (DC) voltage that is generated at a predetermined (and/or otherwise set) voltage level outside the analog-to-digital converting circuit. An error amplifier included in the reference voltage generator may compare the bandgap reference voltage V.sub.BGR with a feedback voltage. The feedback voltage may be determined by resistors connected to an end of the error amplifier. When the feedback voltage is lower than the bandgap reference voltage V.sub.BGR, a transistor may be activated, and the reference current I.sub.REFP may be output from the supply voltage V.sub.DD connected to an end of the activated transistor. The reference voltage generator may generate and output the reference voltage V.sub.REF according to the reference current I.sub.REFP.

[0053] Although the embodiment of FIG. 6 shows a circuit diagram of an LDO that generates the reference voltage V.sub.REF with low power, the example embodiments are not limited thereto. For example, the embodiments may include any embodiments, in which the peak current I.sub.PEAK may be supplied from the first or second decoupling capacitor C.sub.REF1 or C.sub.REF2 in FIG. 5 to the ADC 200, and/or the reference voltage V.sub.REF may be generated by a buffer and/or the like.

[0054] FIG. 7 is a block diagram of the configuration of the ADC 200 according to some example embodiment. FIG. 8 is a circuit diagram illustrating the DAC 230 and the comparator 240 of the ADC 200, according to some example embodiments. FIG. 9 is a graph showing data of a digital signal generated by comparing a comparison voltage with the voltage level of the input signal V.sub.in.

[0055] Referring to FIG. 7, the ADC 200 may include a control circuit 210, a sample/hold circuit 220, a DAC 230, and a comparator 240. The ADC 200 may externally receive a clock signal CLK and perform a conversion operation on an analog signal in synchronization with the clock signal CLK.

[0056] For example, the sample/hold circuit 220 may receive the clock signal CLK and an input signal V.sub.in corresponding to an analog signal and perform a sampling operation. The sample/hold circuit 220 may generate a sampled signal from the input signal V.sub.in based on the clock signal CLK and output the sampled signal V.sub.samp to the DAC 230. The control circuit 210 may provide a control signal CS to the DAC 230, and the DAC 230 may generate the comparison voltage V.sub.CDAC in response to the control signal CS.

[0057] Referring to FIGS. 7 and 8, the DAC 230 may generate the comparison voltage V.sub.CDAC for each bit to be generated for a digital signal, which may be comprise a plurality of bits, based on a common voltage V.sub.CDAC and the reference voltage V.sub.REF received from the reference voltage generator. The comparison voltage V.sub.CDAC may have a voltage level obtained by adding and/or subtracting the voltage level of the reference voltage V.sub.REF or the common voltage V.sub.CM to (and/or from) the voltage level of the sampled signal received from the sample/hold circuit 220. An example embodiment in which the DAC 230 generates the comparison voltage V.sub.CDAC for each bit will be described with reference to FIGS. 8 and 9 below.

[0058] The comparator 240 may compare the comparison voltage V.sub.CDAC generated by the DAC 230 with the common voltage V.sub.CM and generate a comparison result voltage V.sub.COMP. For example, the DAC 230 may generate the comparison voltage VcDAc for determining the logic level of the most significant bit (MSB), and the comparator 240 may compare the common voltage V.sub.CM with the comparison voltage V.sub.CDAC. When the comparison voltage V.sub.CDAC is higher than or equal to the common voltage V.sub.CM, the comparator 240 may output the comparison result voltage V.sub.COMP at a logic high level. When the comparison voltage V.sub.CDAC is lower than the common voltage V.sub.CM, the comparator 240 may output the comparison result voltage V.sub.COMP at a logic low level.

[0059] The comparator 240 may provide data of a logic level determined for each bit to the control circuit 210. The control circuit 210 may generate the control signal CS for generating the comparison voltage V.sub.CDAC for a subsequent bit, according to the logic level. For example, when data of a logic high level is output in correspondence to the MSB, the control circuit 210 may determine a voltage, which is lower than a comparison voltage corresponding to the MSB, as a comparison voltage corresponding to a subsequent bit. When data of a logic low level is output in correspondence to the MSB, the control circuit 210 may determine a voltage, which is higher than a comparison voltage corresponding to the MSB, as a comparison voltage corresponding to a subsequent bit. For example, the voltage level of the comparison voltage V.sub.CDAC corresponding to a lower bit may differ based on the logic level of an upper bit.

[0060] The comparator 240 may provide the comparison result voltage V.sub.COMP corresponding to each of bits from the MSB to the LSB to the control circuit 210, and the control circuit 210 may generate a digital output signal D.sub.out based on the logic level of the comparison result voltage V.sub.COMP corresponding to each bit. For example, the digital output signal D.sub.out generated by the control circuit 210 may include data information constituted of a series of bits.

[0061] FIG. 8 shows an example embodiment of the DAC 230, which receives the input signal V.sub.in in a single-ended mode and performs digital-to-analog conversion, and the comparator 240; however, the DAC 230 is not limited to the example of FIG. 8 but may include any embodiment that may generate a plurality of comparison voltages V.sub.CDAC under the control of a switch array and compare one of the comparison voltages V.sub.CDAC with the common voltage V.sub.CM. For example, DAC 230 is not limited to the number of comparison voltage capacitors (e.g., Ci through C4) and/or comparison voltage switches (N1 through N3) illustrated in FIG. 8. Additionally, the DAC 230 may receive the sampled signal V.sub.samp in a differential mode and perform digital-to-analog conversion. Hereinafter, an example embodiment of generating a 3-bit digital signal from an analog signal will be described with reference to FIGS. 8 and 9.

[0062] Referring to FIG. 8, the DAC 230 may include a capacitor array, which includes a plurality of comparison voltage capacitors (e.g., first through fourth comparison voltage capacitors C.sub.1 through C.sub.4) and a switch array, which includes a plurality of comparison voltage switches (e.g., first through third comparison voltage switches N.sub.1 through N.sub.3). Some of the comparison voltage capacitors of the capacitor array may be respectively connected to the comparison voltage switches of the switch array. For example, the first through third comparison voltage capacitors C.sub.1 through C.sub.3 may be respectively connected to the first through third comparison voltage switches N.sub.1 through N.sub.3.

[0063] Each of the first through third comparison voltage capacitors C.sub.1 through C.sub.3 of the capacitor array may generate data corresponding to one of first through third bits, and the fourth comparison voltage capacitor C4 may correspond to a dummy capacitor. For example, the first bit may correspond to the MSB of a data signal, and the third bit may correspond to the LSB of the data signal.

[0064] When the DAC 230 performs a conversion operation to generate the first bit, the first comparison voltage switch N.sub.1 connected to the first comparison voltage capacitor C.sub.1 may be switched. When the DAC 230 performs a conversion operation to generate the second bit, the second comparison voltage switch N.sub.2 connected to the second comparison voltage capacitor C.sub.2 may be switched. When the DAC 230 performs a conversion operation to generate the third bit, the third comparison voltage switch N.sub.3 connected to the third comparison voltage capacitor C.sub.3 may be switched.

[0065] The capacitance of the first comparison voltage capacitor C.sub.1 that generates the data of the MSB may be twice the capacitance of the second comparison voltage capacitor C.sub.2 that generates the data of a lower bit next to the MSB. The capacitance of the second comparison voltage capacitor C.sub.2 may be twice the capacitance of the third comparison voltage capacitor C.sub.3 that generates the data of the LSB. In some example embodiments, the capacitance of the third comparison voltage capacitor C.sub.3 may be the same as the capacitance of the fourth comparison voltage capacitor C.sub.4.

[0066] The DAC 230 may, for example, generate the comparison voltage V.sub.CDAC corresponding to a bit to be converted using a CDAC switching operation. Before the data of the MSB is generated, the first through third comparison voltage switches N.sub.1 through N.sub.3 may be connected to a node of the common voltage V.sub.CM, and the comparison voltage V.sub.CDAC may have the same value as the sampled signal V.sub.samp. The amount of charges stored in the first through fourth comparison voltage capacitors C.sub.1 through C.sub.4 may be defined as Equation 1.

Q=(C.sub.1+C.sub.2+C.sub.3+C.sub.4)*(V.sub.samp−V.sub.CM)   [Equation 1]

[0067] Here, when V.sub.CM is V.sub.REF/2, the comparator 240 may generate MSB data by comparing the level of the sampled signal V.sub.samp with the level of the common voltage V.sub.CM. The negative (−) terminal of the comparator 240 may receive the common voltage VCM, and the positive (+) terminal thereof may be connected to an output node of the DAC 230, and accordingly, the logic level of the comparison result voltage V.sub.COMP output from the comparator 240 may be determined according to the sign of the voltage level difference between the comparison voltage V.sub.CDAC and the common voltage VCM. For example, when the logic level of the comparison result voltage V.sub.COMP is a logic high level, the MSB data may be “1,” And when the logic level of the comparison result voltage V.sub.COMP is a logic low level, the MSB data may be

[0068] According to some example embodiments, the DAC 230 may perform a different switching operation on a lower bit according to the logic level of an upper bit. For example, the DAC 230 may change the switching operation of the switch array according to the logic level of the MSB. When the logic level of the MSB is a logic low level, the first comparison voltage switch N.sub.1 may be switched to a node connected to the reference voltage V.sub.REF. When the logic level of the MSB is a logic high level, the first comparison voltage switch N.sub.1 may be switched to a ground node.

[0069] Accordingly, when the sampled signal V.sub.samp is lower than the common voltage VCM, the comparison result voltage V.sub.COMP may have low-level data, and the control circuit 210 in FIG. 7 may apply the control signal CS to the DAC 230 to connect the first comparison voltage switch N.sub.1 to the node connected to the reference voltage V.sub.REF and maintain the connection between each of the second and third comparison voltage switches N.sub.2 and N.sub.3 and a node connected to the common voltage V.sub.CM. For example, the amounts of charges respectively stored in the first through fourth comparison voltage capacitors C.sub.1 through C.sub.4 may have the relationship defined as Equation 2 to satisfy charge conservation.

(C.sub.1+C.sub.2+C.sub.3+C.sub.4)*(V.sub.samp−V.sub.CM)=C.sub.1*(V.sub.CDAC−V.sub.REF)+(C.sub.2+C.sub.3+C.sub.4)*(V.sub.CDAC−V.sub.CM)   [Equation 2]

[0070] Here, when the capacitance of the first comparison voltage capacitor C.sub.1 is 4*C, the capacitance of the second comparison voltage capacitor C.sub.2 is 2*C, and the capacitance of each of the third and fourth comparison voltage capacitors C.sub.3 and C.sub.4 is C; the comparison voltage V.sub.CDAC satisfying Equation 2 may be given Equation 3.

V.sub.CDAC=V.sub.samp+1/4*V.sub.REF   [Equation 3]

[0071] To generate the data of a bit following the MSB, the comparator 240 may determine the logic level of the comparison result voltage V.sub.COMP (e.g., by comparing the voltage level of the common voltage V.sub.CM with the voltage level of the comparison voltage V.sub.CDAC).

[0072] Referring to Equation 3, and the relationship between the reference voltage V.sub.REF and the common voltage V.sub.CM, when the voltage level of the comparison voltage V.sub.CDAC is at least a half of the voltage reference (e.g., (1/2)*V.sub.REF), the comparator 240 may output a logic high level for the comparison result voltage V.sub.COMP. When the voltage level of the comparison voltage V.sub.CDAC is lower than (1/2)*V.sub.REF, the comparator 240 may output a logic low level for the comparison result voltage V.sub.COMP.

[0073] When the data of a bit following the MSB corresponds to a logic low level, the second comparison voltage switch N.sub.2 may be switched to the node connected to the reference voltage V.sub.REF. For example, the voltage level of the comparison voltage V.sub.CDAC satisfying charge conservation may be defined as Equation 4.

V.sub.CDAC=V.sub.samp+1/4*V.sub.REF+1/8*V.sub.REF   [Equation 4]

[0074] However, when the data of the bit following the MSB corresponds to a logic high level, the second comparison voltage switch N.sub.2 may be switched to the ground node. For example, the voltage level of the comparison voltage VCDAC satisfying charge conservation may be defined as Equation 5.

V.sub.CDAC=V.sub.samp+1/4*V.sub.REF−1/8*V.sub.REF   [Equation 5]

[0075] For example, referring to FIG. 9, the DAC 230 may update the comparison voltage VcDAc for each of bits from the MSB to the LSB through CDAC switching while performing a conversion operation on a sampled signal and determine the data of a digital signal according to a result of comparing the comparison voltage V.sub.CDAC with the common voltage V.sub.CM.

[0076] When the DAC 230 sequentially performs conversion operations respectively for the bits from the MSB to the LSB, the difference between successive comparison voltages V.sub.CDAC may decrease. For example, a comparison voltage, which has a difference of 0.25V.sub.REF from a comparison voltage generated when a conversion operation is performed for the first bit, may be generated when a conversion operation is performed for the second bit; and a comparison voltage, which has a difference of 0.125 V.sub.REF from the comparison voltage generated when the conversion operation is performed for the second bit, may be generated when a conversion operation is performed for the third bit. In other words, when a conversion operation is performed for a lower bit, a sophisticated voltage shift may be necessary for accurate comparison.

[0077] FIG. 10 is a graph showing switch signals applied to a plurality of switches and a comparison current provided to an ADC, according to some example embodiments.

[0078] Referring to FIGS. 5 and 10, the first switch SW.sub.1 connecting the first reference voltage generation circuit to the ADC 200 may be activated in a different period than the second switch SW.sub.2 connecting the second reference voltage generation circuit to the ADC 200. For example, the first switch SW.sub.1 may be activated while the second switch SW.sub.2 is deactivated in the first conversion period of an entire conversion period; and the first switch SW.sub.1 may be deactivated while the second switch SW.sub.2 is activated in the second conversion period of the entire conversion period.

[0079] The first conversion period (in which the first switch SW.sub.1 is activated) may correspond to a time period, in which a significant voltage shift is necessary in a comparison voltage each time when a CDAC switching operation is performed. The second conversion period (in which the second switch SW.sub.2 is activated) may correspond to a time period, in which a smaller voltage shift than in the first conversion period is used in a comparison voltage each time when a CDAC switching operation is performed.

[0080] For example, in the first conversion period, there may be a great change in the reference voltage V.sub.REF because a large peak current is provided from the first decoupling capacitor C.sub.REF1 of the first reference voltage generation circuit to the ADC 200; and, in the second conversion period, there may be a small change in the reference voltage V.sub.REF because a small peak current is provided from the second decoupling capacitor C.sub.REF2 of the second reference voltage generation circuit to the ADC 200. For example, a sixth time period T.sub.6 in FIG. 10 may correspond to the first conversion period, and a seventh time period T.sub.7 in FIG. 10 may correspond to the second conversion period.

[0081] In addition, because a large peak current may be output from a reference voltage generation circuit during an eighth time period T.sub.8 (in which the analog-to-digital converting circuit 10 resets the DAC 230) the first switch SW.sub.1 may be activated such that the first reference voltage generation circuit is connected to the ADC 200. However, a large peak current does not need to be output during fifth and ninth time periods T.sub.5 and T.sub.9, in which a sampling operation is performed, and therefore, the second switch SW.sub.2 may be activated.

[0082] FIG. 11 is a graph showing a plurality of reference voltages V.sub.REF generated by the analog-to-digital converting circuit 10 and reference voltages V.sub.REF applied to the ADC 200, according to some example embodiments.

[0083] Referring to FIGS. 10 and 11, a first reference voltage V.sub.REF1 generated by the first reference voltage generation circuit may be applied to the ADC 200 during the sixth time period T.sub.6, and a second reference voltage V.sub.REF2 generated by the second reference voltage generation circuit may be applied to the ADC 200 during the seventh time period T.sub.7.

[0084] The reference voltage may be a DC voltage, but the reference voltage V.sub.REF is enlarged in the direction of the voltage scale in FIG. 11 to help explain a fluctuation in the reference voltage V.sub.REF. When the fluctuation in the reference voltage V.sub.REF increases due to a peak current, an incorrect comparison voltage may be generated, causing an error in a result of analog-to-digital conversion. To correct the error, the analog-to-digital converting circuit 10 may perform error correction using redundancy.

[0085] For example, referring to FIG. 11, the reference voltage V.sub.REF generated in the sixth time period T.sub.6 may have a lower voltage level than the reference voltage V.sub.REF generated in the seventh time period T.sub.7. At this time, the analog-to-digital converting circuit 10 may generate an incorrect comparison voltage based on a difference between the minimum of the reference voltage V.sub.REF generated in the sixth time period T.sub.6 and the maximum of the reference voltage V.sub.REF generated in the seventh time period T.sub.7.

[0086] The error correction using redundancy may include, e.g., additionally performing a conversion operation for a dummy bit. For example, between the first conversion period and the second conversion period, a conversion operation may be performed for a dummy bit to correct an error occurring in the first conversion period. According to some example embodiments, the redundancy error correction may not be limitedly performed only between the first conversion period and the second conversion period but be performed, e.g., in any period in which a second conversion operation is performed.

[0087] FIG. 12 is a graph showing the comparison voltage V.sub.CDAC and the comparison current I.sub.CDAC, which are generated by the ADC 200, according to FIGS. 10 and 11.

[0088] Referring to FIG. 12, a peak current used by the DAC 230 during the sixth time period T.sub.6 may be provided from the first reference voltage generation circuit to the ADC 200, and a peak current needed by the DAC 230 during the seventh time period T.sub.7 may be provided from the second reference voltage generation circuit to the ADC 200. Referring to FIGS. 5, 10 and 12, the peak current generated by the first reference voltage generation circuit in FIG. 10 may correspond to a peak current in the sixth time period T.sub.6 in FIG. 12, and the peak current generated by the second reference voltage generation circuit FIG. 10 may correspond to a peak current in the seventh time period T.sub.7 in FIG. 12.

[0089] Each time when a CDAC switching operation is performed in the sixth time period T.sub.6 and the seventh time period T.sub.7, the comparison voltage Vc.sub.DAc may be decreased or increased by a peak current consumed by a CDAC, and the peak current may be applied to the ADC 200. After conversion is completed, the first reference voltage generation circuit may receive the peak current in the eighth time period T.sub.8 so that a CDAC reset operation may be performed.

[0090] According to some example embodiments, the analog-to-digital converting circuit 10 may generate the reference voltage V.sub.REF using different reference voltage generation circuits in the first conversion period, in which a change in the comparison voltage V.sub.CDAC and a peak current are relatively great, and in the second conversion period, in which the change in the comparison voltage V.sub.CDAC and the peak current are relatively small, thereby generating the reference voltage V.sub.REF using lower capacitance of capacitors, compared to the comparative embodiment. In addition, because a small peak current is necessary in the second conversion period, an LDO of the second reference voltage generation circuit may generate the reference voltage V.sub.REF with lower power, compared to the comparative embodiment.

[0091] Although it has been described above that the first and second reference voltage generation circuits alternately provide the reference voltage V.sub.REF to the ADC 200 in the analog-to-digital converting circuit 10, the analog-to-digital converting circuit 10 is not limited thereto. The reference voltage V.sub.REF may be provided to the ADC 200 using at least three reference voltage generation circuits.

[0092] FIG. 13 is a graph showing the results of simulating a signal-to-noise and distortion ratio (SNDR) of an ADC with respect to the capacitance of decoupling capacitors used in a present embodiment and a comparative embodiment.

[0093] Referring to FIG. 13, as the capacitance of the decoupling capacitor CREF used in the comparative embodiment increases, the SNDR indicating the performance of the analog-to-digital converting circuit 10 also increases. This will be understood from the description of FIG. 4 that a change in the reference voltage V.sub.REF decreases as the capacitance of the decoupling capacitor CREF increases.

[0094] Similarly, as the capacitance of a decoupling capacitor used in the present embodiment increases, the SNDR may also increase. However, according to the present embodiment, reference voltage generation circuits may alternately generate the reference voltage V.sub.REF in a plurality of conversion periods, into which an entire conversion period is divided, and therefore, the capacitance of a decoupling capacitor may be less compared to the comparative embodiment.

[0095] For example, though the decoupling capacitor C.sub.REF of the comparative embodiment needs to have a capacitance of at least 900 pF not to allow a change in the reference voltage V.sub.REF to influence the SNDR, according to the present embodiment, when the first decoupling capacitor C.sub.REF1 has a capacitance of at least 8 pF and the second decoupling capacitor C.sub.REF2 has a capacitance of at least 40 pF, the SNDR does not deteriorate. Thus, the present embodiment may secure similar SNDR performance to the comparative embodiment just by using a capacitor having about 1/19 of the capacitance of the comparative embodiment, and accordingly, the area of the analog-to-digital converting circuit 10 may be significantly reduced.

[0096] FIG. 14 is a block diagram of a communication device according to an example embodiment.

[0097] Referring to FIG. 14, a communication device 1000 may include a receiver 1012, a transmitter 1016, a communication module 1020, an antenna 1018, an external input/output (I/O) device 1040, and a reference oscillator 1042. The receiver 1012 may include the analog-to-digital converting circuit 10 performing an analog-to-digital conversion operation according to the embodiments of FIGS. 1 through 13. The receiver 1012 may receive an analog signal through the antenna 1018, convert the analog signal into a digital signal using the analog-to-digital converting circuit 10, and provide the digital signal to the communication module 1020. The transmitter 1016 may receive a digital signal from the communication module 1020, convert the digital signal into an analog signal, and output the analog signal through the antenna 1018.

[0098] The communication module 1020 may include a modem processor 1022, a reduced instruction set computer (RISC)/digital signal processor (DSP) 1024, a controller/processor 1026, a memory 1028, an I/O device 1030, and a phase-locked loop (PLL) 1032.

[0099] The modem processor 1022 may perform processing operations, such as encoding, modulation, demodulation, and decoding, to transmit and receive data. The RISC/DSP 1024 may perform a general or specialized processing operation in the communication device 1000. The controller/processor 1026 may control blocks of the communication module 1020. The memory 1028 may store data and various instructions code. The I/O device 1030 may communicate with the external I/O device 1040. The I/O device 1030 may include the analog-to-digital converting circuit 10 performing analog-to-digital conversion according to the embodiments described with reference to FIGS. 1 through 13. The I/O device 1030 may convert a data signal received from the external I/O device 1040 into a digital signal using the analog-to-digital converting circuit 10. The external I/O device 1040 may include an input (a camera, microphone, touch-panel, and/or the like) and/or output (a display, a speaker, haptic feedback, and/or the like) device. The PLL 1032 may perform frequency modulation using a frequency signal received from the reference oscillator 1042. The reference oscillator 1042 may include a crystal oscillator (XO), a voltage controlled crystal oscillator (VCXO), and/or a temperature compensated crystal oscillator (TCXO). The communication module 1020 may perform a processing operation (e.g., for communication) using an output signal generated by the PLL 1032.

[0100] FIG. 15 is a block diagram illustrating systems according to an example embodiment.

[0101] Referring to FIG. 15, a memory system 2000 and a host system 2300 may communicate with each other through an interface 2400. The memory system 2000 may include a memory controller 2100 and memory devices 2200.

[0102] The interface 2400 may use an electrical signal and/or an optical signal. For example, the interface 2400 may include at least one of a serial advanced technology attachment (SATA) interface, a SATA express (SATAe) interface, a serial attached small computer system interface (SCSI) (SAS), a universal serial bus (USB) interface, and/or the like. The host system 2300 and the memory controller 2100 may include a serializer/deserializer (SerDes) for serial communication.

[0103] In some example embodiments, the memory system 2000 may be configured to be removably coupled to the host system 2300 and may communicate with the host system 2300. The memory devices 2200 may include volatile memory and/or non-volatile memory. The memory system 2000 may be called a storage system. For example, the memory system 2000 may include at least one of a solid-state drive (or disk) (SSD), an embedded SSD (eSSD), a multimedia card (MMC), an embedded MMC (eMMC), and/or the like. The memory controller 2100 may control the memory devices 2200 in response to a request received from the host system 2300 through the interface 2400.

[0104] The analog-to-digital converting circuit 10 according to example embodiments may be included in at least one of (and/or each of) the memory controller 2100, the memory devices 2200, and the host system 2300. For example, the memory controller 2100, the memory devices 2200, and the host system 2300 may receive a data signal based on pulse amplitude modulation (PAM) and convert the data signal into digital data using the method according to the example embodiments.

[0105] FIG. 16 is a block diagram of a system-on-chip (SoC) according to some example embodiments.

[0106] A SoC 3000 may refer to an integrated circuit in which components of a computing system (and/or another electronic system) are integrated. For example, an application processor (AP), as an example of the SoC 3000, may include a processor and components for other functions.

[0107] Referring to FIG. 16, the SoC 3000 may include a core 3100, a DSP 3200, a graphics processing unit (GPU) 3300, an embedded memory 3400, a communication interface 3500, and/or a memory interface 3600. The elements of the SoC 3000 may communicate with one another through a bus 3700.

[0108] The core 3100 may process instructions and control the operations of the elements of the SoC 3000. For example, the core 3100 may drive an operating system (OS) by processing a series of instructions and execute applications on the OS. The DSP 3200 may generate useful data by processing a digital signal, for example, provided from the communication interface 3500. The GPU 3300 may generate data, which corresponds to an image output through a display device, from image data provided from the embedded memory 3400 or the memory interface 3600 or may encode the image data. The embedded memory 3400 may store data necessary for the operations of the core 3100, the DSP 3200, and the GPU 3300. The memory interface 3600 may provide an interface for an external memory of the SoC 3000 (e.g., dynamic random access memory (DRAM) or flash memory).

[0109] The communication interface 3500 may process and/or provide serial communication with the outside of the SoC 3000. For example, the communication interface 3500 may access Ethernet and include a SerDes for serial communication.

[0110] The analog-to-digital converting circuit 10 according to the example embodiments may be applied to the communication interface 3500 and/or the memory interface 3600. For example, the communication interface 3500 and/or the memory interface 3600 may receive a data signal based on PAM and convert the data signal into digital data using the method according to the example embodiments.

[0111] While the inventive concepts have been particularly shown and described with reference to some example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.