GEIGER-MODE FOCAL PLANE ARRAY WITH MONOLITHICALLY INTEGRATED RESISTORS

Abstract

A GmAPD FPA having increased tolerance optical overstress includes a limit resistor that is monolithically integrated into each pixel in the FPA, and which limits the magnitude of the current entering the read out integrated circuit.

Claims

1.-12. (canceled)

13. A method for increasing the tolerance of a Geiger-mode avalanche photodiode (GmAPD) focal plane array (FPA) to optical overstress, the method comprising increasing, within each pixel of the GmAPD FPA, the series resistance of an electrical connection between the GmAPD and a unit cell of a read out integrated circuit (ROIC unit cell), the ROIC unit cell having an active quenching circuit.

14. The method of claim 13 and further wherein the electrical connection is between an electrical contact of the GmAPD and an input of a sense transistor in the active quenching circuit within the ROIC unit cell.

15. The method of claim 13 wherein increasing the series resistance consists of increasing the series resistance by an amount in a range of about 1 kOhm to about 100 kOhms.

16. The method of claim 13 wherein increasing the series resistance comprises using a thin-film resistor.

17. The method of claim 16 wherein increasing the series resistance comprises monolithically integrating the thin-film resistor into each pixel of the GmAPD FPA.

18. The method of claim 17 wherein increasing the series resistance comprises monolithically integrating the thin-film resistor into a GmAPD of each pixel of the GmAPD FPA.

19. The method of claim 17 wherein increasing the series resistance comprises monolithically integrating the thin-film resistor into a ROIC unit cell in each pixel of the GmAPD FPA.

20. The method of claim 16 wherein the thin-film resistor has a serpentine shape.

21. The method of claim 13 wherein the active quenching circuit comprises an arm transistor, a disarm transistor, and a sense transistor.

22. The method of claim 13 wherein increasing the series resistance comprises monolithically integrating a first thin-film resistor into a GmAPD of some pixels of the GmAPD FPA and integrating a second thin-film resistor into the ROIC unit cell of said some pixels of the GmAPD FPA.

23. A method for increasing the tolerance of a Geiger-mode avalanche photodiode (GmAPD) focal plane array (FPA) to optical overstress, the method comprising: monolithically integrating, into each pixel of the GmAPD FPA, a limit resistor, wherein the limit resistor is electrically coupled to an electrical contact of the GmAPD and to an active quenching circuit within a unit cell of a read out integrated circuit (ROIC unit cell).

24. The method of claim 23 wherein the electrical coupling to the active quenching circuit is to an input of a sense transistor in said active quenching circuit.

25. The method of claim 23 wherein the limit resistor increases the series resistance of the electrical coupling by an amount in the range of about 1 kOhm to about 100 kOhms.

26. The method of claim 23 wherein monolithically integrating the limit resistor into each pixel of the GmAPD FPA comprises monolithically integrating the limit resistor into a GmAPD in each pixel of the GmAPD FPA.

27. The method of claim 23 wherein monolithically integrating the limit resistor into each pixel of the GmAPD FPA comprises monolithically integrating the limit resistor into a ROIC unit cell in each pixel of the GmAPD FPA.

28. The method of claim 23 wherein monolithically integrating the limit resistor into each pixel of the GmAPD FPA comprises monolithically integrating a first limit resistor into a GmAPD of some pixels of the GmAPD FPA and integrating a second thin-film resistor into the ROIC unit cell of said some pixels of the GmAPD FPA.

29. The method of claim 23 wherein the limit resistor is a thin-film resistor.

30. The method of claim 29 wherein the limit resistor has a serpentine shape.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. 1 depicts an electrical circuit model of a prior-art GmAPD FPA pixel.

[0019] FIG. 2A depicts the voltage-vs-time behavior of the pixel of FIG. 1 following an avalanche event.

[0020] FIG. 2B depicts the current-vs-time behavior of the pixel of FIG. 1 following an avalanche event.

[0021] FIG. 3A depicts an electrical circuit model of a GmAPD FPA pixel in accordance with a first embodiment of the present invention.

[0022] FIG. 3B depicts an electrical circuit model of a GmAPD FPA pixel in accordance with a second embodiment of the present invention.

[0023] FIG. 4A depicts a comparison of the voltage-vs-time behavior of the GmAPD FPA pixel of FIG. 1 and a GmAPD FPA pixel in accordance with the present teachings, following an avalanche event.

[0024] FIG. 4B depicts a comparison of the current-vs-time behavior of the GmAPD FPA pixel of FIG. 1 and a GmAPD FPA pixel in accordance with the present teachings, following an avalanche event.

[0025] FIG. 5 depicts a flow diagram of method for fabricating a GmAPD PDA pixel in accordance with the illustrative embodiment.

[0026] FIGS. 6A, 6C, and 6E depict cross-sectional views of a GmAPD PDA pixel in various stages of fabrication, in accordance with the illustrative embodiment.

[0027] FIGS. 6B, 6D, and 6F depict top views of a GmAPD PDA pixel in various stages of fabrication, in accordance with the illustrative embodiment.

[0028] FIG. 7 depicts a top view of a GmAPD FPA pixel at a stage of fabrication, and showing an alternative layout of a limit resistor.

DETAILED DESCRIPTION

[0029] Embodiments of the invention provide a GmAPD FPA having increased tolerance optical overstress. For the sake of clarity, the embodiments of the invention are depicted and described at the pixel level. Each GmAPD FPA pixel includes a GmAPD pixel and a unit cell of an ROIC. There is a 1:1 relationship between GmAPDs and unit cells of the ROIC. Each unit cell of the ROIC provides a digital readout of the avalanche events that occur within the associated GmAPD. It is within the capabilities of those skilled in the art to appropriately scale to the level of a GmAPD FPA.

[0030] FIG. 3A depicts a circuit model of GmAPD FPA pixel 300A, in accordance with an embodiment of the present invention. GmAPD FPA pixel 300A differs from prior-art GmAPD FPA pixel 100 in that the former includes limit resistor 316A. In this embodiment, limit resistor 316A is monolithically integrated into GmAPD 302 (as opposed to the ROIC unit cell). In an embodiment of a GmAPD FPA based on FIG. 3A, which will include a 2D array of pixels like that depicted in FIG. 3A, each such pixel will include limit resistor 316A that has been monolithically integrated within the GmAPD of the pixel.

[0031] In some embodiments in which limit resistor 316A is monolithically integrated in GmAPD 302, the limit resistor is a thin-film resistor that is patterned on the GmAPD from, for example, standard-production, high-resistivity NiCr and TaN thin films.

[0032] FIG. 3B depicts a circuit model of GmAPD FPA pixel 300B, in accordance with an embodiment of the present invention. Like GmAPD FPA pixel 300A, GmAPD FPA pixel 300B differs from prior-art GmAPD FPA pixel 100 in that pixel 300B includes limit resistor 316B. In this embodiment, however, limit resistor 316B is monolithically integrated into ROIC unit cell 306.

[0033] Thus, in both embodiments depicted, the limit resistor is: (a) located in the circuit between the GmAPD and the ROIC unit cell, and (b) monolithically integrated into the GmAPD FPA pixel.

[0034] FIGS. 4A and 4B depict a comparison of the electrical behavior of a prior-art GmAPD FPA pixel (see FIG. 1) and a GmAPD FPA pixel in accordance with the present teachings (e.g., see FIGS. 3A, 3B).

[0035] With reference to FIGS. 1, 3A, 3b, and 4A, upon closing of switch S at time to, the voltage V in a GmAPD FPA pixel in accordance with the present invention (dashed line) drops more slowly than a GmAPD FPA pixel of the prior art (solid line). As depicted in FIG. 4B, current I still flows to the ROIC, but the total charge injected into the ROIC (which is the area under each curve in FIG. 4B) is discharged at a more gradual pace, thereby reducing the peak current magnitude as compared to the prior art.

[0036] Because sense transistor 114 in the ROIC unit cell is a voltage threshold detector, the smaller current amplitudes generated in embodiments of the invention will not degrade the circuit's ability to detect avalanches. The primary performance trade-off to be considered is avoiding degradation of the FPA timing jitter performance associated with an increase in avalanche RC time constants induced by the presence of limit resistor 316A or 316B. This places an upper limit on useful values of the limit resistor of about 100 kOhms. The lower limit of resistance of the limit resistor, which is about 1 kOhm, is determined by the minimum value that reduces the peak current to an acceptable value.

[0037] Since the existing series resistance between the GmAPD anode and the ROIC input in an APD FPA is dominated by the contact resistance of the APD anode contact, which is about 100 ohms, the aforementioned resistance range of the limit resistor (i.e., about 1 kOhm to about 100 kOhms) is expected to yield, at minimum, a factor-of-ten improvement in optical-overload tolerance. At the same time, keeping the resistance in the aforementioned range will, as previously noted, avoid unacceptable levels of degradation in timing jitter performance.

[0038] As previously noted, in embodiments of the invention, the limit resistor is monolithically integrated into the GmAPD FPA pixel. A process for monolithically integrating the limit resistor into a GmAPD, such as to form GmAPD 301 (FIG. 3A), is disclosed in FIGS. 5 and 6A-6F and the accompanying description.

[0039] The fabrication operations germane to embodiments of the invention take place after epitaxial growth of the various layers (e.g., absorption layer, charge control layer, cap layer, etc.) composing an APD (hereinafter referred to in the disclosure and claims as the “APD device layers”), but before diffusing a dopant into the cap layer to form the active region of the APD. Conventional techniques are used for metal deposition, insulator deposition, patterning, etc.

[0040] Referring now to FIG. 5, in operation S501 of method 500, a layer providing electrical passivation (and also electrical insulation), referred to herein and the appended claims as a “passivation layer,” is deposited on the APD device layers. The passivation layer comprises, for example and without limitation, SiN.sub.x, Al.sub.2O.sub.3, and SiO.sub.2. In operation S502, an opening is patterned in the passivation layer and dopant is diffused through the opening, via standard techniques (photolithography/reactive ion etching, wet-etching, ion milling, sputtering, laser-assisted etching, etc.). It is within the capabilities of those skilled in the art to determine the size of the opening. If the material being doped is n-type semiconductor, the dopant will be a p-type dopant, such as zinc, cadmium, beryllium, and carbon. If the semiconductor layer is a p-type material, then the dopant will be an n-type dopant, such as sulfur or silicon. It is within the capabilities of those skilled in the art to appropriately dope the cap layer to provide an active region in the APD.

[0041] In operation S503, an n- or p-contact metal (dependent on device type) is deposited on a portion of the active region. As needed, additional “passivation” material is deposited to fill what remains of the opening formed in the passivation layer.

[0042] FIGS. 6A and 6B depict respective cross-sectional and top views of a nascent GmAPD at the completion of operation S503. At this point in the fabrication, the GmAPD includes substrate 620, APD device layers 622, active region 624, passivation layer 626, and contact 628.

[0043] In operation S504, a layer of metal, such as, without limitation, high resistivity NiCr or TaN, is deposited between the contact (i.e., contact 628) and a region in which a bond pad will be deposited. This layer of metal can be deposited, for example, via electron beam evaporation, or sputtering, and be patterned into a desired configuration using techniques known in the art. This layer of metal serves as the limit resistor.

[0044] In operation S505, additional metal is deposited in a location at which a bond pad is desired. This metal will partially (or wholly) overlap the metal serving as the limit resistor. The bond pad comprises, for example and without limitation, gold, aluminum, copper, and alloys thereof.

[0045] FIGS. 6C and 6D depict respective cross-sectional and top views of the nascent GmAPD at the completion of operation S505. At this stage of completion, the GmAPD includes limit resistor 630 and bond pad 632, in addition to substrate 620, APD device layers 622, active region 624, passivation layer 626, and contact 628.

[0046] In operation S506, a layer of electrical insulation is deposited over the APD. Materials suitable for use as the layer of electrical insulation include, for example and without limitation, BCB, SiO.sub.2, SiN.sub.x, and Al.sub.2O.sub.3. An opening is then formed around the bond pad to enable electrical contact between the GmAPD and the ROIC.

[0047] FIGS. 6E and 6F depict respective cross-sectional and top views of the GmAPD at the completion of operation S506, at which point the GmAPD, as modified to include the limit resistor, is complete. The GmAPD includes insulation layer 634, in addition to substrate 620, APD device layers 622, active region 624, passivation layer 626, and contact 628, limit resistor 630 and bond pad 632. Also depicted is electrical connection 636 from bond pad 632 to the ROIC.

[0048] FIG. 7 depicts resistor 730 having a serpentine shape, which is an alternative embodiment of limit resistor 630. Limit resistor 730 includes a greater number of resistor “squares” between the active region (i.e., active region 624) and bond pad 632, and thus presents greater electrical resistance. The excess of space available on the surface of the PDA is what enables the incorporation of additional resistor squares into the limit resistor. This approach, whereby additional resistor squares are added resulting in a serpentine (or other) shape, enables tuning the resistance of the limit resistor.

[0049] Monolithically integrating a limit resistor into an ROIC will necessarily proceed along a somewhat different path as a consequence of the structural differences between a GmAPD and a ROIC. In light of the present teachings, those skilled in the art will be able to adapt ROIC fabrication procedures to incorporate a limit resistor.

[0050] It is to be understood that the disclosure teaches just one example of the illustrative embodiment and that many variations of the invention can easily be devised by those skilled in the art after reading this disclosure and that the scope of the present invention is to be determined by the following claims.