Methods and circuits for decision-feedback equalization using compensated decision regions

Abstract

A decision-feedback equalizer (DFE) samples an input signal with respect to a gamut of p reference-voltage levels to place the symbol represented by the input signal within a voltage region. The DFE derives a set of tentative decisions for the voltage region, the set excluding at least one of the possible values for the symbol under consideration. A feedback stage then selects a final decision from among the tentative decisions.

Claims

1. A decision-feedback equalizer (DFE) comprising: an input node to receive an input signal expressing a series of symbols, each of the symbols representing one of a set of possible symbol values; a first open-loop stage coupled to the input node to receive the series of symbols, the first open-loop stage to compare each symbol in the series of symbols with a set of reference-voltage levels to identify a voltage region; a second open-loop stage coupled to the first open-loop stage to derive from the voltage region a set of tentative decisions representing a subset of the set of possible symbol values; and a feedback stage coupled to the second open-loop stage to select one of the set of tentative decisions as a final decision responsive to a prior final decision; wherein the first open-loop stage selects the set of reference-voltage levels from a gamut of reference-voltage levels responsive to a level of each symbol in the series of symbols; wherein the comparing of each symbol relative to the set of reference-voltage levels successively compares the symbol to each reference-voltage level in the set of reference-voltage levels; and wherein the first open-loop stage performs a binary search for the voltage region by the successive comparison of the symbol to each reference-voltage level in the set of reference-voltage levels.

2. The DFE of claim 1, wherein the first open-loop stage, the second open-loop stage, and the feedback stage are of a first DFE slice, the DFE further comprising additional DFE slices each coupled to the input node to receive the series of symbols and produce a respective series of final decisions.

3. The DFE of claim 2, wherein the feedback stage of each DFE slice receives the prior final decision from another of the DFE slices.

4. The DFE of claim 2, further comprising a reference-level generator to generate a gamut of reference-voltage levels, including the set of reference-voltage levels, and apply the gamut of reference-voltage levels to the first open-loop stage of each of the DFE slices.

5. The DFE of claim 1, further comprising a look-up table, coupled to the second open-loop stage, to store a mapping between the voltage regions and subsets of the set of symbol values.

6. The DFE of claim 1, the second open-loop stage including a substage that further selects the set of tentative decisions from a prior set of tentative decisions.

7. A decision-feedback equalizer (DFE) comprising: an input node to receive an input signal expressing a series of symbols, each of the symbols representing one of a set of possible symbol values; a reference-level generator to provide a gamut of reference-voltage levels; and an open-loop stage coupled to the input node to receive the series of symbols, the open-loop stage to compare a present level of each symbol in the series of symbols to a subset of the gamut of reference-voltage levels to identify a voltage region for the symbol; wherein the open-loop stage selects the subset of reference-voltage levels responsive to the present level.

8. The DFE of claim 7, wherein comparing the present level of each symbol with the subset of reference-voltage levels successively compares the present level to each reference-voltage level in the subset of the reference-voltage levels.

9. The DFE of claim 8, wherein the open-loop stage performs a binary search for the voltage region by the successive comparing.

10. The DFE of claim 9, wherein the open-loop stage is of a first DFE slice, the DFE further comprising additional DFE slices each coupled to the input node to receive the series of symbols and sample the received series of symbols at respective sample timings.

11. The DFE of claim 10, wherein each of the DFE slices provides a final decision to another of the DFE slices.

12. The DFE of claim 7, further comprising: a second open-loop stage coupled to the first-mentioned open-loop stage to derive from the identified voltage region a set of tentative decisions representing a subset of the possible symbol values.

13. The DFE of claim 12, further comprising: a feedback stage coupled to the second open-loop stage to select one of the tentative decisions as a final decision responsive to a prior final decision.

14. The DFE of claim 12, wherein the second open-loop stage further derives the set of tentative decisions from a prior set of tentative decisions.

15. A method of interpreting an input signal expressing a series of symbols, each of the symbols representing one of a set of possible symbol values, the method comprising: performing, for each symbol, a binary search for a voltage region corresponding to the symbol, the binary search comprising comparing each symbol in the series of symbols to a set of reference-voltage levels selected from a gamut of reference-voltage levels, and wherein the comparing of each symbol performs the binary search for the voltage region by sampling the symbol relative to each reference-voltage level in the set of reference-voltage levels; deriving, from the voltage region, a set of tentative decisions representing a subset of the possible symbol values; and selecting one of the tentative decisions as a final decision responsive to a prior final decision.

16. The method of claim 15, wherein the set of reference-voltage levels is a subset of the gamut of reference-voltage levels, the method further comprising selecting the subset of the gamut of reference-voltage levels responsive to the comparing.

17. The method of claim 15, wherein deriving the set of tentative decisions considers a prior set of tentative decisions.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The detailed description is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

(2) FIG. 1 depicts a PAM-4 DFE 100 that receives an input signal x (lower left) distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes (voltages) to convey two binary bits of data per symbol.

(3) FIG. 2 includes an eye diagram 200 and table 205 illustrating how ISI calibration circuitry 117 of FIG. 1 calculates ISI-adjusted reference levels V.sub.p-1:V.sub.0.

(4) FIG. 3 depicts an eye diagram 300 in which ISI-adjusted reference-voltage levels V.sub.p-1:V.sub.0 of table 205 of FIG. 2 partition the entire range of received signal levels thirteen decision regions R.sub.12:R.sub.0.

(5) FIG. 4 depicts a tentative-decision look-up table (LUT) 400 relating voltage regions R.sub.12:R.sub.0 for a current symbol value d.sub.n(k) to tentative symbol values given a preceding symbol value d.sub.n-1 (k).

(6) FIG. 5 details one slice 500 of open-loop equalizer 105 of FIG. 1, including first open-loop stage 120(0) and second open-loop stage 125(0).

(7) FIG. 6 is a decision tree 600 illustrating the binary search performed by first open-loop stage 120(0) to identify voltage regions R.sub.12:R.sub.0 and the sets of tentative decisions TD.sub.12:TD.sub.0 associated with each region shown in FIG. 3.

(8) FIG. 7 depicts a tentative-decision LUT 700 similar to LUT of FIG. 4 but including a mapping of partial region decisions r.sub.0, r.sub.1, r.sub.2, and r.sub.3 to voltage regions R.sub.12:R.sub.0 and tentative-decision sets TD.sub.12:TD.sub.0.

(9) FIG. 8A depicts a second open-loop stage 800 in accordance with another embodiment.

(10) FIG. 8B illustrates how sub-stage 810 of FIG. 8A shares sets of tentative pre-decisions TD.sub.q-1:TD.sub.0 from sub-stage 805 to produce refined sets of tentative pre-decisions RTD.sub.q-1:RTD.sub.0.

DETAILED DESCRIPTION

(11) FIG. 1 depicts a PAM-4 DFE 100 that receives an input signal x (lower left) distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes (voltages) to convey two binary bits of data per symbol. DFE 100 includes N+1 DFE slices—collectively a “lane”—each operating at a data rate of 1/(N+1) times that of input signal x with a timing offset of one symbol time of input signal x relative to the neighboring DFE slice. The N+1 DFE slices thus process input signal x in parallel to relax timing constraints on DFE 100. In general, input signal x.sub.n(k) represents the sample of the nth DFE slice for n=0:N at discrete time k, and output signal d.sub.n(k) represent the final decision for the sample value of the nth DFE slice for n=0:N at discrete time k. DFE slice 0, for example, samples a symbol of input signal x.sub.0(k) with respect to a gamut of p reference-voltage levels V[p−1:0] to place the symbol within a voltage region R, makes a set of tentative decisions TD indicating the possible symbol values represented by the voltage region R, and considers the value of a prior symbol d.sub.N(k−1) from DFE slice N to narrow the tentative decisions down to a final decision d.sub.0(k). The number of DFE slices is thirty-two (N=31) in one embodiment.

(12) DFE 100 includes an open-loop (feed-forward) equalizer 105 and a closed-loop (feedback) decision stage 110, each of which is divided into N+1 slices. A reference block 115 includes ISI calibration circuitry 117 that develops p reference-voltage levels Vp−1:V0 and pre-decision computation circuitry 119 that produces q sets of tentative pre-decisions TDq−1:TD0 based on the voltage levels. As detailed below, each set of tentative pre-decisions identifies fewer than four tentative values of a sampled symbol given its measured voltage region. Decision stage 110 thus selects from among fewer than the four potential values of a PAM-4 system for each incoming symbol. To save power and area, the reference signals from block 115 are shared by all N DFE slices in this embodiment.

(13) Open-loop equalizer 105 includes a first open-loop stage 120 and a second open-loop stage 125, each of which is divided into N+1 slices in service of like-referenced ones of DFE slices 0 to N. Considering DFE slice 0, first open-loop stage 120(0) samples each symbol in series symbols x.sub.0(k) relative to all or a subset of reference-voltage levels V.sub.p-1:V.sub.0 to locate the voltage level for the symbol within one of a set of q voltage regions R.sub.q-1:R.sub.0. Second open-loop stage 125(0) selects one of pre-decision sets TD.sub.q-1:TD.sub.0 using the identified voltage region.

(14) Tentative-decision sets TD.sub.q-1:TD.sub.0, also referred to as “pre-decision sets,” represent the symbol value or values that are possible for a given voltage region, with each set excluding at least one of the four PAM-4 values. Each tentative-decision set also relates the possible value or values to the value expressed by the preceding symbol. Decision stage 110(0) selects a final decision d.sub.0(k) from among the tentative subset of possible values based on the resolved value of prior decision d.sub.N(k−1) from the DFE slice N charged with resolving the value of the preceding symbol in overall input signal x. Second open-loop stage 125(0) simplifies the process of making the final decision by reducing the number of possibilities to a tentative subset and thus eases the timing closure of the closed-loop decision feedback loop of decision stage 110(0).

(15) FIG. 2 includes an eye diagram 200 and table 205 illustrating how ISI calibration circuitry 117 of FIG. 1 calculates ISI-adjusted reference levels V.sub.p-1:V.sub.0. PAM-4 DFE 100 communicates four symbol values s.sub.3:s.sub.0. In particular, symbol value s.sub.0 is the decision symbol for PAM-4 transmit level (−3); symbol value s.sub.1 is the decision symbol for PAM-4 transmit level (−1); symbol s.sub.2 is the decision symbol for PAM-4 transmit level (1); and symbol value s.sub.3 is the decision symbol for PAM-4 transmit level (3). These four PAM-4 signal levels are distinguished using three nominal reference-voltage levels. Reference voltage level V.sub.b (bottom level) represents the decision boundary between symbol values s.sub.0 and s.sub.1; voltage level V.sub.c (center level) the decision boundary between symbol values s.sub.1 and s.sub.2; and voltage level V.sub.t (top level) the decision boundary between symbol values s.sub.2 and s.sub.3.

(16) Nominal reference levels V.sub.b, V.sub.c, and V.sub.t are adjusted using DFE taps to generate 3×2.sup.2L ISI-adjusted reference levels, where L is the number of DFE taps. DFE 100 of FIG. 1 has one tap, calling for the three sets of four (twelve) reference-voltage levels provided in the following equations 1-3.

(17) $\begin{array}{cc}{\hat{V}}_{t,m\left(0\right),\mathrm{.Math.},m\left(L-1\right)}=V_t+\underset{l=0}{\overset{L-1}{.Math.}}{c}_l\left[m\left(l\right)\right]& \left(1\right)\\ {\hat{V}}_{c,m\left(0\right),\mathrm{.Math.},m\left(L-1\right)}=V_c+\underset{l=0}{\overset{L-1}{.Math.}}{c}_l\left[m\left(l\right)\right]& \left(2\right)\\ {\hat{V}}_{b,m\left(0\right),\mathrm{.Math.},m\left(L-1\right)}=V_b+\underset{l=0}{\overset{L-1}{.Math.}}{c}_l\left[m\left(l\right)\right]& \left(3\right)\end{array}$

(18) Vector c.sub.l=[−α.sub.l, −β.sub.l, β.sub.l, α.sub.l], for l=0:L−1 represents the DFE taps for the cancellation of ISI from the lth post-cursors, and m(l)ϵ{0, 1, 2, 3} is an index for selecting the m(l)th entry in vector c.sub.l; α.sub.l is the DFE tap to be added to the received signal (or subtracted from the reference level) for ISI compensation when the lth post-cursor decision is s.sub.3, for l=0:L−1; and β.sub.l is the DFE tap to be added to the received signal for ISI compensation when the lth post-cursor decision is s.sub.2, for l=0:L−1.

(19) The ISI-adjusted reference levels are either static or quasi-static because the DFE taps and reference levels are either fixed after initial calibration or adapted periodically in operation. The computation of the ISI-adjusted reference levels can be implemented either as firmware or low-speed logic for reduced power. The ISI-adjusted reference levels are shared by the parallel DFE slices in a lane.

(20) Given a preceding symbol decision s.sub.0, top reference level Vt is adjusted by subtracting the corresponding DFE tap α.sub.0. The ISI-adjusted reference level Vt-α.sub.0 replaces V.sub.t as the decision boundary between symbols s.sub.2 and s.sub.3. Offsets for top reference-voltage level Vt are similarly calculated for the three remaining potential symbol decisions, as are the four offsets for each of center and bottom reference-voltage levels V.sub.c and V.sub.b. Without loss of generality, table 205 lists the ISI-adjusted reference levels for a one-tap PAM-4 DFE that cancels ISI from the first post-cursor symbol, previous decision d.sub.n-1(k). Calculating tap values is well known to those of skill in the art so a detailed treatment is omitted.

(21) FIG. 3 depicts an eye diagram 300 in which ISI-adjusted reference-voltage levels V.sub.p-1:V.sub.0 of table 205 of FIG. 2 partition the entire range of received signal levels into thirteen ISI-compensated decision regions R.sub.12:R.sub.0. There are twelve reference-voltage levels and thirteen decision regions in this example but more of fewer can be used for PAM-4 or other modulation schemes. In one embodiment selecting a value of p between eight and the lessor of sixteen or 3×2.sup.2L, where L is the number of DFE taps, tends to optimize for power and area.

(22) The highest and lowest regions R.sub.12 and R.sub.0 are dispositive as to the symbol value they represent. Region R.sub.12 is above all reference-voltage levels V.sub.11:V.sub.0 and thus represents the highest value s.sub.3. Region R.sub.0 is below all reference-voltage levels V.sub.11:V.sub.0 and thus represents the lowest value s.sub.0. The remaining regions are not dispositive but do exclude at least one of the four possible symbol values. Voltage region R.sub.8, for example, is above all possible variants of bottom reference voltage V.sub.b (i.e. V.sub.1 to V.sub.4) and thus cannot represent the lowest symbol value s.sub.0 but can represent any of the remaining symbol values s.sub.1, s.sub.2, and s.sub.3. Pre-decision computation block 119 uses the ISI-adjusted voltages V.sub.0 to V.sub.11 in this way to populate a look-up table (LUT) relating each voltage region from R.sub.0 to R.sub.12 to a corresponding set of possible symbol values and makes these sets available to open-loop stage 125. Second open-loop stage 125 “looks up” the possible values for each region identified by first open-loop stage 120 to reduce the four possible PAM-4 symbol values to a tentative subset, and thus reduces the computational complexity of selecting a final value for each symbol. For example, second open-loop stage 125(0) can use voltage region R.sub.8 from first open-loop stage 120(0) to select tentative-decision set TD.sub.8 for passing to decision stage 110(0), and thus allow stage 110(0) to select final decision d.sub.0(k) from among symbol values s.sub.1, s.sub.2, and s.sub.3.

(23) FIG. 4 depicts a tentative-decision look-up table (LUT) 400 relating voltage regions R.sub.12:R.sub.0 for a current symbol value d.sub.n(k) to tentative symbol values given a preceding symbol value d.sub.n-1(k). For each identified voltage region R second open-loop stage 125(0) passes decision stage 110(0) a corresponding tentative decision set TD that identifies a set of tentative decisions in relation to the prior symbol value. Returning to the example of voltage region R.sub.8, LUT 400 indicates that this level corresponds to tentative-decision set TD.sub.8, which represents a current value s.sub.1 if the preceding symbol was s.sub.3, a current value s.sub.2 if the preceding values was s.sub.1 or s.sub.2, and a current value s.sub.3 if the preceding value was also s.sub.0. Each set of tentative pre-decisions TD reduces the number of possible symbol values, which eases the timing closure of decision stage 110. LUT 400 can be static or quasi-static and can be implemented using either firmware or low-speed logic. LUT 400 can be shared by all parallel DFE slices in a lane to save area and power.

(24) FIG. 5 details one slice 500 of open-loop equalizer 105 of FIG. 1, including first open-loop stage 120(0) and second open-loop stage 125(0). The remaining slices are the same or similar.

(25) First open-loop stage 120(0) includes four comparators 505, 510, 515, and 520 that issue respective partial region decisions r.sub.0, r.sub.1, r.sub.2, and r.sub.3 responsive to a subset of the gamut of reference-voltage levels V.sub.11:V.sub.0. Second open-loop stage 125(0) decodes each combination of partial region decisions r.sub.3:r.sub.0 to select among tentative decision sets TD.sub.12:TD.sub.0 for a given one of regions R.sub.12:R.sub.0, the sets noted for example in LUT 400 of FIG. 4.

(26) From left to right, comparator 505 compares the level of present symbol x.sub.0(k) with the middle reference-voltage level V.sub.5, issuing logic one (zero) value for partial region decision r.sub.0 if the level of the present symbol is above (below) level V.sub.5. Partial region decision r.sub.0 is fed to second stage 125(0) and to a multiplexer 525 that compares present symbol x.sub.0(k) with either reference-voltage level V.sub.2 or V.sub.8 depending upon the value of partial region decision r.sub.0 to issue a second partial region decision r.sub.1. Two more multiplexers 530 and 535 continue this binary search against the remaining reference-voltage levels until the set of partial region decision r.sub.3:r.sub.0 indicate one of regions R.sub.12:R.sub.0. Second stage 125(0) then produces the corresponding set of tentative decisions from among sets TD.sub.12:TD.sub.0. ISI is thus indirectly compensated for by locating each symbol's amplitude within an ISI-compensated region.

(27) FIG. 6 is a decision tree 600 illustrating the binary search performed by first open-loop stage 120(0) to identify voltage regions R.sub.12:R.sub.0 and the sets of tentative decisions TD.sub.12:TD.sub.0 associated with each region. Each region is shown with four pre-symbol possibilities, one for each symbol type, and the corresponding tentative decisions. As noted previously, for example, region R.sub.8 represents a current value s.sub.1 if the preceding symbol was s.sub.3, a current value s.sub.2 if the preceding values was s.sub.1 or s.sub.2, and a current value s.sub.3 if the preceding value was s.sub.0. Temporary decision TD.sub.8 passes a value indicative of these relationships to allow decision stage 110 to simply select the final decision d.sub.n(k) based on the final decision d.sub.n-1(k) for the preceding symbol.

(28) FIG. 7 depicts a tentative-decision LUT 700 similar to LUT of FIG. 4 but including a mapping of partial region decisions r.sub.0, r.sub.1, r.sub.2, and r.sub.3 to voltage regions R.sub.12:R.sub.0 and tentative-decision sets TD.sub.12:TD.sub.0.

(29) FIG. 8A depicts a second open-loop stage 800 that can be used in place of open-loop stage 125 of FIG. 1 to produce further refined sets of tentative pre-decisions RTD.sub.q-1:RTD.sub.0. Second open-loop stage 800 includes a first open-loop sub-stage 805 and a second open-loop substage 810, each of which is divided into N+1 slices in service of like-references ones of DFE slices 0 to N in the manner detailed in connection with FIG. 1.

(30) Sub-stage 805 produces the same sets of tentative pre-decisions TD.sub.q-1:TD.sub.0 detailed previously, each set representing the symbol value or values that are possible for a given voltage region. Sub-stage 810 then considers the tentative pre-decisions from neighboring slices, and thus the values of prior symbols, to further reduce the size of one or more sets of tentative pre-decisions TD.sub.q-1:TD.sub.0, and thus produce refined sets of tentative pre-decisions RTD.sub.q-1:RTD.sub.0. Reducing the number of potential symbol values further eases timing closure for decision feedback of e.g. stage 110.

(31) FIG. 8B illustrates how slices of sub-stage 810 of FIG. 8A share sets of tentative pre-decisions TD.sub.q-1:TD.sub.0 to produce refined sets of tentative pre-decisions RTD.sub.q-1:RTD.sub.0. A delay element 815 delays pre-decision TD.sub.N(k) by one parallel clock cycle to apply delayed pre-decision TD.sub.N(k−1) to sub-stage 810(0). Each slice of sub-stage 810 receives sets of tentative pre-decisions from an adjacent slice that represent potential values of prior symbol d.sub.n-1(k), and that can be used to further reduce the number of tentative symbol values. With reference to FIG. 7, for example, a slice of sub-stage 810 receiving tentative pre-decisions TD.sub.4 for the present symbol and prior tentative pre-decisions TD.sub.1 from an adjacent slice can pass on a refined set of tentative decisions indicating that the current symbol is either s.sub.1 or s.sub.2. The value so otherwise associated with tentative decision TD.sub.4 is eliminated from consideration because the prior symbol, while not determined, is known not to have a value of s.sub.3.

(32) Another embodiment splits the amplitude range illustrated in FIG. 3 into e.g. four zones, one for each of respective symbol values s.sub.3:s.sub.0 for processing in parallel by four instances of the two open-loop stages. Each first open-loop stage considers a reduced number of sub-regions and each second stage requires a smaller LUT. This embodiment may reduce the latency of the forward data path, particularly for large numbers of DFE taps and sub-regions.

(33) While the subject matter has been described in connection with specific embodiments, other embodiments are also envisioned. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Only those claims specifically reciting “means for” or “step for” should be construed in the manner required under the sixth paragraph of 35 U.S.C. § 112.