METHOD OF OPERATING A FLYBACK CONVERTER WITH ACTIVE CLAMP, CORRESPONDING CONTROL CIRCUIT AND FLYBACK CONVERTER

Abstract

The present disclosure relates to solutions for operating a flyback converter comprising an active clamp. The flyback converter comprises two input terminals and two output terminals. A first electronic switch and the primary winding of a transformer are connected in series between the input terminals. An active clamp circuit is connected in parallel with the primary winding. The active clamp circuit comprises a series connection of a clamp capacitor and a second electronic switch. A third electronic switch and the secondary winding of the transformer are connected in series between the two output terminals. In particular, the present disclosure relates to solutions for switching the first, second and third electronic switch in order to achieve a zero-voltage switching of the first electronic switch.

Claims

1. A method of operating a flyback converter, comprising: during a first time interval of a switching cycle, closing a first electronic switch and opening second and third electronic switches, the first electronic switch being connected with a primary winding of a transformer between first and second input terminals for receiving an input voltage, the first electronic switch and primary winding being coupled to each other at a phase node and a capacitance is associated with the phase node, the second electronic switch and a clamp capacitor being connected to each other as an active clamp circuit connected in parallel with the primary winding, the third electronic switch and a secondary winding of the transformer being connected between first and second output terminals for providing an output voltage, wherein closing the first electronic switch during the first time interval electrically couples the primary winding to said input voltage and causes a current flowing through said primary winding to increase, thereby storing energy in said transformer; during a subsequent second time interval of the switching cycle, opening said first switch, and keeping open said second and third electronic switches, whereby the current flowing through said primary winding charges said capacitance associated with said phase node; during a subsequent third time interval of the switching cycle, keeping open said first electronic switch and closing both said second and third electronic switches, which electrically couples said clamp capacitor with said primary winding and the current flowing through said primary winding charges also said clamp capacitor, wherein said third time interval ends when said current flowing through said primary winding reaches zero; during a subsequent fourth time interval of the switching cycle, keeping open said first electronic switch, keeping closed said third electronic switch, and opening said second electronic switch, whereby the current flowing through said primary winding is zero and the energy stored in said transformer is released via a current flowing through said secondary winding; and during a subsequent fifth time interval of the switching cycle, keeping open said first electronic switch, closing said second electronic switch, and keeping closed said third electronic switch, whereby said clamp capacitor is electrically coupled in parallel with said primary winding, whereby said clamp capacitor and said leakage inductance form a resonant circuit having a given resonance period, and wherein said fifth time interval ends after one or more half-periods of said resonance period.

2. The method of claim 1, wherein the fourth time interval ends when the current flowing through the secondary winding reaches zero.

3. The method of claim 1, wherein the second electronic switch comprises a diode.

4. The method of claim 1, wherein the third electronic switch comprises a diode.

5. The method of claim 1, further comprising: determining a reference value for the current flowing through the primary winding during a sixth time interval, the reference value being indicative of the energy to discharge the capacitance; and ending the sixth time interval when the current flowing through the primary winding exceeds the reference value.

6. The method of claim 1, further comprising: determining a duration for a sixth time interval as a function of duty cycles of the flyback converter, the duty cycle corresponding to a ratio between a duration of the first time interval and a duration of the switching cycle; and ending the sixth time interval after the duration for the sixth time interval.

7. The method according to claim 1, further comprising: obtaining a maximum value for the output voltage and a minimum value for the input voltage; determining a minimum clamp time as a function of the maximum value for the output voltage and the minimum value for the input voltage; and selecting a capacitance value of the clamp capacitor, a half-period of the resonance period of the clamp capacitor and the leakage inductance being shorter than the minimum clamp time.

8. A control circuit for a flyback converter that includes first and second input terminals for receiving an input voltage, first and second output terminals for providing an output voltage, a transformer having primary and secondary windings and a leakage inductance, a first electronic switch coupled with the primary winding between the first and second input terminals, a phase node between the first electronic switch and the primary winding, a capacitance associated with the phase node, an active clamp connected to the primary winding and including a connection of a clamp capacitor and a second electronic switch, and a third electronic switch electrically coupled with the secondary winding between the first and second output terminals, the control circuit being configured to: during a first time interval of a switching cycle, close the first electronic switch and open the second and third electronic switches, wherein the closed first electronic switch during the first time interval electrically couples the primary winding to the input voltage and causes a current flowing through the primary winding to increase, thereby storing energy in the transformer; during a subsequent second time interval of the switching cycle, open the first switch, and keep open the second and third electronic switches, whereby the current flowing through the primary winding charges the capacitance associated with the phase node; during a subsequent third time interval of the switching cycle, keep open the first electronic switch and close both of the second and third electronic switches, which electrically couples the clamp capacitor with the primary winding and the current flowing through the primary winding charges also the clamp capacitor, wherein the third time interval ends when the current flowing through the primary winding reaches zero; during a subsequent fourth time interval of the switching cycle, keep open the first electronic switch, keep closed said third electronic switch, and open the second electronic switch, whereby the current flowing through said primary winding is zero and the energy stored in the transformer is released via a current flowing through the secondary winding; and during a subsequent fifth time interval of the switching cycle, keep open the first electronic switch, close the second electronic switch, and keep closed the third electronic switch, whereby the clamp capacitor is electrically coupled in parallel with the primary winding, whereby the clamp capacitor and the leakage inductance form a resonant circuit having a given resonance period, and wherein the fifth time interval ends after one or more half-periods of the resonance period.

9. The control circuit of claim 8, wherein the fourth time interval ends when the current flowing through the secondary winding reaches zero.

10. The control circuit of claim 8, wherein the second electronic switch comprises a diode.

11. The control circuit of claim 8, wherein the third electronic switch comprises a diode.

12. The control circuit of claim 8, wherein the control circuit is configured to: detect when the current flowing through the secondary winding reaches zero; and end the fourth time interval in response to detecting that the current flowing through the secondary winding has reached zero.

13. A flyback converter, comprising: first and second input terminals for receiving an input voltage; first and second output terminals for providing an output voltage; a transformer including a primary winding and a secondary winding, wherein a leakage inductance and a magnetizing inductance are associated with said transformer; a first electronic switch connected with the primary winding between said first and second input terminals, wherein said first electronic switch and said primary winding are connected to each other by a phase node, wherein a capacitance is associated with said phase node; an active clamp circuit connected with said primary winding, said active clamp circuit a clamp capacitor and a second electronic switch connected in series; a third electronic switch connected with said secondary winding between said first and said second output terminals; and a control circuit configured to: during a first time interval of a switching cycle, close the first electronic switch and open the second and third electronic switches, wherein the closed first electronic switch during the first time interval electrically couples the primary winding to the input voltage and causes a current flowing through the primary winding to increase, thereby storing energy in the transformer; during a subsequent second time interval of the switching cycle, open the first switch, and keep open the second and third electronic switches, whereby the current flowing through the primary winding charges the capacitance associated with the phase node; during a subsequent third time interval of the switching cycle, keep open the first electronic switch and close both of the second and third electronic switches, which electrically couples the clamp capacitor with the primary winding and the current flowing through the primary winding charges also the clamp capacitor, wherein the third time interval ends when the current flowing through the primary winding reaches zero; during a subsequent fourth time interval of the switching cycle, keep open the first electronic switch, keep closed said third electronic switch, and open the second electronic switch, whereby the current flowing through said primary winding is zero and the energy stored in the transformer is released via a current flowing through the secondary winding; and during a subsequent fifth time interval of the switching cycle, keep open the first electronic switch, close the second electronic switch, and keep closed the third electronic switch, whereby the clamp capacitor is electrically coupled in parallel with the primary winding, whereby the clamp capacitor and the leakage inductance form a resonant circuit having a given resonance period, and wherein the fifth time interval ends after one or more half-periods of the resonance period.

14. The flyback converter of claim 13, wherein the fourth time interval ends when the current flowing through the secondary winding reaches zero.

15. The flyback converter of claim 13, wherein: the first electronic switch is a n-channel FET; the second electronic switch is a n-channel FET; and the third electronic switch is a n-channel FET or a diode.

16. The flyback converter of claim 13, wherein the second electronic switch comprises a diode.

17. The flyback converter of claim 13, wherein the third electronic switch comprises a diode.

18. The flyback converter of claim 13, wherein the control circuit is configured to: determine a reference value for the current flowing through the primary winding during a sixth time interval, the reference value being indicative of the energy to discharge the capacitance; and end the sixth time interval when the current flowing through the primary winding exceeds the reference value.

19. The flyback converter according to claim 13, wherein the control circuit is configured to: end a sixth time interval after a duration that is a function of a duty cycle of the flyback converter, the duty cycle corresponding to a ratio between a duration of the first time interval and a duration of the switching cycle.

20. The flyback converter according to claim 13, wherein the control circuit is configured to: detect when the current flowing through the secondary winding reaches zero; and end the fourth time interval in response to detecting that the current flowing through the secondary winding has reached zero.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0035] The embodiments of the present disclosure will now be described with reference to the annexed plates of drawings, which are provided purely to way of non-limiting example and in which:

[0036] FIG. 1 shows an example of a flyback converter comprising an active clamp;

[0037] FIGS. 2A to 2D show an embodiment of the control of the flyback converter of FIG. 1;

[0038] FIGS. 3A to 3E, and 4 show an embodiment of the control of the flyback converter of FIG. 8;

[0039] FIGS. 5A, 5B and 6 show an embodiment of the control of the flyback converter of FIG. 8;

[0040] FIG. 7 shows an embodiment of the control of the flyback converter of FIG. 8; and

[0041] FIG. 8 shows a flyback converter comprising an active clamp according to one embodiment of the present disclosure.

DETAILED DESCRIPTION

[0042] In the ensuing description, various specific details are illustrated aimed at enabling an in-depth understanding of the embodiments. The embodiments may be provided without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments will not be obscured.

[0043] Reference to “an embodiment” or “one embodiment” in the framework of this description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment”, “in one embodiment”, or the like that may be present in various points of this description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0044] The references used herein are only provided for convenience and hence do not define the sphere of protection or the scope of the embodiments.

[0045] In FIGS. 2 to 8 described below, parts, elements or components that have already been described with reference to FIG. 1 are designated by the same references used previously in these figures. The description of these elements has already been made and will not be repeated in what follows in order not to burden the present detailed description.

[0046] Various embodiments of the present description relate to the operation of a flyback converter comprising an active clamp. The general architecture of such a flyback converter 20 is shown in FIG. 1, and the respective description applies in its entirety, in particular with respect to the connection of the flyback converter (transformer T, electronic switches S1 and S3, and capacitor C) and the active clamp (electronic switch S2 and capacitor C2). In this respect the present description relates to the control implemented within the control circuit 210. Specifically, such a control circuit may be any suitable analog and/or digital processing circuit, including a dedicated integrate control circuit or a programmable processing unit, such as a micro-processor programmed via software instructions.

[0047] As described in the foregoing, the control circuit 210 may drive such an active clamp with a complementary control, usually comprising four phases, which are repeated periodically: [0048] during a first time interval Δt1, the electronic switch S1 is closed and the electronic switch S2 is opened; [0049] during a second (dead-time) interval Δt2, the electronic switch S1 is opened and the electronic switch S2 remains open; [0050] during a third time interval Δt3, the electronic switch S1 remains open and the electronic switch S2 is closed; and [0051] during a fourth (dead-time) interval Δt4, the electronic switch S1 remains open and the electronic switch S2 is opened.

[0052] As schematically shown in FIG. 2A, during the time interval Δt1, the current Ipri in the primary side flows through the transformer T and increases linearly at a rate:

dIpri/dt=V.sub.in/Lpri

where Lpri represents the equivalent inductance at the primary side Lpri=L.sub.S+L.sub.M.

[0053] As schematically shown in FIG. 2B, during the time interval Δt2, both primary side electronic switches S1 and S2 are switched off. The current Ipri flows through the primary side of the transformer T and the parasitic capacitors C1 at the phase node (between the transformer T and the electronic switch S1), thereby increasing the voltage Vlsd at this node, which, e.g., corresponds to the drain-source voltage of a respective low-side FET S1.

[0054] As schematically shown in FIG. 2C, during the time interval Δt3, the current Ipri flows through the primary side T1. By providing a suitable dimensioning the leakage inductance L.sub.S of the transformer T and the clamp capacitance C2, an oscillation may be generated by these components.

[0055] At the same time the difference between the magnetizing current I.sub.LM flowing through the magnetizing inductance L.sub.M and the leakage current I.sub.LS flowing through the leakage inductance L.sub.S flows (in scaled form due to the turn ratio n of the transformer T) as secondary current Isec through the secondary side T2 of the transformer T.

[0056] As schematically shown in FIG. 2D, during the time interval Δt4, by switching off the electronic switch S2 at the end of the interval Δt3 when the primary side current Ipri is negative, this negative current flows through the transformer T and the parasitic capacitances C1 at the phase node, thereby discharging the parasitic capacitances C1. If the energy in the magnetizing L.sub.M and/or leakage inductance L.sub.S are high enough when the electronic switch S2 is turned off at the end of the interval Δt3, the phase node drops down to zero, thereby permitting a full zero voltage switching (ZVS) of the electronic switch S1 at the beginning of the following interval Δt1.

[0057] As described in the foregoing, such a complementary control has several drawbacks. However, the inventors have observed that the active clamp may also be driven with a non-complementary control.

[0058] FIG. 8 shows a flyback converter 30 that includes a control circuit 310 for driving the active clamp with a non-complementary control according to one embodiment of the present disclosure.

[0059] Specifically, as schematically shown in FIG. 3A, by closing the electronic switch S1 during the time interval Δt1 (with the switches S2 and S3 opened), the current Ipri in the primary side flows through the transformer T and increases linearly. Substantially, this phase is unchanged compared to the complementary control shown in FIG. 2A.

[0060] As schematically shown in FIG. 3B, during a second time interval Δt2′, the control circuit 310 keeps all electronic switches S1, S2 and S3 opened. However, when implementing the electronic switch S2 with a FET, at the end of this phase, the current Ipri in the primary side leakage inductance is steered to the clamp capacitor C2 through the body diode of the transistor S2 (or a similar diode D2 connected in parallel with the electronic switch S2) until the current Ipri drops to zero.

[0061] As schematically shown in FIG. 3C, during a third time interval Δt3a′, the high side switch S2 is kept off (or in can be kept on for the period of conduction of the diode associated with the switch S2), while the rectifier switch S3 is turned on. Substantially, in this phase, no current can flow on the primary side (Ipri=0), while the current flows to the output on the secondary side T2. Substantially, this phase corresponds to the flyback phase of a traditional flyback converter.

[0062] As schematically shown in FIG. 3D, when the current Isec on the secondary side T2 reaches zero, the control circuit 310 turns on the high side switch S2, thereby starting a fourth time interval Δt3b′. Substantially, at the beginning of this interval, the voltage on the clamp capacitor C2 is slightly higher than the voltage reflected from the secondary side, whereby the current Isec on the secondary side starts again to increase. Substantially, in this condition may again be present a resonance between the clamp capacitance C2 and the leakage inductance L.sub.S. At the same time, the current I.sub.LM on the magnetizing inductance L.sub.M becomes negative.

[0063] After a time which is preferably long enough to provide enough energy in the magnetizing inductance L.sub.M to force a soft switching, both the rectifier (S3) and the high side (S2) electronic switch are turned off, thereby terminating the fourth time interval Δt3b′.

[0064] Thus, as schematically shown in FIG. 3E, by switching off the electronic switch S2 at the end of the interval Δt3b′, when the magnetizing current I.sub.LM is negative, this negative current flows through the transformer T and the parasitic capacitances C1 at the phase node, thereby discharging the parasitic capacitances C1 and permitting a full zero voltage switching of the electronic switch S1 at the beginning of the following interval Δt1.

[0065] FIG. 4 shows in this respect an embodiment of the waveforms of the secondary side current Isec, the primary side current Ipri (including also the part of the magnetizing current I.sub.LM), the voltage Vlsd at the phase node (between the primary winding T1 and the electronic switch S1) and the drive signals LSGD, HSGD and SRGD for the switches S1, S2 and S3, respectively.

[0066] The inventors have observed that such a non-complementary control permits to reach low ringing on the secondary side T2 by tuning the transformer ratio n (ratio between the windings of the primary winding T1 and the secondary winding T2) and the clamp capacitance C2 for a given input voltage V.sub.in and output voltage V.sub.out. However, the inventors have observed that it is difficult to provide a matching for a wide range of input/output voltages.

[0067] FIG. 6 shows an embodiment of a modified control implemented within the control circuit 310.

[0068] Specifically, during a first time interval Δt1, the control circuit generates the drive signal LSGD, HSGD and SRGD in order to close the electronic switch S1, and open the electronic switches S2 and S3. Substantially, this phase remains unchanged compared to the controls shown in FIGS. 2A and 3A. Thus, the primary winding T1 is connected to the input voltage V.sub.in and the current Ipri in the primary side T1 increases linearly. As will be described in greater detail in the following, in various embodiments, the control circuit 310 may vary the duration of the time interval Δt1 in order to regulate the output voltage V.sub.out to a given reference value indicative of a requested output voltage.

[0069] During a second time interval Δt2a, the control circuit 310 keeps all electronic switches S1, S2 and S3 opened. Thus, the (positive) current Ipri in the primary side leakage inductance at the end of the interval Δt1 charges the parasitic capacitance C1 and the voltage Vlsd at the phase node increases.

[0070] Once the voltage Vlsd at the phase node reaches a given threshold, the electronic switch S2 is closed. Specifically, for this purpose the control circuit 310 may set the control signal HDGD in order to directly close the electronic switch S2, or the electronic switch S2 may be closed automatically via respective diode D2 connected in parallel with the electronic switch S2, such as the body diode of a respective FET. For example, the use of such a diode D2 has the advantage that the control circuit 310 does not have to monitor the voltage at the phase node.

[0071] Thus, during the following third time interval Δt2b the current Ipri in the primary side leakage inductance is also provided to the clamp capacitor C2 until it drops to zero. For example, for this purpose, the control circuit 310 may monitor the current Ipri and determine when the current Ipri reaches zero. As may be seen in FIG. 8, the control circuit 310 may have a first input coupled to the transformer T in order to detect the current Ipri, such as via a sense resistor (not shown).

[0072] In the embodiment considered, the control circuit 310 closes the electronic switch S3 during the time interval Δt2b, thereby permitting a current flow at the secondary side T2 of the transformer T. As will be described in greater detail in the following, the electronic switch S3 may also be implemented only with a diode D3 or a diode D3 may be connected in parallel with the electronic switch S3, such as the body diode of a respective FET. Accordingly, also the drive signal SRGD may not be required and thus is purely optional.

[0073] Thus, the time intervals Δt2a and Δt2b substantially correspond to the second time interval Δt2′ described with respect to FIG. 3B.

[0074] Accordingly, in the embodiment considered, at the end of the interval Δt2b the primary side current Ipri reaches zero and the secondary side current Isec reaches its maximum peak value.

[0075] During the following time interval Δt3a′ the electronic switches S1 and S2 are thus opened and the electronic switch S3 is closed. Accordingly, the primary side current Ipri remains zero, while the current Isec flows to the output on the secondary side T2. Specifically, the time interval Δt3a′ ends when the secondary side current Isec reaches zero. For example, for this purpose, the control circuit 310 may monitor the current Isec and determine when the current Isec reaches zero. As may be seen in FIG. 8, the control circuit 310 may have a second input coupled to the drain of the electronic switch S3 in order to detect the current Isec, such as via a sense resistor (not shown).

[0076] Substantially, this time interval Δt3a′ corresponds to the flyback phase already described with respect to FIG. 3C. However, compared to the embodiment described with respect to FIGS. 3 and 4, the operation changes for the following time intervals.

[0077] Specifically, similar to FIG. 3D, the control circuit 310 closes then the electronic switch S2 during a time interval Δt3c.

[0078] Specifically, as shown in FIG. 5A, during this switching state, the electronic switch S1 is opened and the electronic switches S2 and S3 are closed. Thus, this switching state corresponds more or less to the switching state described with respect to FIG. 3D, with some substantive difference which will be described in greater detail in the following.

[0079] Specifically, at the beginning of this interval Δt3c, the voltage on the clamp capacitor C2 is slightly higher than the voltage reflected from the secondary side, whereby the current Isec on the secondary side starts again to increase. Moreover, in this condition is present a resonance between the clamp capacitance C2 and the leakage inductance L.sub.S of the transformer. Specifically, this resonance has a period Tres corresponding to:

Tres=2π.Math.√{square root over (L.sub.S.Math.C2)}  (1)

[0080] At the same time, the current I.sub.LM on the magnetizing inductance L.sub.M becomes negative.

[0081] However, with respect to FIG. 3D, in the embodiment considered, the time interval Δt3c ends after Tres/2, i.e., after a semi-period of the oscillation of the clamp capacitance C2 and the leakage inductance L.sub.S. In various embodiments, the control circuit 310 may determine the end of the time interval Δt3c by determining whether the current Isec reaches again zero or the duration of the time interval Δt3c may be fixed to Tres/2.

[0082] Thus, while in FIG. 3D, the current at both primary and secondary side is truncated, in the presently considered embodiment, the time interval Δt3c ends at the instant when the secondary side current Isec reaches zero.

[0083] Thus, at the beginning of the following time interval Δt3d, the control circuit 310 may open the electronic switch S3 at zero current.

[0084] The respective switching state during the interval Δt3d is shown in FIG. 5B. Specifically, during the interval Δt3d, the electronic switches S1 and S3 are opened, and the electronic switch S2 remains closed.

[0085] In various embodiments, the duration of this phase Δt3d is determined by the energy to be stored on the transformer magnetizing inductance L.sub.M to obtain soft switching of the electronic switch S1 in the next phase.

[0086] The inventors have observed that the energy E.sub.SS to obtain such a soft switching can be approximated as

E.sub.SS=1/2C1V.sub.in.sup.2  (2)

[0087] Starting from zero crossing (at the end of the interval Δt3a′/beginning of the interval Δt3c), the current in the magnetizing inductor L.sub.M increases approximately as

[00001]$\begin{array}{cc}{I}_{\mathrm{LM}}=\frac{{\mathrm{nV}}_{\mathrm{out}}}{L_M}{t}_{\mathrm{clamp}}& \left(3\right)\end{array}$

where n is the turn ration between the primary and the secondary winding and tclamp is the total clamp time corresponding to the sum of the durations of the intervals Δt3c and Δt3d (i.e., tclamp=Δt3c+Δt3d).

[0088] The energy E.sub.LM in the magnetizing inductor L.sub.M is:

E.sub.LM=1/2L.sub.MI.sub.LM.sup.2  (4)

i.e., by combining equations (3) and (4):

[00002]$\begin{array}{cc}{E}_{\mathrm{LM}}=\frac{1}{2}\frac{n^2{V}_{\mathrm{out}}^2}{L_M}{t}_{\mathrm{clamp}}^2& \left(5\right)\end{array}$

[0089] Accordingly, to obtain an energy E.sub.LM in the magnetizing inductor equal to energy E.sub.SS, the total clamp time may be calculated from equations (2) and (5) as:

[00003]$\begin{array}{cc}{t}_{\mathrm{clamp}}=\frac{1}{n}\sqrt{C1L_M}\frac{V_{\mathrm{in}}}{V_{\mathrm{out}}}& \left(6\right)\end{array}$

[0090] Thus, equation (6) can be used to calculate the total clamp duration t.sub.clamp. Alternatively, equations (2) and (4) may be used to determine a threshold value for the current at the primary side Ipri (which during the interval Δt3d corresponds to the magnetization current I.sub.LM) and the control circuit 310 may monitor the primary side current Ipri and the control circuit 310 may end the interval Δt3d when the primary side current Ipri reaches the given threshold value.

[0091] Thus, at the end of the interval Δt3d, the primary current Ipri is negative and the magnetizing inductance L.sub.M has stored enough energy to discharge the parasitic capacitance C1 associated with the phase node.

[0092] During a following time interval Δt4, the control circuit 310 may thus switch off the electronic switch S2. Thus, during the time interval Δt4 (which substantially corresponds to the situation already described with respect to FIGS. 2D and 3E, the negative primary current Ipri flows through the transformer T and the parasitic capacitances C1 at the phase node, thereby discharging the parasitic capacitances C1. Moreover, once the voltage Vlsd at the phase node reaches zero, the control circuit 310 may close again the electronic switch S1, thereby starting the following time interval Δt1. For example, for this purpose the control circuit 310 may monitor the voltage at the phase node. Generally, the duration of the time interval Δt4 may also be fixed.

[0093] Thus, in the embodiment considered, each switching cycle has the following switching duration T.sub.SW:

T.sub.SW=Δt1+Δt2a+Δt2b+Δt3a′+Δt3c+Δt3d+Δt4.

[0094] In the embodiment considered, the electronic switch S3 is closed when the secondary current Isec is positive (intervals Δt2b, Δt3a′ and Δt3c). Thus, this electronic switch S3 could also be implemented with a diode D3 or with a diode connected in parallel with the electronic switch S3, such as a body diode of a respective FET, wherein either: [0095] the anode of the diode D3 is connected to the terminal 202b and the cathode is connected to the secondary winding T2 (as shown in FIG. 1), or [0096] the anode of the diode is connected to the secondary winding T2 and the cathode is connected to the terminal 202a.

[0097] Moreover, as described in the foregoing, the start and end of the interval Δt2b may be automatically by connecting a diode D2 in parallel with the electronic switch S2, such as the body diode of a respective FET, wherein the anode is connected to the phase node and the cathode is connected to the capacitor C2.

[0098] Thus, in in various embodiments, the control circuit 310 may generate the control signals LSGD and HSGB in order to control the duration Δt1 (electronic switch S1 is closed) and the duration t.sub.clamp=Δt3c+Δt3d (electronic switch S2 is closed). Generally, in the embodiments considered, the control circuit 310 should also determine the end of the interval Δt3a′ when the secondary side current Isec reaches zero.

[0099] Specifically, the control circuit 310 may vary the duration Δt1 in order to obtain a given output voltage V.sub.out. In fact, in a flyback converter the ratio V.sub.in/V.sub.out between the input and the output voltage is proportional to the term D/(1-D), where D=Δt1/T.sub.SW is the duty cycle.

[0100] Conversely, as described with respect to equation (6) the duration t.sub.clamp should also take into account the ratio V.sub.in/V.sub.out. Thus, instead of measuring the input voltage V.sub.in, the duration t.sub.clamp may be calculated by multiplying a fixed parameter with D/(1−D), i.e., the control circuit 310 may determine the duration t.sub.clamp as a function of the duty cycle D, which in turn is determined as a function of the duration Δt1.

[0101] In the embodiment considered, the clamp capacitor C2 should thus be dimensioned in order to store enough energy for reaching the ZVS condition on the primary side T1, but small enough to complete a half resonance with the leakage inductance L.sub.S during phase Δt3c.

[0102] Specifically, as shown in equation (1), the minimum clamp duration is determined by the clamp capacitor C2 and leakage inductance L.sub.S values. Generally, the inventors have observed, that it is desirable to maintain this duration as short as enables to obtain soft switching in the condition having the shortest clamping time, which, as shown in equation (6), happens in the operating condition when the input voltage V.sub.in has its minimum value and the output voltage V.sub.out has its maximum value.

[0103] The inventors have observed that this control gives best results with a synchronous rectifier on the second side, while it can be applied even to system with non-synchronous rectification.

[0104] FIG. 7 shows a second embodiment of the driving implemented within the control circuit. Specifically, as described in the foregoing, the control circuit 310 determines the end of the interval Δt3c when the secondary side current Isec reaches zero, e.g., by either monitoring the secondary side current Isec or by using a fixed duration for the interval Δt3c, which corresponds to Tres/2.

[0105] However, as shown in FIG. 7, the control circuit 310 does not necessarily have to terminate the interval Δt3c (interval Δt3c′ in FIG. 7) after the first half-period of the resonance Tres, but the control circuit 310 may terminate the interval Δt3c′ after a multiple of Tres/2, i.e., at instants which correspond to multiple half-periods of the oscillation. In fact, in each of these instants the secondary side current Isec would be zero. Thus, in various embodiments, the control circuit 310 may determine the end of the time interval Δt3c′ by determining whether the current Isec has reached zero for a given number N of times or the duration of the time interval Δt3c may be fixed to N.Math.Tres/2, with N being a positive integer number. For example, in FIG. 2, the duration of the interval Δt3c′ corresponds to Tres, i.e., N=2.

[0106] Of course, without prejudice to the principle of the disclosure, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present disclosure.

[0107] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.