Abstract
Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The described methods and devices also address carrier aggregation requirements and provide solutions that can be used both in single-mode and split-mode operations.
Claims
1.-25. (canceled)
26. A radio frequency (RF) receiver front-end comprising: a low noise amplifier (LNA) block; a selectively bypassable source follower amplifier stage, and a configurable output matching network, wherein the LNA block is selectively connectable to either of the selectively bypassable source follower amplifier stage or the configurable output matching network based on a selected band-width and/or a selected gain.
27. The RF receiver front-end of claim 26, wherein a bandwidth and a gain of the RF receiver front-end is adjustable based on a bypass state of the selectively bypassable source follower amplifier stage and a configuration state of the configurable output matching network.
28. The RF receiver front-end of claim 27, wherein: in a first state: the LNA block is connected to the configurable output matching network; the LNA block is disconnected from the selectively bypassable source follower amplifier stage; and the selectively bypassable source follower amplifier stage is bypassed by having a gate terminal of the selectively bypassable source follower amplifier stage shorted to ground; in a second state: the LNA block is disconnected from the configurable output matching network; and the LNA block is connected to the selectively bypassable source follower amplifier stage.
29. The RF receiver front-end of claim 28, further comprising a configurable input matching network coupled with the LNA block, and wherein the bandwidth and the gain of the RF receiver front-end are adjustable based on a configuration of the input matching network.
30. The RF receiver of claim 29, wherein i) the configuration states of the configurable input matching network and the configurable output matching network and ii) the bypass state of the selectively bypassable source follower amplifier stage are controlled by a switching network.
31. The RF receiver of claim 30, wherein the configurable input matching network and the configurable output matching network comprise selectively switchable capacitors and inductors.
32. The RF receiver front-end of claim 30, wherein the switching network configures and reconfigures the RF receiver front-end to operate at one or more frequency ranges comprising at least a narrowband, an extended narrowband and a wideband frequency range.
33. The RF receiver front-end of claim 26, implemented on a single die or chip.
34. A radio frequency (RF) receiver front-end comprising: a first amplifying element; a first configurable output matching network comprising a first source follower amplifier stage; and a second configurable output matching network comprising a second source follower amplifier stage, wherein: the first and the second output matching networks are each coupled to a drain terminal of the first amplifying element, and the first and the second source follower amplifier stages are each configured to selectively be in an active or inactive state.
35. The RF receiver front-end of claim 34, wherein: in a first single-mode state, the first source follower amplifier stage is in the active state and the second source follower amplifier stage is in the inactive state; in a second single-mode state, the first source follower amplifier stage is in the inactive state and the second source follower amplifier stage is in the active state, and in a split-mode state, the first and the second source follower amplifier stages are in the active state.
36. The RF receiver front-end of claim 35, further comprising a first cascode transistor coupling the first amplifying element to the first source follower amplifier stage, and a second cascode transistor coupling the second source follower amplifier stage to the first amplifying element.
37. The RF receiver front-end of claim 36, wherein: in the first single-mode state, the first cascode transistor is in the active state and the second cascode transistor is in the inactive state; in the second single-mode state, the first cascode transistor is in the inactive state and the second cascode transistor in the active state, and in the split-mode state, the first and the second cascode transistors are in the active state.
38. The RF receiver front-end of claim 34, wherein a bandwidth and a gain of the RF receiver front-end are adjustable based on states of the first and the second source follower amplifier stages and configuration state of the first and the second configurable output matching networks.
39. The RF receiver front-end of claim 38, further comprising a configurable input matching network coupled with the first amplifying element, and wherein the bandwidth and the gain of the RF receiver front-end are adjustable based on a configuration of the configurable input matching network.
40. The RF receiver of claim 39, wherein the configuration states of the input, the first, and the second configurable output matching networks and the states of the first and the second source follower amplifier stages are controlled by a switching network.
41. The RF receiver of claim 39, wherein the configurable input, the first, and the second output matching networks comprise selectively switchable capacitors and inductors.
42. The RF receiver front-end of claim 41, wherein the switching network configures or reconfigures the RF receiver front-end to operate at one or more frequency ranges comprising at least a narrowband, an extended narrowband and a wideband frequency range.
43. The RF receiver front-end of claim 34, further comprising a third source follower amplifier stage connected to a source terminal of the first source follower amplifier stage and a fourth source follower amplifier stage connected to a source terminal of the second source follower amplifier stage.
44. The RF receiver front-end of claim 34, further comprising a second amplifying element having a drain terminal connected to the drain terminal of the first amplifying element.
45. The RF receiver front-end of claim 44 configured to receive a first RF signal at an input of the first amplifying element, and to receive a second RF signal at an input of the second amplifying element, the second RF signal being different from the first RF signal.
46. A method to control an RF receiver front-end including a low noise amplifier (LNA), the method comprising: providing a configurable output matching network; providing a source follower amplifier, and based on a desired gain and/or bandwidth: selectively connecting or disconnecting one of the configurable output matching network or the source follower amplifier to the LNA.
47. The method of claim 46, further comprising shorting a gate terminal of the source follower amplifier to ground when connecting the output matching network to the LNA.
Description
DESCRIPTION OF THE DRAWINGS
[0041] FIG. 1 shows some examples of frequency band specifications as defined by the 5G new radio (NR) standard.
[0042] FIG. 2A shows prior art RF receiver front-end which is more suitable for narrow-band applications.
[0043] FIG. 2B shows another prior art RF receiver front-end architecture.
[0044] FIG. 2C shows a prior art RF receiver front-end using multi-stage output matching.
[0045] FIG. 2D shows a comparison table summarizing the overall performances of the architectures shown in FIGS. 2A-2C when used in wideband applications.
[0046] FIG. 2E shows a prior art RF receiver front-end architecture.
[0047] FIG. 3 shows an electronic circuit according to an embodiment of the present disclosure.
[0048] FIG. 4A shows another electronic circuit according to an embodiment of the present disclosure.
[0049] FIG. 4B shows a switching network according to embodiments of the present disclosure.
[0050] FIGS. 5A, 6A, 7A, 8A and 9 show various electronic circuits in accordance with embodiments of the present disclosure.
[0051] FIGS. 5B, 6B, 7B and 8B shows tables representing switch states according to embodiments of the present disclosure.
[0052] FIG. 10 shows a high level flowchart representing the reconfigurablility of RF receiver front-end designed according to the teachings of the present disclosure.
[0053] FIGS. 11-14 show electronic circuits according to embodiments of the present disclosure.
[0054] FIGS. 15-16 show multiple-input, multiple-output electronic circuits according to further embodiments of the present disclosure.
DETAILED DESCRIPTION
[0055] Throughout the present disclosure, the term “node” will be used to describe any point on a circuit where connections of two or more circuit elements meet or are adapted to meet. Although nodes will be graphically represented by points in the present disclosure, the person skilled in the art will understand that a node may also present part of a line or connection between elements or circuital devices, not just a single point.
[0056] FIG. 3 shows an electronic circuit (300) according to an embodiment of the present disclosure. The electronic circuit (300) comprises an RF receiver front-end (310) connectable to an input circuit (360) at the RF receiver front-end input (361) and to a load (350) at the RF receiver front-end output (351). The RF receiver front-end (310) comprises and LNA block (322), an output matching network (330) and a switching network (340). The LNA block (322) comprises an input matching network (321). The switching network (340) is connected to the output matching network (330), the LNA block (322) and the input matching network (321). The RF receiver front-end (310) is configured to receive an input signal (Vin) from the input circuit (360) at the RF receiver front-end input (361) and to generate a corresponding output signal at the RF receiver front-end output (351), across load (350).
[0057] With reference to FIG. 3, the switching network (340) comprises one or more switches used to configure/reconfigure the RF receiver front-end (310) to meet different and possibly conflicting requirements imposed by various applications. In other words, by turning a subset of such switches on or off, certain electronic elements that are constituents of the input matching network (321), LNA block (322), and/or output matching network (330) may be switched in and out of a signal path from the RF receiver front-end input (361) to RF receiver front-end output (351), such that the RF receiver front-end (310) is adapted to meet certain design requirements. By way of example, and not of limitation, the RF receiver front-end (310) may be used in a first application where saving power is of highest importance. In such application, the RF receiver front-end (310) may be configured to possibly switch to lower gains more often so that the overall power consumption requirements are met. This is in contrast with a second exemplary application where a signal having the highest possible strength is highly desired. In this scenario, the RF receiver front-end (310) may be configured to accommodate the highest data rate providing signal with the highest fidelity. In order to do so and compared to the first application, a different set of switches may be turned on or off thereby switching in and out different electronic elements so the requirements imposed by the second application are met. The person skilled in the art will appreciate that the methods and devices designed in accordance with teachings of the present disclosure allow for a higher flexibility to accommodate applications imposing completely different requirements using practically the same design. In what follows, exemplary embodiments of the present disclosure will be described to further clarify such concept.
[0058] FIG. 4A shows an electronic circuit (400A) in accordance with an embodiment of the present disclosure. The electronic circuit (400A) comprises output matching network (430) and an LNA block (422) including an input matching network (421). The RF receiver front-end (410) is an exemplary implementation of the RF receiver front-end (310) of FIG. 3. In other words, input matching network (421), LNA block (422) and output matching network (430) are exemplary implementations of their counterparts, input matching network (321), LNA block (322) and output matching network (330) of FIG. 3, respectively. The RF receiver front-end (410) is connectable to the load (350). Connections of the switching network (440) to the rest of the circuit are not shown for the sake of simplicity. As shown in FIG. 4A, RF receiver front-end (410) comprises several connection points that are represented by nodes (a, a1, b, b′, b″, c, cl, . . . , 1, 1′). Nodes represented with same alphabetic letter in their name correspond to each other. For example, nodes (a, a′) may be connected to each other using a switch. As a further example, node (b) may be connected to node (b′) or (b″) depending on the position of a corresponding single-pole double-throw switch. As will be explained in what follows, switches used for such purpose may be constituents of the switching network (340). The switching network may be configured differently to serve different applications with various and sometimes conflicting requirements.
[0059] With reference to FIG. 4A: [0060] feedback resistor (R.sub.f) may be switched in and out by connecting and disconnecting nodes (a, a′) respectively. The feedback resistor (R.sub.f) may be switched in to provide a wider band input matching. According to embodiments of the present disclosure, the feedback resistor (R.sub.f) may be part of a feedback network comprising resistors and reactive elements such as inductors and/or capacitors. [0061] Depending on the required output matching, a larger or smaller inductor can be used by connecting node (b) to node (b′) or node (b″), respectively. In accordance with further embodiments of the present disclosure, any or a combination of inductors (L.sub.d1, L.sub.d2) may be replaced by a variable inductor. [0062] Transistor (T3) may be switched in/out by connecting/disconnecting nodes (i, i′) respectively. When transistor (T3) is switched in, a combination of such transistor and current source (Io) provide a source follower configuration, and such a source follower being bypassable through connecting or disconnecting a combination of nodes (i i′, j j′ and k k′), as shown in FIG. 5A (source follower active) and FIG. 6A (source follower bypassed). As mentioned previously, such configuration is used when a wider band output matching is desired while minimizing impact on gain and linearity. In narrower band application where transistor (T3) may not be required, the gate of transistor (T3) is connected to ground by connecting nodes (j, j′) to minimize power consumption. [0063] As mentioned previously, for wideband applications, resistor (Rd) may be switched in by connecting nodes (c, c′). As a result, wider band output matching is achieved at the expense of the gain. [0064] A combination of capacitors (C1, C2, C3) and inductor (L4) or a subset thereof may be switched in to achieve wideband operation using only passive elements. This represents essentially a multi-stage passive output matching network. [0065] Nodes (1,1′) can be connected/disconnected to achieve narrow/wide band input matching. When nodes (1, 1′) are connected, a combination of capacitance (C3) and gate-source capacitance (C.sub.gs) of transistor (T3) with inductances (L1, L2) and feedback resistor (R.sub.f) forms the input matching network (421). Therefore, switching feedback resistor (R.sub.f) and/or capacitor (C4) provides two different mechanisms to provide wider or narrow band input matching depending on desired requirements. [0066] RF receiver front-end (410) may be configured to receive voltages (V.sub.d1, V.sub.d2) for biasing purposes.
[0067] FIG. 4B shows a switching network (440) in accordance with embodiments of the present disclosure. Switching network (440) represents an exemplary implementation of the switching network (340) of FIGS. 3 and 4A, comprising one or more switches (S1, . . . , S12). Switching network (440) further comprises several nodes shown in black dots connecting to various corresponding nodes of the electronic circuit (400A). Connections of the nodes of the switching network (440) to corresponding nodes of the electronic circuit (400A) are shown with dotted arrows. Referring to FIGS. 4A-4B, and as an example, switch (S1) may connect or disconnect nodes (a, a1), switch (S2) may connect or disconnect nodes (b, b′) or (b′b″), switch (S3) may connect or disconnect nodes (c, c′) and so on. As a further example, as mentioned previously, the configuration of switches (S1, . . . , S12) depends on the application and therefore the desired set of requirements that are to be met. According to the embodiment of the present disclosure, the configuration of switches (S1, . . . , S12) may change during operation of the circuit. According to embodiments of the present disclosure, switching network (440) may comprise a control circuit (not shown) to control the state of switches (S1, . . . , S12).
[0068] In accordance with embodiments of the present disclosure, FIG. 5A shows an electronic circuit (500A) comprising an RF receiver front-end (510) which is the RF receiver front-end (410) of FIG. 4A configured according to what is shown in switching configuration table (500B) of FIG. 5B. As shown in switching configuration table (500B), switches (S1, . . . , S12) of switching network (540) are mentioned in a top row, with a bottom row showing states of the switches and a middle row showing switch node IDs. In other words, input matching network (521), LNA block (522) and output matching network (530) represent their respective counterparts (421, 422, 430) of FIG. 4A, each configured according to table (500B) of FIG. 5B. In view of what described previously throughout the disclosure, the RF receiver front-end (510) is configured to meet wideband requirements using a source follower configuration providing best gain flatness across wideband and using larger inductance (series combination of L.sub.d1 and L.sub.d2).
[0069] In accordance with further embodiments of the present disclosure, FIG. 6A shows an electronic circuit (600A) comprising an RF receiver front-end (610) which is the RF receiver front-end (410) of FIG. 4A configured according to what is shown in switching configuration table (600B) of FIG. 6B. As shown in switching configuration table (600B), switches (S1, . . . , S12) of switching network (640) are mentioned in a top row with a bottom row showing states of the switches and a middle row showing switch node IDs. In other words, input matching network (621), LNA block (622) and output matching network (630) represent their respective counterparts (421, 422, 430) of FIG. 4A, each configured according to table (600B) of FIG. 6B. In contrast with the RF receiver front-end (510) of FIG. 5A, in RF frond-end (610), the source follower is switched out (nodes i i′ and k k′ are disconnected while nodes j j′ are connected) and output matching is achieved using passive elements. In other words, a combination of inductors (L.sub.d1, L.sub.d1-FL.sub.d2, L.sub.4) and capacitors (C1, C2, C3) provides a multi-pole filter which may be designed to accommodate output matching according to the desired requirements. Moreover, the gate of transistor (T3) is connected to ground for lower current consumption. Referring back to the comparison table of FIG. 2D and the architectures shown in FIGS. 2B-2C, it can be noticed that RF receiver front-end (510) may provide improved gain flatness and linearity over the RF receiver front-end (610) with a possible increase in power depending on the required performance in other parameters with a flexibility to choose how to optimize.
[0070] In accordance with other embodiments of the present disclosure, FIG. 7A shows an electronic circuit (700A) comprising an RF receiver front-end (710) which is the RF receiver front-end (410) of FIG. 4A configured according to what is shown in switching configuration table (700B) of FIG. 7B. As shown in switching configuration table (700B), switches (S1, . . . , S12) of switching network (740) are mentioned in a top row with a bottom row showing states of the switches and a middle row showing switch node IDs. In other words, input matching network (721), LNA block (722) and output matching network (730) represent their respective counterparts (421, 422, 430) of FIG. 4A, each configured according to table (700B) of FIG. 7B. In view of what described previously throughout the disclosure, the RF receiver front-end (710) is configured to be used in narrow band application. In such configuration, narrow band output matching is achieved by switching out capacitors (C1, C2), inductor (L4), resistor (Rd) and transistor (T3). By virtue of using a combination of a smaller inductance (e.g. using only (L.sub.d1 and switching out L.sub.d2)) with capacitor (C3) narrow band operation is optimized for a desired band. As for the input matching, feedback resistor (R.sub.f) is switched out and the capacitor (C4) is switched in to optimize input matching performance for narrow-band operation.
[0071] In accordance with yet other embodiments of the present disclosure, FIG. 8A shows an electronic circuit (800A) comprising RF receiver front-end (810) which is the RF receiver front-end (410) of FIG. 4A configured according to what is shown in switching configuration table (800B) of FIG. 8B. As shown in switching configuration table (800B), switches (S1, . . . , S12) of switching network (840) are mentioned in a top row with a bottom row showing states of the switches and a middle row showing switch node IDs. In other words, input matching network (821), LNA block (822) and output matching network (830) represent their respective counterparts (421, 422, 430) of FIG. 4A, each configured according to table (800B) of FIG. 8B. In view of what was described previously throughout the disclosure, the RF receiver front-end (810) is configured to be used in wide band applications but in lower gain mode. In such configuration, wideband output matching is achieved by de-Qing, e.g. switching in resistor (Rd). As discussed previously, this will result in a lower gain. Following the similar mechanism as described before, wideband input matching is obtained by switching the feedback resistor in. With reference to the embodiments shown in FIGS. 4A, 5A, . . . , 8A, one or more passive elements (inductors or capacitors) may be variable to provide further flexibility to meet different requirements.
[0072] With further reference to FIGS. 4A-8B, the person skilled in the art will appreciate that, by reconfiguring the same circuit, different requirements imposed by various applications may be met using the teachings of the present disclosure.
[0073] FIG. 9 shows an electronic circuit (900) comprising an RF receiver front-end (910) according to embodiments of the present disclosure. The RF receiver front-end (910) comprises an LNA block (922) including an input matching network (921), and an output matching network (930) that are exemplary implementations of the input matching network (321), the LNA block (322) and an output matching network (330) of FIG. 3. The concepts discussed with regards to embodiments of FIGS. 4A-8A are equally applicable here. In other words, nodes represented with same letters correspond to each other and by connecting or disconnecting corresponding nodes, various elements of the electronic circuit (900) may be switched in or out thereby providing flexibility of adapting to stringent and possibly conflicting requirements imposed by different applications. As shown in FIG. 9, the output matching network (930) comprises variable resistor (Rd) and variable capacitors (C.sub.1, . . . . C.sub.5) to provide additional flexibility when designing such a circuit for different use cases. With reference to FIGS. 4A and 9, it can be noticed that the current source (Io) of FIG. 4A is now replaced by inductance (L.sub.sf). By way of example, when nodes (n, n′) and nodes (k, k′) are connected by closing their corresponding switches, inductors (L.sub.d1, L.sub.sf) are effectively parallel to each other, resulting a smaller overall inductance. Such configuration may be used in high performance narrowband application when high quality matching is required to be achieved by using smaller inductances. In such application, single stage LC matching may be achieved by connecting nodes (m, m′) and (f, f′) to each other by closing corresponding switches. Continuing with the same scenario, the person skilled in the art will appreciate that by virtue of having variable capacitors (C1, C4), tuning into different bands for high quality output matching is made possible. The person skilled in the art will also understand that, without departing from the scope and spirit of the invention, each passive element may comprise series and/or parallel combination of elements of the same type. As an example, variable capacitor (C1) may comprise a series and/or a parallel combination of capacitors or a combination thereof. Same applies to all inductors and resistors that are constituents of the electronic circuit (900) of FIG. 9. Different exemplary switching configurations described previously using switching configuration tables (500B, 600B, . . . 800B) are also equally applicable here for the electronic circuit (900) of FIG. 9.
[0074] With reference to FIGS. 4A-9, embodiments in accordance with the present disclosure may be envisaged where: [0075] The cascode configuration using transistors (T1, T2) may comprise one or more transistors. [0076] Transistors (T1, T2, T3) may comprise field-effect transistors (FET) or metal-oxide semiconductor field-effect transistors (MOSFETs) [0077] Constituent switches of the switching network may comprise field-effect transistors (FET) or metal-oxide semiconductor field-effect transistors (MOSFETs) [0078] The switching network may comprise one or more switches depending on the requirements. [0079] Constituents of such embodiments may be implemented on the same chip or on separate chips. [0080] A combination of transistor (T3) and current source (Io) or degenerative inductor (L.sub.sf) may be implemented according to a common source or common gate configuration.
[0081] FIG. 10 shows a high-level flowchart representing the reconfigurability of RF receiver front-ends designed according to the teachings of the disclosure and as controlled either by external control commands or by internal commands generated in response to internal conditions. As shown, an input signal received, step (1001). Depending on the bandwidth requirement, step (1002), the RF receiver front-end is configured to narrowband or wideband as shown in steps (1003, 1004) respectively. Moreover, depending also on gain requirements, as shown in step (1005), the RF receiver front-end is configured for a low or high gain, as shown in steps (1006, 1007) and then the output signal is generated. This is a flowchart based on exemplary requirements such as frequency ranges and gain modes just illustrating the flexibility of a design using the same hardware that can adapt to various requirements. As detailed previously, the person skilled in the art will understand that the disclosed teachings can also be used to configure RF receiver front-ends to adapt to various requirements other than gain or frequency range.
[0082] FIG. 11 shows an electronic circuit (1100) according to an embodiment of the present disclosure. The electronic circuit (1100) has some similarities with the electronic circuit (300) of FIG. 3 and provides all the benefits associated with the electronic circuit (300) of FIG. 3 as detailed previously. Additionally, the electronic circuit (1100) is designed to operate in various single and split-modes to address carrier aggregation requirements as described previously using examples from the 5G NR standard.
[0083] With reference to FIG. 11, the electronic circuit (1100) comprises an RF receiver front-end (1110) connectable to an output load (1150) having a plurality of load elements (L.sub.1, . . . , L.sub.n). The electronic circuit (1100) is configured to receive an input signal at input (in) and to provide a plurality of corresponding output signals at outputs (out.sub.1, . . . , out.sub.n). The RF receiver front-end (1110) comprises an LNA block (1122), an output matching network (1130) and a switching network (1140). The LNA block (1122) comprises an input matching network (1121) connected with the plurality of electronic elements (E.sub.1, . . . , E.sub.n). The output matching network (1130) comprises a plurality of output matching elements (M.sub.1, . . . , M.sub.n) connected with corresponding electronic elements (E.sub.1, . . . , E.sub.n). As shown in FIG. 11, the signal split occurs at split-point (1123), which is essentially an output of the input matching network (1121). According to embodiments of the present disclosure, and depending on the operation mode, the signal at the split-point (1123) is divided between the plurality of the electronic elements (E.sub.1, . . . , E.sub.n). The switching network (1140) is connected to the output matching network (1130), the LNA block (1122) and the input matching network (1121) and provides the same functionalities as what was described with regards to switching network (340) of FIG. 3. In accordance with embodiments of the present disclosure, the electronic circuit (1110) may be configured to operate in various single-mode operations connecting the input (in) to any of the outputs (out.sub.1, . . . , out.sub.n). According to further embodiments of the present disclosure, the electronic circuit (1110) may also be configured to operate in various split-mode operations connecting the input (in) to any two or more of the outputs (out.sub.1, . . . , out.sub.n). In what follows, exemplary implementations of the electronic circuit (1110) in accordance with teachings of the present disclosure will be presented.
[0084] FIG. 12 shows an electronic circuit (1200) in accordance with embodiments of the present disclosure. The electronic circuit (1200) is designed to be configurable both for single-mode and split-mode operations depending on the states of switches (S.sub.1, . . . , S.sub.4). With reference to FIGS. 11-12, the input matching network (1221) is an exemplary implementation of the input matching network (1121) of FIG. 11. The electronic circuit (1200) further comprises two output matching network (1230a, 1230b), each of which may be an exemplary implementation of any of the output matching elements (M.sub.1, . . . , M.sub.n) of FIG. 11. In other words, a combination of the two output matching network (1230a, 1230b) is the counterpart of the output matching network (1130) of FIG. 11. Similarly, each of the transistors (T2a, T2b) may be an exemplary implementation of any of the electronic elements (E.sub.1, . . . , E.sub.n). Moreover, each of the resistors (RL, RL′) may represent any of the load elements (L.sub.1, . . . , L.sub.n) of FIG. 11.
[0085] With further reference to FIG. 12, a combination of the transistors (T1, T2a) or transistors (T1, T2b) represent each a cascode configuration wherein the split is initiated at the drain of transistor (T1) representing essentially the counterpart of the split-point (1123) of FIG. 11. The electronic circuit (1200) is configured to receive an input signal from the input (in) and to generate output signal(s) at the one or both of outputs (out1, out2) depending on the states of switches (S.sub.1, . . . , S.sub.4). A combination of switches (S.sub.1, . . . , S.sub.4) may be an exemplary implementation of the switching network (1140) of FIG. 11. Transistors (T3a, T3b) combined with their respective current sources (Ia, Ib) represent source followers providing the wideband output matching similar to what was described with regards to some of previously described embodiments such as the embodiment as shown in FIG. 4A. With reference to FIG. 2E and FIG. 12, the person skilled in the art will appreciate that in the electronic circuit (1200) the split is initiated at the cascode transistors (drain of transistor (T1)) and the source followers provides the required isolation and impedance transformation requirements. As a result, there is no degradation of the NF performance which was the case for the front-end receiver (200E) of FIG. 2E where the split was performed at the input.
[0086] With further reference to FIG. 12, the electronic circuit (1200) has three modes of operation: [0087] Single mode (in to out1): in this mode switch (S3) is closed and as a result, transistor (T2b) is disabled as its gate is pulled to ground. Transistor (T3b) is also disabled. This can be done either by opening switch (S4) to disable current source (Ib) or by turning off the bias voltage (V2). Switch (S2) is open and switch (S1) is closed. Transistors (T1, T2a, T3a) are enabled. [0088] Single mode (in to out2): in this mode switch (S2) is closed and as a result, transistor (T2a) is disabled as its gate is pulled to ground. Transistor (T3a) is also disabled. This can be done either by opening switch (S1) to disable current source (Ib) or by turning off the bias voltage (V2). Switch (S3) is open and switch (S4) is closed. Transistors T1, T2b, T3b) are enabled. [0089] Split mode: Switches (S1, S4) are closed and switches (S2, S3) are open. As a result, transistors (T2a, T2b) as well as transistors (T3a, T3b) are enabled to amplify the input signal at input (in) to both outputs (out1, out2) simultaneously.
[0090] FIG. 13 shows an electronic circuit (1300) in accordance with further embodiments of the present disclosure. The principle of operation of the electronic circuit (1300) is similar to what was described with regards to electronic circuit (1200) of FIG. 12.
[0091] With reference to FIGS. 11 and 13, the input matching network (1321) is an exemplary implementation of the input matching network (1121) of FIG. 11. The electronic circuit (1300) further comprises two output matching networks (1330a, 1330b), each of which may be an exemplary implementation of any of the output matching elements (M.sub.1, . . . , M.sub.n) of FIG. 11. In other words, a combination of the two output matching network (1330a, 1330b) is the counterpart of the output matching network (1130) of FIG. 11. Similarly, each of the transistors (T2a, T2b) may be an exemplary implementation of any of the electronic elements (E.sub.1, . . . , E.sub.n). Moreover, each of the resistors (RL, RL′) may represent any of the load elements (L1, . . . , Ln) of FIG. 11. A combination of switches (S5, S6, S7) may be an exemplary implementation of some of the switches included in the switching network (1140) of FIG. 11. With reference to FIGS. 12-13, the person skilled in the art will understand that the electronic circuit (1300) may also include switches (S.sub.1, . . . , S.sub.4) of FIG. 12 providing the same functionalities. Such switches are not shown in FIG. 13 for the sake of clarity.
[0092] As shown in FIG. 13, the transconductance current generated by transistor (T1) is split equally into currents (i.sub.1, i.sub.2). Assuming everything else equal, this corresponds to 6 dB gain drop in the split-mode compared to the single-mode. In order to have substantially equal gains in both single and split-modes, one solution is to use de-Qing resistors (Rd, Rd′) which may be switched in (when operating in single-mode) and out (when operating in split-mode) using their respective switches (S5, S6). By way of example, in a single-mode operation where transistors (T2a, T3a) are active, switch (S5) may be closed to switch in resistor (Rd). In this scenario, a combination of inductor (Ld) and resistor (Rd) are designed such that substantially equal gains are maintained during single and split-mode operation. According to embodiments of the present disclosure, additional capacitive switching may be implemented to maintain correct resonant frequency in all modes of operation. In other words, capacitors (not shown) may be implemented parallel with resistor (Rd) and (Rd′). Such capacitors may be switched in and out during different modes to maintain the same resonant frequency for both single and split-mode.
[0093] With further reference to FIG. 13, a combination of the switch (S7) and inductor (L2, L2′) may also be used to maintain equal gains in various modes of operation. According to embodiments of the present disclosure, only inductor (L2′) may be switched in during the split-mode resulting in an increase in gain at the expense of input matching performance. During the single-mode operation, the position of switch (S7) may be changed to include both inductors (L2, L2′) and therefore reduce the gain. Embodiments in accordance with further embodiments of the present disclosure may be envisaged wherein current sources (Ia, Ib) may be replaced by inductors. In such a case, the bias point of the source follower including transistor (T3b) is set by the gate of transistor (T3b) which may be DC-decoupled from the drain of transistor (T2b) by a series DC blocking capacitor (not shown). Similarly, the bias point of the source follower including transistor (T3a) is set by the gate of transistor (T3a) which may be DC-decoupled from the drain of transistor (T2a) by a series DC blocking capacitor (not shown).
[0094] FIG. 14 shows an electronic circuit (1400) in accordance with other embodiments of the present disclosure. With reference to FIGS. 11 and 14, the input matching network (1421) is an exemplary implementation of the input matching network (1121) of FIG. 11. The electronic circuit (1400) further comprises two output matching network (1430a, 1430b), each of which may be an exemplary implementation of any of the output matching elements (M.sub.1, . . . , M.sub.n) of FIG. 11. In other words, a combination of the two output matching networks (1430a, 1430b) is the counterpart of the output matching network (1130) of FIG. 11. Similarly, each of the transistors (T2a, T2b) may be an exemplary implementation of any of the electronic elements (E.sub.1, . . . , E.sub.n). Moreover, each of the resistors (RL, RL′) may represent any of the load elements (L1, . . . , L.sub.n) of FIG. 11. A combination of switches (S5, S6, S7) may be an exemplary implementation of the some of the switches included in the switching network (1140) of FIG. 11. With reference to FIGS. 12 and 14, the person skilled in the art will understand that the electronic circuit (1400) may also include switches (S.sub.1, . . . , S.sub.4) of FIG. 12 providing the same functionalities. Such switches are not shown in FIG. 14 for the sake of clarity
[0095] With reference to FIGS. 13-14, the principle of operation of the electronic circuit (1400) is similar to what was described with regards to electronic circuit (1300) of FIG. 13, except that there are two additional source-followers implemented using transistor (T4a) together with current source (Ia′) as well as transistor (T4b) together with its associated current source (Ib′). At the expense of additional DC currents due to current sources (Ia′, Ib′), such architecture provides improved output-to-output isolation by adding extra output buffer stages. Since transistors (T4a, T4b) drive the high-impedance gates of transistors (T3a, T3b) respectively, transistors (T4a, T4b) may not have current requirements that transistors (T3a, T3b) may have to drive 50 Ohm loads. Therefore, the DC current (Ia′) may be smaller than current (Ia) and DC current (Ib′) may be smaller than DC current (Ib). In single-mode operations where output-output isolation may not be required, transistors (T4a, T4b) may be bypassed by closing switches (S.sub.8, S.sub.9) respectively, and current sources (Ia′, Ib′) may be shut down.
[0096] Referring back to FIG. 11, the person skilled in the art will understand that the embodiments of FIGS. 12-14 represent exemplary implementations of the embodiment shown in FIG. 11. Without departing from the scope and spirit of the invention, further embodiments may be envisaged using various designs and concepts as disclosed previously and with regards to embodiments of FIGS. 4A-9. By way of example, and not of limitation, and with continued reference to FIG. 11, embodiments may be made wherein: [0097] the input matching network (1121) may be implemented using the input matching network (421) of FIG. 4A [0098] One or more matching elements of the plurality of matching elements (M.sub.1, . . . , M.sub.n) of the output matching network (1130) may be implemented using the output matching network (430) of FIG. 4A [0099] One or more matching elements of the plurality of matching elements (M.sub.1, . . . , M.sub.n) of the output matching network (1130) may be implemented using the output matching network (930) of FIG. 9 [0100] The switching network (1140) may be implemented using the switching network (440) of FIG. 4B, and based on any configurations as shown in the tables of FIGS. 5B-8B. [0101] One or more electronic elements of the plurality of electronic elements (E.sub.1, . . . , E.sub.n) of the LNA block (1122) may be implemented using a transistor, similar to what was described with regards to embodiments shown in FIGS. 12-14.
[0102] Making further reference to FIG. 11, and according to various embodiments of the present disclosure: [0103] All electronic elements of the plurality of electronic elements (E.sub.1, . . . , E.sub.n) may be the same. [0104] At least one electronic element of the plurality of electronic elements (E.sub.1, . . . , E.sub.n) may be different from other electronic elements of the plurality of electronic elements (E.sub.1, . . . , E.sub.n). [0105] Each electronic element of plurality of electronic elements (E.sub.1, . . . , E.sub.n) may be different from any other electronic element of the plurality of electronic elements (E.sub.1, . . . , E.sub.n). [0106] All output matching elements of the plurality of output matching elements (M.sub.1, . . . , M.sub.n) may be the same. [0107] At least one output matching element of the plurality of output matching elements (M.sub.1, . . . , M.sub.n) may be different from other output matching elements of the plurality of output matching elements (M.sub.1, . . . , M.sub.n). [0108] Each output matching element of the plurality of output matching elements (M.sub.1, . . . , M.sub.n) may be different from any other output matching elements of the plurality of output matching elements (M.sub.1, . . . , M.sub.n).
[0109] FIG. 15 shows an electronic circuit (1500) according to an embodiment of the present disclosure. The electronic circuit (1500) has some similarities with the electronic circuit (1100) of FIG. 11 and provides all the benefits associated with the electronic circuit (300) of FIG. 3 as detailed previously. Additionally, the electronic circuit (1500) may be configured to receive one or more input signal from inputs (in.sub.1, . . . , in.sub.k). Similar to what was described with regards to the electronic circuit (1100) of FIG. 11, the electronic circuit (1500) may be configured to provide output signals to one or more outputs (out.sub.1, . . . , out.sub.n), wherein ‘k’ and ‘n’ are integers larger than 1. The electronic circuit (1500) is essentially a multiple-input, multiple-output circuit providing all the benefits as described with regards to the electronic circuit (1100) of FIG. 11 as well as the capability of handling more than one input signal. According to embodiments of the present disclosure, the electronic circuit (1500) may be configured for: [0110] various single-mode operations involving an input signals received from any one of the inputs (in.sub.1, . . . , in.sub.k) to provide an output signal at any one of the outputs (out.sub.1, . . . , out.sub.n), and [0111] various split-mode operations involving T input signals received from any T inputs (in.sub.1, . . . , in.sub.k) to provide T output signals at any T outputs (out.sub.1, . . . , out.sub.n) wherein ‘i’ and ‘j’ are integers, and wherein ‘i’ is larger or equal to 1 and ‘j’ is larger or equal to ‘i’.
[0112] FIG. 16 shows an electronic circuit (1600) in accordance with an embodiment of the present disclosure where switches are not shown for an easier understanding of the figure. The electronic circuit (1600) is an exemplary implementation of the electronic circuit (1500) of FIG. 15. The electronic circuit (1600) is essentially a multiple-input, multiple-output circuit and may be configured to receive two input signals at inputs (in1, in2) and generate two output signals at outputs (out1, out2). Transistors (T1, T1′) are configured as common-source transistors and transistors (T2, T2′) are configured as cascade transistors. As also shown in FIG. 15, and similar to what was described previously, the split is initiated at cascode transistors, in other words at drains of transistors (T1, T1′). Transistors (T3, T3′) together with their respective current sources (Ia, Ia′) are source-followers used for improved output matching. According to embodiments of the disclosure, the electronic circuit (1600) may have the following modes of operation: [0113] Single-mode (in1 to out1): transistors (T1, T2, T3) are active and all other transistors are inactive. Similar to what was discussed with regards to FIGS. 1-15, a set of switches can may be implemented to allow transistors (T1, T2, T3) to be active, and all other transistors to be inactive. [0114] Single-mode (in1 to out2): transistors (T1, T2′, T3′) are active and all other transistors are inactive. Similar to what was discussed with regards to FIGS. 1-15, a set of switches may be implemented to allow transistors (T1′, T2′, T3) to be active, and all other transistors to be inactive. [0115] Single-mode (in2 to out1): transistors (T1′, T2, T3) are active and all other transistors are inactive. Similar to what was discussed with regards to FIGS. 1-15, a set of switches may be implemented to allow transistors (T1′, T2, T3) to be active, and all other transistors to be inactive. [0116] Single-mode (in2 to out2): transistors (T1′, T2′, T3′) are active and all other transistors are inactive. Similar to what was discussed with regards to FIGS. 1-15, a set of switches may be implemented to allow transistors (T1′, T2′, T3′) to be active, and all other transistors to be inactive. [0117] Split-mode (in1 to out1 and out2): transistors (T1, T2, T3, T2′, T3′) are active. Transistor (T1′) is inactive. Similar to what was discussed with regards to FIGS. 1-15, a set of switches may be implemented to allow transistors (T1, T2, T3, T2′, T3′) to be active, and transistor (T1′) to be inactive. [0118] Split-mode (in2 to out1 and out2): transistors (T1′, T2, T3, T2′, T3′) are active. Transistor (T1) is inactive. Similar to what was discussed with regards to FIGS. 1-15, a set of switches may be implemented to allow transistors (T1′, T2, T3, T2′, T3′) to be active, and transistor (T1) to be inactive.
[0119] The term “MOSFET”, as used in this disclosure, means any field effect transistor (FET) with an insulated gate and comprising a metal or metal-like, insulator, and semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.
[0120] As should be readily apparent to one of ordinary skill in the art, various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice and various embodiments of the invention may be implemented in any suitable IC technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, the invention may be implemented in other transistor technologies such as bipolar, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the inventive concepts described above are particularly useful with an SOI-based fabrication process (including SOS), and with fabrication processes having similar characteristics. Fabrication in CMOS on SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 50 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.
[0121] Voltage levels may be adjusted or voltage and/or logic signal polarities reversed depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functional without significantly altering the functionality of the disclosed circuits.
[0122] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, or parallel fashion.
[0123] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).
