SYSTEM AND METHOD FOR SUPERCONDUCTING MULTI-CHIP MODULE

Abstract

A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

Claims

1. An interconnect for connecting electronic circuits, comprising a plurality of cold-welded indium bonds, each indium bond comprising a pair of aligned opposing posts, each having post having an indium bump which is cold-welded at a temperature not greater than a melting temperature of the indium bump, and under a sufficient pressure to deform and cold-weld the indium bumps of the pair of aligned opposing posts.

2. The interconnect according to claim 1, wherein the temperature not greater than a melting temperature of the indium bump is a temperature of between 50° C. and 150° C.

3. The interconnect according to claim 1, wherein at least one electronic circuit comprises a cryogenic Josephson junction.

4. The interconnect of claim 1, further comprising a diffusion barrier under each respective indium bump.

5. The interconnect of claim 4, wherein the diffusion barrier comprises a superconducting compound selected from the group consisting of niobium nitride and titanium nitride.

6. The interconnect of claim 1, wherein the indium bumps are formed on a rear of an integrated circuit wafer with respect to electronic circuits fabricated on the wafer, and through-wafer vias enable electrical connection from the electronic circuit to the indium bumps on the opposite side of the wafer.

7. The interconnect of claim 1, wherein at least one opposing post comprises a copper post.

8. The interconnect of claim 1, wherein the electronic circuits comprise a plurality of electronic circuits bonded to a common carrier for a multi-chip module.

9. The method of claim 1, wherein at least one of the cold-welded indium bonds electrically connects to a superconducting ground layer.

10. The method of claim 1, wherein at least one indium bump is about 30 micrometers or less in diameter.

11. The method of claim 1, wherein at least one of the electronic circuits comprises a superconducting electronic device, and the cold-welded indium bonds are configured to carry an electrical current of at least about 10 mA without resistance at a temperature of less than 3.4° K.

12. The method of claim 1, wherein at least one of the electronic circuits comprises at least one qubit.

13. The method of claim 1, wherein at least one of the electronic circuits comprises a single-flux-quantum logic circuit.

14. The method of claim 1, wherein at least one of the electronic circuits comprises a superconducting electromagnetic sensor.

15. The method of claim 1, wherein the sufficient pressure comprises a uniaxial pressure of less than five thousand bars applied across the plurality of bumps for a period of less than one hour.

16. An electronic circuit module, comprising at least two electronic circuit substrates, each substrate having a plurality of posts, wherein the plurality of posts of the at least two electronic circuit substrates are aligned and bonded by a respective cold-welded indium bond between a respective pair of posts.

17. The electronic circuit module according to claim 16, wherein at least one electronic circuit substrate comprises a cryogenic Josephson junction.

18. The electronic circuit module according to claim 17, further comprising a superconducting diffusion barrier between the cold-welded indium bond and a supporting metal post.

19. The electronic circuit module according to claim 16, wherein the posts are disposed on a surface of an integrated circuit wafer opposite a fabricated electronic circuit on the integrated circuit wafer, with through-wafer vias connecting the fabricated integrated circuit to the cold-welded indium bond.

20. A multi-chip module comprising at least two superconducting electronic chips interconnected through a plurality of indium bumps, each indium bump comprising an indium coating on a post, wherein opposing indium bumps are compressed and heated below a melting temperature of the indium to form a cold-welded bond.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0094] FIGS. 1-7 illustrate a preferred embodiment of the steps to fabricate an array of indium bumps on a superconducting circuit.

[0095] FIG. 1 shows the deposition of a superconducting ground plane.

[0096] FIG. 2 shows the deposition of an insulating layer above the ground plane shown in FIG. 1, with holes through to the ground plane.

[0097] FIG. 3 shows the deposition of a superconducting wiring layer on the insulating layer of FIG. 2, forming vias to the ground plane, and a large contact pad.

[0098] FIG. 4 shows the deposition of a gold contact pad connecting to the superconducting wiring layer of FIG. 3.

[0099] FIG. 5 shows the deposition of copper posts on top of the superconducting vias of FIG. 4.

[0100] FIG. 6 shows the deposition of a diffusion stopping layer on top of the copper posts of FIG. 5.

[0101] FIG. 7 shows the deposition of indium bumps on top of the diffusion stopping layer of FIG. 6.

[0102] FIG. 8 shows the cross section of two bump bonds before bonding.

[0103] FIG. 9 shows a photograph of a carrier chip and a matching flip chip, each with an array of 2066 bumps.

[0104] FIG. 10 shows the flip-chip alignment configuration for bonding to the carrier chip.

[0105] FIG. 11 shows a cross-sectional view of two aligned bonds before full compression.

[0106] FIG. 12 shows a cross-sectional view of two aligned bonds after full compression.

[0107] FIG. 13 shows a measurement of the resistance of a series of bonds as a function of cryogenic temperature.

[0108] FIG. 14 shows a measurement of V(I) for a series of superconducting indium bonds, showing a large critical current.

[0109] FIG. 15 shows a measurement of the superconducting critical current of a series of bonds as a function of cryogenic temperature.

[0110] FIG. 16 shows a conceptual picture of a set of two bonded chips for a quantum computing application.

[0111] FIGS. 17A-17D show four alternative configurations for bonding a quantum circuit to a classical circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0112] FIGS. 1 through 7 show steps of a preferred embodiment of the method for preparing indium bump bonds on superconducting Nb chips, integrated into a prior-art method for fabricating superconducting integrated circuits. All of these are designed to be carried out on an entire 150 mm silicon wafer, although only a 2-mm portion of a single chip is shown for simplicity.

[0113] FIG. 1 shows Step 1, the deposition of a superconducting Nb ground plane comprising 100 nm of sputtered Nb on top of an oxidized silicon wafer, known in the Hypres standard process (www.hypres.com/foundry/niobium-process/; www.hypres.com/wp-content/uploads/2010/11/DesignRules-6.pdf; Yohannes, D., et al., “Parametric Testing of HYPRES Superconducting Integrated Circuit Fabrication Processes”, IEEE Trans. Applied Superconductivity, V. 17, No. 2, June 2007, pp. 181-186, www.hypres.com/wp-content/uploads/2010/12/Parameter-Testing.pdf) as the layer M0. The small circles show the ultimate locations of the indium bumps, which are not yet present.

[0114] FIG. 2 shows Step 2, the deposition of 150 nm of insulating silicon dioxide (SiO.sub.2, typically deposited using plasma-enhanced chemical vapor deposition, or PECVD) on top of the Nb, with an array of patterned holes to establish electrical conducting vias to the next conducting layer. The holes have diameters of about 30 μm or less.

[0115] FIG. 3 shows Step 3, the deposition of 300 nm of superconducting Nb that can represent a superconducting signal or a via to ground. Also shown is a large pad on the right that connects to this layer.

[0116] FIG. 4 shows Step 4, the deposition of a large contact pad for external connections, comprising 100 nm Ti and 100 nm Pd followed by 200 nm Au. This establishes a well-adhering pad for external contacts from gold-plated pins.

[0117] Steps 1 through 4 comprise steps similar to the fabrication of a prior-art superconducting integrated circuit. Not shown are other standard steps of the prior-art methods, including depositing and defining Josephson junctions of Nb/Al/AlOx/Nb, using controlled oxidation and anodization, depositing a resistive layer such as Mo, additional wiring layers, and steps of planarization. Also, in each case whenever a conducting film is deposited on a sample that has been patterned outside the vacuum system, an initial cleaning step in an argon plasma may be used to ensure unoxidized interfaces.

[0118] FIG. 5 shows Step 5, the evaporation deposition of an array of 2 μm thick Cu posts on top of the small Nb contacts. Note that the Cu post has a slightly smaller diameter than the Nb contact, leaving a Nb ring around it. These Cu posts can be on ground contacts or signal contacts. The use of Cu is not unique; another metal that is not deformable (or less deformable that the indium under the compression conditions) would also be acceptable, such as Nb, Mo, Ti, Au, etc.

[0119] FIG. 6 show Step 6, the deposition of 100 nm of a diffusion stopping layer (DSL) on top of the Cu posts and the Nb ring around each post. Preferred DSL materials include NbN and TiN, both of which can be prepared by reactive sputtering in a gas that includes nitrogen.

[0120] FIG. 7 shows Step 7, the evaporation deposition of 2 μm of indium on top of the DSL. Pure indium is preferred, since indium alloys tend to have a multi-phase microstructure that is harder and more brittle. The metallized patterns may be etched after deposition to form the isolated regions on top of other features.

[0121] FIG. 8 shows the cross section of two of the bumps prepared according to Steps 5 through 7 above, before the chips are pressed together, showing the indium bump, diffusion stopping layer, and copper post on top of the Nb contact. The numbers on the left indicate the approximate layer thicknesses in nm for a preferred embodiment.

[0122] FIG. 9 shows a photograph of a 10 mm carrier chip and a 5 mm flip chip, each with 2066 bumps, matching on both chips. These bumps comprise 1000 signal bumps (25 rows of 40 bumps each, 30 μm in diameter with 80 μm pitch) alternating with 1066 ground bumps. The carrier chip has gold-plated ground and signal contacts around its periphery, for external biasing and signal measurement. All 1000 signal bumps could be measured at the same time, or any of the 25 rows could be measured independently. Two other similar test structures were also tested using carrier and flip chips of the same size: The first structure had 300 signal bumps (15 rows of 20 bumps each, 30 μm in diameter with 130 μm pitch) alternating with 366 ground bumps, where all signal bumps could be measured together, or with independent rows. The second structure had 2691 signal bumps (39 rows of 69 bumps each, 15 μm in diameter with 50 μm pitch) alternating with 3353 ground bumps.

[0123] After removal of the wafer from the deposition system, the individual chips are separated (diced) using a commercial dicing machine. If there will be a significant delay before flip-chip bonding, the chips should be maintained in an environment that minimizes oxidation of the indium surfaces. The presence of significant oxide layers on indium surfaces may reduce the reliability of the method. For example, the chips may be immersed in a bath of methanol. Alternatively, just before bonding, the indium bumps may be subjected to an argon plasma etch to remove an accumulated surface oxide.

[0124] FIG. 10 shows how the bumps on the flip chip are aligned with the corresponding bumps on the carrier chip, with the help of the small alignment marks noted. This may be carried out using a commercial flip-chip bonder, such as the Karl Suss MicroTec FC-150, which permits micron alignment resolution. This bonder also allows controlled compression and temperature. For each structure, the chips were heated to about 75-125° C., using a force up to 20 kg (i.e., 200 Nt or 44 lb) for a period of about 15 minutes. Given the contact area of the bonds, this force corresponded to a uniaxial pressure up to several thousand bars.

[0125] FIG. 11 provides a cross-sectional view of aligned indium bumps as compression is initiated, with a thick layer of In between the two DSL/copper posts. Thicknesses of layers are not drawn to scale.

[0126] FIG. 12 provides a cross-section of aligned bumps as compression is completed, with most of the indium between the two DSL/copper posts squeezed out. Since the DSL/Cu is not compressed, this provides a hard stop for the separation of the two chips, about 4μm for the steps presented. While current can flow through the Cu posts in the resistive state, the superconducting indium shorts out the C.u below 3.4° K, providing a fully superconducting current path. Thicknesses of layers are not drawn to scale.

[0127] FIG. 13 shows the resistance of a series of In bonds as a function of temperature. The resistance drops sharply when the Nb goes superconducting at 9° K, and drops to zero when the In goes superconducting at 3.4° K.

[0128] FIG. 14 shows the current-voltage curve V(I) for a series of In bonds at 3° K, showing a sharp rise in voltage at the critical current of 15 mA. The large local power dissipation then heats up the In above its critical temperature 3.4° K, until the current is lowered down to 3 mA, when the voltage drops to zero. This sort of hysteresis related to local heating is characteristic of current-driven transitions in superconducting wires.

[0129] FIG. 15 shows the critical current of In bonds as a function of temperature below 3.4° K, showing a typical dependence rising as the temperature is cooled further. Any operating temperature at about 3° K. or below would be compatible with fully superconducting interconnects.

[0130] These tests were carried out for chips mounted on a cryocooler, a cryogenic refrigerator that uses helium as a working fluid, designed to cool down to temperatures as low as 3° K. Even lower temperatures can be achieved if the working fluid comprises the isotope helium-3, especially if the refrigerator is configured as a helium dilution refrigerator, which can achieve temperatures less than 0.1° K.

[0131] The tests based on the chips fabricated according to the disclosed optimized processes and parameters demonstrated very high yields on multiple chips, each with thousands of bonds. Further, the results were duplicated with multiple thermal cycles between room temperature and 3° K, indicating robust and reproducible contacts.

[0132] FIG. 16 provides a conceptual picture of a two-chip package, where one chip comprises superconducting quantum bits (qubits), and the other comprises single-flux-quantum control and readout circuits. Each of these chips might be manufactured with a distinct process, as long as both may be combined with indium bump bonds and copper posts. For example, the qubit chip might be prepared using aluminum Josephson junctions and NbTi wiring for transmon qubits, while the control chip might be prepared with Nb Josephson junctions and Nb wiring for energy-efficient SFQ circuits. The entire package could operate at very low temperatures (much less than 1° K) typical of superconducting quantum computing. Further, a three-dimensional quantum computing package need not be limited to two chips. One could also have a multi-chip module comprising a plurality of flip chips on a single carrier.

[0133] A further set of preferred embodiments for quantum-classical MCMs is illustrated in FIGS. 17A-17D. The simplest of the configurations is shown in FIG. 17A, where the quantum circuits at the bottom of the quantum chip are in close proximity to the classical circuits of the classical chip. There may be a concern that classical SFQ circuits may generate some hot electrons (excited quasiparticles), which may migrate to the quantum circuits and degrade their performance. However, as mentioned above, the presence of the copper posts in the bonds between the classical and quantum circuits may tend to trap at least a significant fraction of the excited quasiparticles, keeping them from contaminating the quantum circuits.

[0134] Furthermore, the classical and quantum circuits may be further separated by placing them on opposite sides of the chips, as shown in FIGS. 17B, 17C, and 17D. This would likely reduce further any remaining deleterious effects of the excited quasiparticles. These latter structures may be somewhat more complex to manufacture, requiring etching through-wafer vias, but similar vias are well known in silicon chip manufacturing. These through-wafer vias can be coated with a superconducting film, such as Nb, Al, or In, enabling a superconducting bias current or electrical signal to be transmitted from one side of the chip to the other, without loss or dissipation. Depending on the desired configuration, the through vias may be present in either the classical chip, or the quantum chip, or both. In some cases, it may be desirable to include circuits on both sides of one or more chips.

[0135] An alternative application of this packaging technology might be for classical supercomputers, with large numbers of superconducting microprocessors operating in parallel at frequencies of 50-100 GHz. This would also require close integration with cryogenic fast cache memory chips in the same cryogenic environment. One can envision, for example, a set of multi-chip modules, each comprising both cryogenic processors and memory, as well as cryogenic input-output chips that communicate to slower processors and memory at higher temperatures.

[0136] A further alternative application of this packaging technology might be for superconducting sensor arrays, which have been demonstrated for magnetic field detection, imaging arrays for astronomy and high-energy physics, and biomedical imaging. Such sensor arrays may further be integrated with superconducting digitizers, digital signal processors, and digital controllers, preferably in the same cryogenic environment as the sensors. This would require a set of multi-chip modules combining sensor chips with digital processing chips.

[0137] While superconducting multichip modules and indium bonding have been disclosed in the prior art, the present technology presents a substantial improvement. Much of the prior art focuses on solder reflow at moderately high temperatures, which would alter the precise parameters of the sensitive Josephson junctions on the chips. Other prior art uses unheated cold-welding of indium, which we have found is impractical for scaling to large numbers of bonds, because that would require pressures that are so large as to risk damaging or cracking the chips or substrates. We have found that a good compromise is an intermediate processing temperature about 75-125° C., but preferably less than 150° C., where the indium is somewhat softer, and neither the temperature nor the pressure risks damage to the chips.

[0138] Another aspect of the prior art of indium bonding is that diffusion and alloying was favored, because the alloy is harder and achieves a more rigid bond. On the contrary, the present invention attempts to reduce or eliminate diffusion and alloying using a diffusion stopping layer (DSL) between the indium and all other metals. This suppresses the formation of brittle intermetallics that would limit plastic flow of the In around the Cu post. Also, the preferred DSL is also superconducting (such as NbN and TiN), so that it may form a sharp superconducting interface between the In and the Nb.

[0139] Other devices, apparatus, systems, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.