ASYMMETRICALLY ANGLED GATE STRUCTURE AND METHOD FOR MAKING SAME

Abstract

A high electron mobility transistor (HEMT) includes a substrate; a source on the substrate; a drain on the substrate spaced from the source; and a gate between the source and the drain, wherein the gate has a stem contacting the substrate, the stem having a source side surface and a drain side surface, wherein a source side angle is defined between the source side surface and an upper planar surface of the substrate and a drain side angle is defined between the drain side surface and the upper planar surface of the substrate, and wherein the source side angle and the drain side angle are asymmetric. Methods for making the HEMT are also disclosed.

Claims

1. A high electron mobility transistor comprising: a substrate; a source on the substrate; a drain on the substrate spaced from the source; and a gate between the source and the drain, wherein the gate comprises a stem contacting the substrate, the stem having a source side surface and a drain side surface, wherein a source side angle is defined between the source side surface and an upper planar surface of the substrate and a drain side angle is defined between the drain side surface and the upper planar surface of the substrate, and wherein the source side angle and the drain side angle are asymmetric.

2. The transistor of claim 1, wherein the source side surface and the drain side surface are non-linear surfaces.

3. The transistor of claim 2, wherein the non-linear surfaces are non-linear from a point of contact with the upper planar surface of the substrate.

4. The transistor of claim 1, wherein the source side surface and the drain side surface are defined by field plates.

5. The transistor of claim 1, wherein the source side angle is greater than the drain side angle.

6. The transistor of claim 1, wherein the source side angle is between 25 and 90° and the drain side angle is smaller than the source side angle.

7. The transistor of claim 6, wherein the source side angle is between 45 and 90°.

8. The transistor of claim 6, wherein the source side angle is between 70 and 90°.

9. The transistor of claim 6, wherein the drain side angle is between 25 and 70°.

10. The transistor of claim 6, wherein the drain side angle is between 25 and 50°.

11. The transistor of claim 1, wherein the gate is a metallic structure formed from one or more metals selected from the group consisting of gold, platinum, nickel and combinations and alloys thereof.

12. A method for making a transistor, comprising the steps of: applying a layer of photoresist to a substrate coated with ohmic material defining a source and a drain; removing portions of the photoresist to define a central space between a first strip of photoresist and a second strip of photoresist, wherein the first strip and the second strip have different widths; reflowing the photoresist to create reflow angles on either side of the central space; and applying a gate metal to the central space.

13. The method of claim 12, further comprising the steps of: applying a further layer of photoresist over the layer of photoresist after the reflowing step; removing a portion of the further layer to expose the central space; applying gate metal to the further layer and the central space; and removing the layer of photoresist and the further layer of photoresist to produce a substrate having the source, the drain and a gate having a stem contacting the substrate, a source side field plate, and a drain side field plate, wherein the source side field plate and the drain side field plate are defined by non-linear surfaces, and wherein a source side angle is defined between the source side field plate and an upper planar surface of the substrate and a drain side angle is defined between the drain side field plate and the upper planar surface of the substrate, and wherein the source side angle and the drain side angle are asymmetric.

14. The method of claim 12, wherein the removing step comprises removing a central portion of the layer of photoresist to define the central space, removing a source side portion of the layer of photoresist to define a source side strip of photoresist having a first width, and removing a drain side portion of the layer to photoresist to define a drain side strip of photoresist having a second width.

15. The method of claim 12, wherein the photoresist is a material selected from the group consisting of polymethyl methacrylate (PMMA), phenol-formaldehyde resin, and combinations thereof.

16. The method of claim 12, wherein the reflowing step comprises exposing the layer of photoresist to a temperature of between 100 and 200° C. for a period of time of between 1 and 10 minutes, whereby the photoresist melts and flows to a shape dictated by surface tension of the photoresist.

17. A method for making a transistor, comprising the steps of: applying a layer of photoresist to a substrate coated with ohmic material defining a source and a drain, and also coated with a dielectric layer; removing portions of the photoresist to define a central space between a first strip of photoresist and a second strip of photoresist, wherein the first strip and the second strip have different widths; reflowing the photoresist to create reflow angles on either side of the central space; etching the dielectric layer through the central space to define a dielectric central space having sides that are at angles defined by the reflow angles; and applying a gate metal to the dielectric central space.

18. The method of claim 17, further comprising the steps of: after the reflowing step, applying a further layer of photoresist over the layer of photoresist; and removing a portion of the further layer to expose the central space.

19. The method of claim 17, further comprising the steps of: after the etching step, stripping the further layer of photoresist and the layer of photoresist from the dielectric layer; applying an additional layer of photoresist over the dielectric layer and the dielectric central space; removing a portion of the additional layer of photoresist to expose the dielectric central space; applying gate metal to the additional layer and the dielectric central space; and removing the additional layer gate metal on the additional layer to produce a substrate having the source, the drain and a gate having a stem contacting the substrate, a source side surface of the stem, and a drain side surface of the stem, wherein a source side angle is defined between the source side surface and an upper planar surface of the substrate and a drain side angle is defined between the drain side surface and the upper planar surface of the substrate, and wherein the source side angle and the drain side angle are asymmetric.

20. The method of claim 17, wherein the removing step comprises removing a central portion of the layer of photoresist to define the central space, removing a source side portion of the layer of photoresist to define a source side strip of photoresist having a first width, and removing a drain side portion of the layer to photoresist to define a drain side strip of photoresist having a second width.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] A detailed description of one or more embodiments of the disclosure follows, with reference to the attached drawings, wherein:

[0029] FIG. 1 schematically illustrates components of an HEMT;

[0030] FIG. 2 illustrates a non-limiting configuration of a PHEMT having an asymmetrically angled gate structure;

[0031] FIG. 3 is an enlarged portion of FIG. 2 to illustrate specific aspects of the disclosure in greater detail;

[0032] FIGS. 4-10 illustrate a method for making an HEMT;

[0033] FIGS. 11-21 illustrate a further non-limiting configuration of a method for making an HEMT.

[0034] Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0035] The present disclosure relates to high electron mobility transistors (HEMTs) and pseudomorphic high electron mobility transistors (PHEMTs), and to a method for making same.

[0036] FIG. 1 schematically illustrates a PHEMT structure 10 including a substrate 12, a source 14 and a drain 16. Positioned between source 14 and drain 16 is a gate 18 as is well known and understood in the art. Substrate 12 is typically a multilayer structure incorporating a junction between two materials with different band gaps. One non-limiting example of suitable material for substrate 12 is a gallium antimony, or GaAs material. This material can be utilized in different forms, for example in combination with aluminum (AlGaAs), or indium (InGaAs) to produce the desired performance in the junction between the materials. The structure is referred to as pseudomorphic because the hetero layers of material are thin enough not to keep their own crystal lattice structure. Rather, these layers of material assume the structure of surrounding material. The disclosure set forth herein is applicable to both HEMT and PHEMT structures. Further, numerous additional layers can be incorporated into substrate 12 for other related or additional reasons, and all such multiple and additional layer structures are considered to fall within the term “substrate” as used herein.

[0037] Source 14 is a layer of ohmic metal. Non-limiting examples of suitable ohmic metals include gold, platinum, nickel, tantalum, tantalum nitride, tungsten, aluminum and their associated alloys.

[0038] Drain 16 is also a layer of ohmic metal such as can be the same type of metals as are suitable for the source. Thus, non-limiting examples of suitable ohmic metals include gold, platinum, nickel, tantalum, tantalum nitride, tungsten, aluminum and their associated alloys. The metals can be the same for both source and drain, or can be different.

[0039] Gate 18 is shown in FIG. 1 having a conventional T shape, with a narrow stem 20 and a wider top 22. Stem 20 in FIG. 1 has equally and oppositely sloped straight sides 24, 26. The position of sides 24, 26 relative to the substrate surface and to each other impacts the possibility of large spikes in electric field at the gate edge, as well as capacitance across the gate.

[0040] Gate 18 has top 22 as shown, with a lateral dimension or width that is greater than width of the stem, and with a vertical dimension or height that is less than the width. The width and height of top 22 impacts resistance in the overall configuration.

[0041] A contact point 28 between the bottom surface of stem 20 and the upper surface of substrate 12 is typically preferred to be as small as possible. Further, sides 24, 26 at a point of contact with substrate 12 are typically kept as close as possible to perpendicular. As set forth above, however, a perfectly vertical T shaped gate can result in a large spike in electric field at the gate edge, and this large spike can be catastrophic to the device.

[0042] FIGS. 2 and 3 illustrate a non-limiting configuration of a portion of a PHEMT 100 according to the disclosure. Gate 102 is shown on a substrate 104 and has a source facing side 106 and a drain facing side 108. Sides 106, 108 are non-linear. In the configuration illustrated in FIGS. 2 and 3, sides 106, 108 are curved along an arc.

[0043] Sides 106, 108 are asymmetrically positioned relative to substrate 104. In this case, side 106 facing the source is angled closer to perpendicular than side 108 which faces the drain. This allows for side 106 to provide a near-vertical angle on the source side, which reduces capacitance, while side 108 is at a shallower angle on the drain side, which produces smoothing field plate effects, also as desired. This configuration would be difficult to accomplish utilizing conventional manufacturing methods because resist and photoresist materials used to define the space or gap for the gate produce symmetrical slant such as is shown in FIG. 1.

[0044] It should be appreciated that FIGS. 2 and 3 show gate 102 with strips of photoresist 110, 112 that are used to form gate 102 according to a method that is further described below. It will further be appreciated that photoresist 110, 112 can be removed after formation of gate 102.

[0045] FIG. 3 is an enlarged portion of FIG. 2 and further illustrates specific details of the configuration, shape and angle of sides 106, 108 in one configuration of a gate according to the disclosure. Side 106 in this configuration is non-linear, and specifically is a curved surface that is concave facing generally toward the source. The overall curved surface 106 is at an angle, or is slanted, relative to substrate 104, specifically relative to an upper flat surface 114 of substrate 104. Because sides 106, 108 in this embodiment are formed around curved surfaces of adjacent photoresist, the angle of sides 106, 108 can best be measured as the contact angle of photoresist that defined the shape of the side. Thus, if side 106 is formed by deposition onto photoresist that has a contact angle with surface 114 of 80°, then the angle A of side 106 relative to substrate 104 will be considered to be 80°. Similarly, side 108 is non-linear and in this configuration curved surface that is concave facing generally toward the drain. Side 108 is also formed by deposition onto photoresist that has a contact angle with surface 114 of substrate 104. Thus, the angle B of side 108 is considered to be the contact angle of the photoresist onto which side 108 is deposited. For example, if this photoresist has/had a contact angle of 40°, then angle B of side 108 as referred to herein will be considered to be 40°. Contact angles A, B in the embodiment of FIG. 3 are shown with respect to lines X, Y and surface 114.

[0046] In one non-limiting configuration, angle A on the source side is greater than angle B on the drain side. Angle A can be between 25 and 90°. In a further non-limiting configuration, angle A can be between 45 and 90°, and further can be between 70 and 90°. Angle B can also broadly be between 25 and 90°, but in one configuration can be between 25 and 70°, and further can be between 25 and 50°. Within these ranges, again, angle A is greater than angle B. As set forth above, this helps to produce the desired low capacitance while still producing field plate effect on the drain side.

[0047] It should be appreciated that while the angles referred to in this embodiment are contact angles, in other configurations the sides 106, 108 may be straight, in which case the angle is simply the angle of the straight side relative to the upper surface of the substrate. Such a configuration is further discussed below. In any of these configurations, the drain side angle B is advantageously less than 90°.

[0048] FIGS. 4-10 illustrate one non-limiting example of a method by which the gate structure illustrated in FIGS. 2 and 3 can be made. FIG. 4 shows a substrate or wafer 104 that has been previously coated with ohmic metal to form what will be source 14 and drain 16. Following known techniques, a layer 116 of resist or photoresist is applied or spin coated over surface 114 of substrate 104, and can also be coated over source 14 and drain 16.

[0049] Layer 116 is then exposed and developed to produce a stem channel 118, or central space, and at least two external channels 120, 122. This combination of channels produces strips 110, 112 of photoresist that have different widths. These strips are referred to as assist features, and this configuration is shown in FIG. 5. This step can be accomplished utilizing any known combination of resist or photoresist material and method for removing or etching same. For example, suitable materials for the photoresist can be selected from the group consisting of polymethyl methacrylate (PMMA), phenol-formaldehyde resin, and combinations thereof.

[0050] With reference to FIG. 6, the structure of FIG. 5 can be subjected to heat, for example in a photoresist baking step, to reflow the photoresist material and thereby generate the shapes of strips 110, 112 between channels as shown in FIG. 6. The resulting shape of reflowed photoresist depends upon the surface tension of the material and also upon the starting width of the strip of photoresist. This is why the outer channels 120, 122 are formed, as external assist features, as they generate a strip of photoresist on one side that has a different width than on the other side of stem channel 118. A narrower strip of photoresist will produce a steeper contact angle in a gate stem formed in the stem channel, and a wider strip of photoresist will produce a more shallow contact angle in the gate stem formed in this manner. Thus, it can be advantageous to configure a strip 112 of photoresist on the drain side that is wider than the strip 110 of photoresist on the source side.

[0051] Referring to FIG. 7, a second layer 124 of photoresist can be applied or spin coated over the top of the first layer 116 and into the channels 118, 120, 122. Second layer 124 can be produced from the same photoresist material, or can advantageously be produced from a photoresist that is more sensitive to etching force than the first material. This allows for a portion or channel of second layer 124 to be removed or etched away without removing the underlying first photoresist layer 116, to the extent that this might be desired. As shown in FIG. 8, a channel 126 is formed or etched in layer 124 at a location that exposes the underlying stem channel 118 and portions of the strips of photoresist of layer 116 that surround and define stem channel 118.

[0052] A layer 128 of gate metal can then be deposited over the entire structure, including over layer 124 of photoresist and into stem channel 118, and over surfaces of layer 116 of photoresist that are exposed in channel 126. Alternatively, the gate metal can be deposited only at the location of stem channel 118. This gate metal can be deposited, for example, using vapor deposition, or evaporation, or using any other known technique. Finally, as shown in FIG. 10, excess metal and photoresist of layers 116 and 124 are removed, for example by stripping from wafer or substrate 104, to leave gate 102 with asymmetrically sloped sides as shown. It should be appreciated that in the illustrations of FIGS. 4-10, the steeper angle of gate 102 is shown facing to the right, because a narrower strip of photoresist as assist feature was utilized on that side. Thus, in this configuration, this structure would have source on the right side, and drain on the left.

[0053] It should be appreciated that any combination of angles on source and drain side of the stem can be produced following this method by selecting the proper combination of widths of the assist strips on either side of the stem channel.

[0054] FIGS. 11-21 illustrate another method for manufacturing a gate for an HEMT where the gate has asymmetrically angled sides.

[0055] Referring to FIG. 11, a substrate 104 can be provided with ohmic material for source 14 and drain 16, and then coated with a layer 128 of gate dielectric material such as silicon carbide or high k material, for example. Then, a first layer 130 of photoresist can be deposited over dielectric layer 128.

[0056] FIG. 12 shows the structure after exposure of photoresist layer 128 to form a stem channel 132 and two spaced external channels 134, 136 on either side of stem channel 132. As with the embodiment of FIGS. 4-10, channels 134, 136 are positioned at different spacing from stem channel 132, such that two strips 138, 140 of photoresist are positioned on either side of stem channel 132, and the two strips 138, 140 are of different width.

[0057] FIG. 13 shows the structure after baking or otherwise reflowing the photoresist such that strips 138, 140 reach their glass transition temperature and reflow to take on a rounded shape that is driven by surface tension and other properties of the material. As shown, the wider strip generates a reflowed shape that has a smaller or more shallow contact angle than the more narrow strip.

[0058] FIG. 14 shows the structure after a second layer 142 of photoresist is applied over the reflowed first layer 130. This second layer 142 can then be exposed or etched away to expose stem channel 132 as shown in FIG. 15.

[0059] At this stage, dielectric layer 128 can be etched through stem channel 132 to form a central channel 144 in dielectric layer 128. Because this etching is accomplished through a space defined between differently angled walls of strips 138, 140, central channel 144 has sides 146, 148 that are differently angled relative to substrate 104. This is shown in FIG. 16.

[0060] FIG. 17 shows the structure after layers 116, 124 of photoresist are removed, leaving the dielectric with central channel 144. A third layer 146 of photoresist can then be positioned or deposited over dielectric layer 128 and central channel 144 as shown in FIG. 18, and this third layer 146 can then be etched or exposed to form an opening 148 over central channel 144. This exposure or etching can be conducted using a mask technique or any other technique, the result being an opening 148 that is wider than central channel 144. Further, opening 148 can be defined by walls 150, 152 that have a spacing that increases closer to dielectric layer 128 (See FIG. 19). Gate metal 150 can then be deposited over the structure and into opening 148 and central channel 144 as shown in FIG. 20. A gate 152 having the expected shape is shown being formed as a result. Finally, third layer of dielectric 146 as well as excess gate metal 150 can be removed, leaving an HEMT structure 100 as shown in FIG. 21. As can be seen, gate 152 has a stem 154 and top 156 which is wider than stem 154. As with the configuration of FIGS. 2 and 3, stem 154 is defined by sides 158, 160 that are at different angles relative to substrate 104. The different angles of these sides can advantageously be within the ranges for angles A and B as discussed above. However, in this configuration the sides 158, 160 are substantially linear. Further, rather than being defined within the substrate, in this case gate 152 is formed with stem 154 contacted on either side in dielectric layer 128.

[0061] One or more embodiments of the present disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, different materials and configurations could be utilized, and transistor structures having different shapes or configurations may benefit from this disclosure. Accordingly, other embodiments are within the scope of the following claims.